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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Core IIO driver for Bosch BMA400 triaxial acceleration sensor.
0004  *
0005  * Copyright 2019 Dan Robertson <dan@dlrobertson.com>
0006  *
0007  * TODO:
0008  *  - Support for power management
0009  *  - Support events and interrupts
0010  *  - Create channel for step count
0011  *  - Create channel for sensor time
0012  */
0013 
0014 #include <linux/bitfield.h>
0015 #include <linux/bitops.h>
0016 #include <linux/device.h>
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/mutex.h>
0020 #include <linux/regmap.h>
0021 #include <linux/regulator/consumer.h>
0022 #include <linux/slab.h>
0023 
0024 #include <asm/unaligned.h>
0025 
0026 #include <linux/iio/iio.h>
0027 #include <linux/iio/buffer.h>
0028 #include <linux/iio/events.h>
0029 #include <linux/iio/trigger.h>
0030 #include <linux/iio/trigger_consumer.h>
0031 #include <linux/iio/triggered_buffer.h>
0032 
0033 #include "bma400.h"
0034 
0035 /*
0036  * The G-range selection may be one of 2g, 4g, 8, or 16g. The scale may
0037  * be selected with the acc_range bits of the ACC_CONFIG1 register.
0038  * NB: This buffer is populated in the device init.
0039  */
0040 static int bma400_scales[8];
0041 
0042 /*
0043  * See the ACC_CONFIG1 section of the datasheet.
0044  * NB: This buffer is populated in the device init.
0045  */
0046 static int bma400_sample_freqs[14];
0047 
0048 static const int bma400_osr_range[] = { 0, 1, 3 };
0049 
0050 /* See the ACC_CONFIG0 section of the datasheet */
0051 enum bma400_power_mode {
0052     POWER_MODE_SLEEP   = 0x00,
0053     POWER_MODE_LOW     = 0x01,
0054     POWER_MODE_NORMAL  = 0x02,
0055     POWER_MODE_INVALID = 0x03,
0056 };
0057 
0058 enum bma400_scan {
0059     BMA400_ACCL_X,
0060     BMA400_ACCL_Y,
0061     BMA400_ACCL_Z,
0062     BMA400_TEMP,
0063 };
0064 
0065 struct bma400_sample_freq {
0066     int hz;
0067     int uhz;
0068 };
0069 
0070 enum bma400_activity {
0071     BMA400_STILL,
0072     BMA400_WALKING,
0073     BMA400_RUNNING,
0074 };
0075 
0076 struct bma400_data {
0077     struct device *dev;
0078     struct regmap *regmap;
0079     struct regulator_bulk_data regulators[BMA400_NUM_REGULATORS];
0080     struct mutex mutex; /* data register lock */
0081     struct iio_mount_matrix orientation;
0082     enum bma400_power_mode power_mode;
0083     struct bma400_sample_freq sample_freq;
0084     int oversampling_ratio;
0085     int scale;
0086     struct iio_trigger *trig;
0087     int steps_enabled;
0088     bool step_event_en;
0089     bool activity_event_en;
0090     unsigned int generic_event_en;
0091     /* Correct time stamp alignment */
0092     struct {
0093         __le16 buff[3];
0094         u8 temperature;
0095         s64 ts __aligned(8);
0096     } buffer __aligned(IIO_DMA_MINALIGN);
0097     __le16 status;
0098     __be16 duration;
0099 };
0100 
0101 static bool bma400_is_writable_reg(struct device *dev, unsigned int reg)
0102 {
0103     switch (reg) {
0104     case BMA400_CHIP_ID_REG:
0105     case BMA400_ERR_REG:
0106     case BMA400_STATUS_REG:
0107     case BMA400_X_AXIS_LSB_REG:
0108     case BMA400_X_AXIS_MSB_REG:
0109     case BMA400_Y_AXIS_LSB_REG:
0110     case BMA400_Y_AXIS_MSB_REG:
0111     case BMA400_Z_AXIS_LSB_REG:
0112     case BMA400_Z_AXIS_MSB_REG:
0113     case BMA400_SENSOR_TIME0:
0114     case BMA400_SENSOR_TIME1:
0115     case BMA400_SENSOR_TIME2:
0116     case BMA400_EVENT_REG:
0117     case BMA400_INT_STAT0_REG:
0118     case BMA400_INT_STAT1_REG:
0119     case BMA400_INT_STAT2_REG:
0120     case BMA400_TEMP_DATA_REG:
0121     case BMA400_FIFO_LENGTH0_REG:
0122     case BMA400_FIFO_LENGTH1_REG:
0123     case BMA400_FIFO_DATA_REG:
0124     case BMA400_STEP_CNT0_REG:
0125     case BMA400_STEP_CNT1_REG:
0126     case BMA400_STEP_CNT3_REG:
0127     case BMA400_STEP_STAT_REG:
0128         return false;
0129     default:
0130         return true;
0131     }
0132 }
0133 
0134 static bool bma400_is_volatile_reg(struct device *dev, unsigned int reg)
0135 {
0136     switch (reg) {
0137     case BMA400_ERR_REG:
0138     case BMA400_STATUS_REG:
0139     case BMA400_X_AXIS_LSB_REG:
0140     case BMA400_X_AXIS_MSB_REG:
0141     case BMA400_Y_AXIS_LSB_REG:
0142     case BMA400_Y_AXIS_MSB_REG:
0143     case BMA400_Z_AXIS_LSB_REG:
0144     case BMA400_Z_AXIS_MSB_REG:
0145     case BMA400_SENSOR_TIME0:
0146     case BMA400_SENSOR_TIME1:
0147     case BMA400_SENSOR_TIME2:
0148     case BMA400_EVENT_REG:
0149     case BMA400_INT_STAT0_REG:
0150     case BMA400_INT_STAT1_REG:
0151     case BMA400_INT_STAT2_REG:
0152     case BMA400_TEMP_DATA_REG:
0153     case BMA400_FIFO_LENGTH0_REG:
0154     case BMA400_FIFO_LENGTH1_REG:
0155     case BMA400_FIFO_DATA_REG:
0156     case BMA400_STEP_CNT0_REG:
0157     case BMA400_STEP_CNT1_REG:
0158     case BMA400_STEP_CNT3_REG:
0159     case BMA400_STEP_STAT_REG:
0160         return true;
0161     default:
0162         return false;
0163     }
0164 }
0165 
0166 const struct regmap_config bma400_regmap_config = {
0167     .reg_bits = 8,
0168     .val_bits = 8,
0169     .max_register = BMA400_CMD_REG,
0170     .cache_type = REGCACHE_RBTREE,
0171     .writeable_reg = bma400_is_writable_reg,
0172     .volatile_reg = bma400_is_volatile_reg,
0173 };
0174 EXPORT_SYMBOL_NS(bma400_regmap_config, IIO_BMA400);
0175 
0176 static const struct iio_mount_matrix *
0177 bma400_accel_get_mount_matrix(const struct iio_dev *indio_dev,
0178                   const struct iio_chan_spec *chan)
0179 {
0180     struct bma400_data *data = iio_priv(indio_dev);
0181 
0182     return &data->orientation;
0183 }
0184 
0185 static const struct iio_chan_spec_ext_info bma400_ext_info[] = {
0186     IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma400_accel_get_mount_matrix),
0187     { }
0188 };
0189 
0190 static const struct iio_event_spec bma400_step_detect_event = {
0191     .type = IIO_EV_TYPE_CHANGE,
0192     .dir = IIO_EV_DIR_NONE,
0193     .mask_separate = BIT(IIO_EV_INFO_ENABLE),
0194 };
0195 
0196 static const struct iio_event_spec bma400_activity_event = {
0197     .type = IIO_EV_TYPE_CHANGE,
0198     .dir = IIO_EV_DIR_NONE,
0199     .mask_shared_by_type = BIT(IIO_EV_INFO_ENABLE),
0200 };
0201 
0202 static const struct iio_event_spec bma400_accel_event[] = {
0203     {
0204         .type = IIO_EV_TYPE_MAG,
0205         .dir = IIO_EV_DIR_FALLING,
0206         .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
0207                        BIT(IIO_EV_INFO_PERIOD) |
0208                        BIT(IIO_EV_INFO_HYSTERESIS) |
0209                        BIT(IIO_EV_INFO_ENABLE),
0210     },
0211     {
0212         .type = IIO_EV_TYPE_MAG,
0213         .dir = IIO_EV_DIR_RISING,
0214         .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
0215                        BIT(IIO_EV_INFO_PERIOD) |
0216                        BIT(IIO_EV_INFO_HYSTERESIS) |
0217                        BIT(IIO_EV_INFO_ENABLE),
0218     },
0219 };
0220 
0221 #define BMA400_ACC_CHANNEL(_index, _axis) { \
0222     .type = IIO_ACCEL, \
0223     .modified = 1, \
0224     .channel2 = IIO_MOD_##_axis, \
0225     .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
0226     .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
0227         BIT(IIO_CHAN_INFO_SCALE) | \
0228         BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
0229     .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
0230         BIT(IIO_CHAN_INFO_SCALE) | \
0231         BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
0232     .ext_info = bma400_ext_info, \
0233     .scan_index = _index,   \
0234     .scan_type = {      \
0235         .sign = 's',    \
0236         .realbits = 12,     \
0237         .storagebits = 16,  \
0238         .endianness = IIO_LE,   \
0239     },              \
0240     .event_spec = bma400_accel_event,           \
0241     .num_event_specs = ARRAY_SIZE(bma400_accel_event)   \
0242 }
0243 
0244 #define BMA400_ACTIVITY_CHANNEL(_chan2) {   \
0245     .type = IIO_ACTIVITY,           \
0246     .modified = 1,              \
0247     .channel2 = _chan2,         \
0248     .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
0249     .scan_index = -1, /* No buffer support */       \
0250     .event_spec = &bma400_activity_event,           \
0251     .num_event_specs = 1,                   \
0252 }
0253 
0254 static const struct iio_chan_spec bma400_channels[] = {
0255     BMA400_ACC_CHANNEL(0, X),
0256     BMA400_ACC_CHANNEL(1, Y),
0257     BMA400_ACC_CHANNEL(2, Z),
0258     {
0259         .type = IIO_TEMP,
0260         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
0261         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ),
0262         .scan_index = 3,
0263         .scan_type = {
0264             .sign = 's',
0265             .realbits = 8,
0266             .storagebits = 8,
0267             .endianness = IIO_LE,
0268         },
0269     },
0270     {
0271         .type = IIO_STEPS,
0272         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
0273                       BIT(IIO_CHAN_INFO_ENABLE),
0274         .scan_index = -1, /* No buffer support */
0275         .event_spec = &bma400_step_detect_event,
0276         .num_event_specs = 1,
0277     },
0278     BMA400_ACTIVITY_CHANNEL(IIO_MOD_STILL),
0279     BMA400_ACTIVITY_CHANNEL(IIO_MOD_WALKING),
0280     BMA400_ACTIVITY_CHANNEL(IIO_MOD_RUNNING),
0281     IIO_CHAN_SOFT_TIMESTAMP(4),
0282 };
0283 
0284 static int bma400_get_temp_reg(struct bma400_data *data, int *val, int *val2)
0285 {
0286     unsigned int raw_temp;
0287     int host_temp;
0288     int ret;
0289 
0290     if (data->power_mode == POWER_MODE_SLEEP)
0291         return -EBUSY;
0292 
0293     ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &raw_temp);
0294     if (ret)
0295         return ret;
0296 
0297     host_temp = sign_extend32(raw_temp, 7);
0298     /*
0299      * The formula for the TEMP_DATA register in the datasheet
0300      * is: x * 0.5 + 23
0301      */
0302     *val = (host_temp >> 1) + 23;
0303     *val2 = (host_temp & 0x1) * 500000;
0304     return IIO_VAL_INT_PLUS_MICRO;
0305 }
0306 
0307 static int bma400_get_accel_reg(struct bma400_data *data,
0308                 const struct iio_chan_spec *chan,
0309                 int *val)
0310 {
0311     __le16 raw_accel;
0312     int lsb_reg;
0313     int ret;
0314 
0315     if (data->power_mode == POWER_MODE_SLEEP)
0316         return -EBUSY;
0317 
0318     switch (chan->channel2) {
0319     case IIO_MOD_X:
0320         lsb_reg = BMA400_X_AXIS_LSB_REG;
0321         break;
0322     case IIO_MOD_Y:
0323         lsb_reg = BMA400_Y_AXIS_LSB_REG;
0324         break;
0325     case IIO_MOD_Z:
0326         lsb_reg = BMA400_Z_AXIS_LSB_REG;
0327         break;
0328     default:
0329         dev_err(data->dev, "invalid axis channel modifier\n");
0330         return -EINVAL;
0331     }
0332 
0333     /* bulk read two registers, with the base being the LSB register */
0334     ret = regmap_bulk_read(data->regmap, lsb_reg, &raw_accel,
0335                    sizeof(raw_accel));
0336     if (ret)
0337         return ret;
0338 
0339     *val = sign_extend32(le16_to_cpu(raw_accel), 11);
0340     return IIO_VAL_INT;
0341 }
0342 
0343 static void bma400_output_data_rate_from_raw(int raw, unsigned int *val,
0344                          unsigned int *val2)
0345 {
0346     *val = BMA400_ACC_ODR_MAX_HZ >> (BMA400_ACC_ODR_MAX_RAW - raw);
0347     if (raw > BMA400_ACC_ODR_MIN_RAW)
0348         *val2 = 0;
0349     else
0350         *val2 = 500000;
0351 }
0352 
0353 static int bma400_get_accel_output_data_rate(struct bma400_data *data)
0354 {
0355     unsigned int val;
0356     unsigned int odr;
0357     int ret;
0358 
0359     switch (data->power_mode) {
0360     case POWER_MODE_LOW:
0361         /*
0362          * Runs at a fixed rate in low-power mode. See section 4.3
0363          * in the datasheet.
0364          */
0365         bma400_output_data_rate_from_raw(BMA400_ACC_ODR_LP_RAW,
0366                          &data->sample_freq.hz,
0367                          &data->sample_freq.uhz);
0368         return 0;
0369     case POWER_MODE_NORMAL:
0370         /*
0371          * In normal mode the ODR can be found in the ACC_CONFIG1
0372          * register.
0373          */
0374         ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
0375         if (ret)
0376             goto error;
0377 
0378         odr = val & BMA400_ACC_ODR_MASK;
0379         if (odr < BMA400_ACC_ODR_MIN_RAW ||
0380             odr > BMA400_ACC_ODR_MAX_RAW) {
0381             ret = -EINVAL;
0382             goto error;
0383         }
0384 
0385         bma400_output_data_rate_from_raw(odr, &data->sample_freq.hz,
0386                          &data->sample_freq.uhz);
0387         return 0;
0388     case POWER_MODE_SLEEP:
0389         data->sample_freq.hz = 0;
0390         data->sample_freq.uhz = 0;
0391         return 0;
0392     default:
0393         ret = 0;
0394         goto error;
0395     }
0396 error:
0397     data->sample_freq.hz = -1;
0398     data->sample_freq.uhz = -1;
0399     return ret;
0400 }
0401 
0402 static int bma400_set_accel_output_data_rate(struct bma400_data *data,
0403                          int hz, int uhz)
0404 {
0405     unsigned int idx;
0406     unsigned int odr;
0407     unsigned int val;
0408     int ret;
0409 
0410     if (hz >= BMA400_ACC_ODR_MIN_WHOLE_HZ) {
0411         if (uhz || hz > BMA400_ACC_ODR_MAX_HZ)
0412             return -EINVAL;
0413 
0414         /* Note this works because MIN_WHOLE_HZ is odd */
0415         idx = __ffs(hz);
0416 
0417         if (hz >> idx != BMA400_ACC_ODR_MIN_WHOLE_HZ)
0418             return -EINVAL;
0419 
0420         idx += BMA400_ACC_ODR_MIN_RAW + 1;
0421     } else if (hz == BMA400_ACC_ODR_MIN_HZ && uhz == 500000) {
0422         idx = BMA400_ACC_ODR_MIN_RAW;
0423     } else {
0424         return -EINVAL;
0425     }
0426 
0427     ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
0428     if (ret)
0429         return ret;
0430 
0431     /* preserve the range and normal mode osr */
0432     odr = (~BMA400_ACC_ODR_MASK & val) | idx;
0433 
0434     ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG, odr);
0435     if (ret)
0436         return ret;
0437 
0438     bma400_output_data_rate_from_raw(idx, &data->sample_freq.hz,
0439                      &data->sample_freq.uhz);
0440     return 0;
0441 }
0442 
0443 static int bma400_get_accel_oversampling_ratio(struct bma400_data *data)
0444 {
0445     unsigned int val;
0446     unsigned int osr;
0447     int ret;
0448 
0449     /*
0450      * The oversampling ratio is stored in a different register
0451      * based on the power-mode. In normal mode the OSR is stored
0452      * in ACC_CONFIG1. In low-power mode it is stored in
0453      * ACC_CONFIG0.
0454      */
0455     switch (data->power_mode) {
0456     case POWER_MODE_LOW:
0457         ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);
0458         if (ret) {
0459             data->oversampling_ratio = -1;
0460             return ret;
0461         }
0462 
0463         osr = (val & BMA400_LP_OSR_MASK) >> BMA400_LP_OSR_SHIFT;
0464 
0465         data->oversampling_ratio = osr;
0466         return 0;
0467     case POWER_MODE_NORMAL:
0468         ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
0469         if (ret) {
0470             data->oversampling_ratio = -1;
0471             return ret;
0472         }
0473 
0474         osr = (val & BMA400_NP_OSR_MASK) >> BMA400_NP_OSR_SHIFT;
0475 
0476         data->oversampling_ratio = osr;
0477         return 0;
0478     case POWER_MODE_SLEEP:
0479         data->oversampling_ratio = 0;
0480         return 0;
0481     default:
0482         data->oversampling_ratio = -1;
0483         return -EINVAL;
0484     }
0485 }
0486 
0487 static int bma400_set_accel_oversampling_ratio(struct bma400_data *data,
0488                            int val)
0489 {
0490     unsigned int acc_config;
0491     int ret;
0492 
0493     if (val & ~BMA400_TWO_BITS_MASK)
0494         return -EINVAL;
0495 
0496     /*
0497      * The oversampling ratio is stored in a different register
0498      * based on the power-mode.
0499      */
0500     switch (data->power_mode) {
0501     case POWER_MODE_LOW:
0502         ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG,
0503                   &acc_config);
0504         if (ret)
0505             return ret;
0506 
0507         ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,
0508                    (acc_config & ~BMA400_LP_OSR_MASK) |
0509                    (val << BMA400_LP_OSR_SHIFT));
0510         if (ret) {
0511             dev_err(data->dev, "Failed to write out OSR\n");
0512             return ret;
0513         }
0514 
0515         data->oversampling_ratio = val;
0516         return 0;
0517     case POWER_MODE_NORMAL:
0518         ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG,
0519                   &acc_config);
0520         if (ret)
0521             return ret;
0522 
0523         ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,
0524                    (acc_config & ~BMA400_NP_OSR_MASK) |
0525                    (val << BMA400_NP_OSR_SHIFT));
0526         if (ret) {
0527             dev_err(data->dev, "Failed to write out OSR\n");
0528             return ret;
0529         }
0530 
0531         data->oversampling_ratio = val;
0532         return 0;
0533     default:
0534         return -EINVAL;
0535     }
0536     return ret;
0537 }
0538 
0539 static int bma400_accel_scale_to_raw(struct bma400_data *data,
0540                      unsigned int val)
0541 {
0542     int raw;
0543 
0544     if (val == 0)
0545         return -EINVAL;
0546 
0547     /* Note this works because BMA400_SCALE_MIN is odd */
0548     raw = __ffs(val);
0549 
0550     if (val >> raw != BMA400_SCALE_MIN)
0551         return -EINVAL;
0552 
0553     return raw;
0554 }
0555 
0556 static int bma400_get_accel_scale(struct bma400_data *data)
0557 {
0558     unsigned int raw_scale;
0559     unsigned int val;
0560     int ret;
0561 
0562     ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &val);
0563     if (ret)
0564         return ret;
0565 
0566     raw_scale = (val & BMA400_ACC_SCALE_MASK) >> BMA400_SCALE_SHIFT;
0567     if (raw_scale > BMA400_TWO_BITS_MASK)
0568         return -EINVAL;
0569 
0570     data->scale = BMA400_SCALE_MIN << raw_scale;
0571 
0572     return 0;
0573 }
0574 
0575 static int bma400_set_accel_scale(struct bma400_data *data, unsigned int val)
0576 {
0577     unsigned int acc_config;
0578     int raw;
0579     int ret;
0580 
0581     ret = regmap_read(data->regmap, BMA400_ACC_CONFIG1_REG, &acc_config);
0582     if (ret)
0583         return ret;
0584 
0585     raw = bma400_accel_scale_to_raw(data, val);
0586     if (raw < 0)
0587         return raw;
0588 
0589     ret = regmap_write(data->regmap, BMA400_ACC_CONFIG1_REG,
0590                (acc_config & ~BMA400_ACC_SCALE_MASK) |
0591                (raw << BMA400_SCALE_SHIFT));
0592     if (ret)
0593         return ret;
0594 
0595     data->scale = val;
0596     return 0;
0597 }
0598 
0599 static int bma400_get_power_mode(struct bma400_data *data)
0600 {
0601     unsigned int val;
0602     int ret;
0603 
0604     ret = regmap_read(data->regmap, BMA400_STATUS_REG, &val);
0605     if (ret) {
0606         dev_err(data->dev, "Failed to read status register\n");
0607         return ret;
0608     }
0609 
0610     data->power_mode = (val >> 1) & BMA400_TWO_BITS_MASK;
0611     return 0;
0612 }
0613 
0614 static int bma400_set_power_mode(struct bma400_data *data,
0615                  enum bma400_power_mode mode)
0616 {
0617     unsigned int val;
0618     int ret;
0619 
0620     ret = regmap_read(data->regmap, BMA400_ACC_CONFIG0_REG, &val);
0621     if (ret)
0622         return ret;
0623 
0624     if (data->power_mode == mode)
0625         return 0;
0626 
0627     if (mode == POWER_MODE_INVALID)
0628         return -EINVAL;
0629 
0630     /* Preserve the low-power oversample ratio etc */
0631     ret = regmap_write(data->regmap, BMA400_ACC_CONFIG0_REG,
0632                mode | (val & ~BMA400_TWO_BITS_MASK));
0633     if (ret) {
0634         dev_err(data->dev, "Failed to write to power-mode\n");
0635         return ret;
0636     }
0637 
0638     data->power_mode = mode;
0639 
0640     /*
0641      * Update our cached osr and odr based on the new
0642      * power-mode.
0643      */
0644     bma400_get_accel_output_data_rate(data);
0645     bma400_get_accel_oversampling_ratio(data);
0646     return 0;
0647 }
0648 
0649 static int bma400_enable_steps(struct bma400_data *data, int val)
0650 {
0651     int ret;
0652 
0653     if (data->steps_enabled == val)
0654         return 0;
0655 
0656     ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG1_REG,
0657                  BMA400_STEP_INT_MSK,
0658                  FIELD_PREP(BMA400_STEP_INT_MSK, val ? 1 : 0));
0659     if (ret)
0660         return ret;
0661     data->steps_enabled = val;
0662     return ret;
0663 }
0664 
0665 static int bma400_get_steps_reg(struct bma400_data *data, int *val)
0666 {
0667     u8 *steps_raw;
0668     int ret;
0669 
0670     steps_raw = kmalloc(BMA400_STEP_RAW_LEN, GFP_KERNEL);
0671     if (!steps_raw)
0672         return -ENOMEM;
0673 
0674     ret = regmap_bulk_read(data->regmap, BMA400_STEP_CNT0_REG,
0675                    steps_raw, BMA400_STEP_RAW_LEN);
0676     if (ret)
0677         return ret;
0678     *val = get_unaligned_le24(steps_raw);
0679     kfree(steps_raw);
0680     return IIO_VAL_INT;
0681 }
0682 
0683 static void bma400_init_tables(void)
0684 {
0685     int raw;
0686     int i;
0687 
0688     for (i = 0; i + 1 < ARRAY_SIZE(bma400_sample_freqs); i += 2) {
0689         raw = (i / 2) + 5;
0690         bma400_output_data_rate_from_raw(raw, &bma400_sample_freqs[i],
0691                          &bma400_sample_freqs[i + 1]);
0692     }
0693 
0694     for (i = 0; i + 1 < ARRAY_SIZE(bma400_scales); i += 2) {
0695         raw = i / 2;
0696         bma400_scales[i] = 0;
0697         bma400_scales[i + 1] = BMA400_SCALE_MIN << raw;
0698     }
0699 }
0700 
0701 static void bma400_regulators_disable(void *data_ptr)
0702 {
0703     struct bma400_data *data = data_ptr;
0704 
0705     regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators);
0706 }
0707 
0708 static void bma400_power_disable(void *data_ptr)
0709 {
0710     struct bma400_data *data = data_ptr;
0711     int ret;
0712 
0713     mutex_lock(&data->mutex);
0714     ret = bma400_set_power_mode(data, POWER_MODE_SLEEP);
0715     mutex_unlock(&data->mutex);
0716     if (ret)
0717         dev_warn(data->dev, "Failed to put device into sleep mode (%pe)\n",
0718              ERR_PTR(ret));
0719 }
0720 
0721 static enum iio_modifier bma400_act_to_mod(enum bma400_activity activity)
0722 {
0723     switch (activity) {
0724     case BMA400_STILL:
0725         return IIO_MOD_STILL;
0726     case BMA400_WALKING:
0727         return IIO_MOD_WALKING;
0728     case BMA400_RUNNING:
0729         return IIO_MOD_RUNNING;
0730     default:
0731         return IIO_NO_MOD;
0732     }
0733 }
0734 
0735 static int bma400_init(struct bma400_data *data)
0736 {
0737     unsigned int val;
0738     int ret;
0739 
0740     /* Try to read chip_id register. It must return 0x90. */
0741     ret = regmap_read(data->regmap, BMA400_CHIP_ID_REG, &val);
0742     if (ret) {
0743         dev_err(data->dev, "Failed to read chip id register\n");
0744         return ret;
0745     }
0746 
0747     if (val != BMA400_ID_REG_VAL) {
0748         dev_err(data->dev, "Chip ID mismatch\n");
0749         return -ENODEV;
0750     }
0751 
0752     data->regulators[BMA400_VDD_REGULATOR].supply = "vdd";
0753     data->regulators[BMA400_VDDIO_REGULATOR].supply = "vddio";
0754     ret = devm_regulator_bulk_get(data->dev,
0755                       ARRAY_SIZE(data->regulators),
0756                       data->regulators);
0757     if (ret) {
0758         if (ret != -EPROBE_DEFER)
0759             dev_err(data->dev,
0760                 "Failed to get regulators: %d\n",
0761                 ret);
0762 
0763         return ret;
0764     }
0765     ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
0766                     data->regulators);
0767     if (ret) {
0768         dev_err(data->dev, "Failed to enable regulators: %d\n",
0769             ret);
0770         return ret;
0771     }
0772 
0773     ret = devm_add_action_or_reset(data->dev, bma400_regulators_disable, data);
0774     if (ret)
0775         return ret;
0776 
0777     ret = bma400_get_power_mode(data);
0778     if (ret) {
0779         dev_err(data->dev, "Failed to get the initial power-mode\n");
0780         return ret;
0781     }
0782 
0783     if (data->power_mode != POWER_MODE_NORMAL) {
0784         ret = bma400_set_power_mode(data, POWER_MODE_NORMAL);
0785         if (ret) {
0786             dev_err(data->dev, "Failed to wake up the device\n");
0787             return ret;
0788         }
0789         /*
0790          * TODO: The datasheet waits 1500us here in the example, but
0791          * lists 2/ODR as the wakeup time.
0792          */
0793         usleep_range(1500, 2000);
0794     }
0795 
0796     ret = devm_add_action_or_reset(data->dev, bma400_power_disable, data);
0797     if (ret)
0798         return ret;
0799 
0800     bma400_init_tables();
0801 
0802     ret = bma400_get_accel_output_data_rate(data);
0803     if (ret)
0804         return ret;
0805 
0806     ret = bma400_get_accel_oversampling_ratio(data);
0807     if (ret)
0808         return ret;
0809 
0810     ret = bma400_get_accel_scale(data);
0811     if (ret)
0812         return ret;
0813 
0814     /* Configure INT1 pin to open drain */
0815     ret = regmap_write(data->regmap, BMA400_INT_IO_CTRL_REG, 0x06);
0816     if (ret)
0817         return ret;
0818     /*
0819      * Once the interrupt engine is supported we might use the
0820      * data_src_reg, but for now ensure this is set to the
0821      * variable ODR filter selectable by the sample frequency
0822      * channel.
0823      */
0824     return regmap_write(data->regmap, BMA400_ACC_CONFIG2_REG, 0x00);
0825 }
0826 
0827 static int bma400_read_raw(struct iio_dev *indio_dev,
0828                struct iio_chan_spec const *chan, int *val,
0829                int *val2, long mask)
0830 {
0831     struct bma400_data *data = iio_priv(indio_dev);
0832     unsigned int activity;
0833     int ret;
0834 
0835     switch (mask) {
0836     case IIO_CHAN_INFO_PROCESSED:
0837         switch (chan->type) {
0838         case IIO_TEMP:
0839             mutex_lock(&data->mutex);
0840             ret = bma400_get_temp_reg(data, val, val2);
0841             mutex_unlock(&data->mutex);
0842             return ret;
0843         case IIO_STEPS:
0844             return bma400_get_steps_reg(data, val);
0845         case IIO_ACTIVITY:
0846             ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG,
0847                       &activity);
0848             if (ret)
0849                 return ret;
0850             /*
0851              * The device does not support confidence value levels,
0852              * so we will always have 100% for current activity and
0853              * 0% for the others.
0854              */
0855             if (chan->channel2 == bma400_act_to_mod(activity))
0856                 *val = 100;
0857             else
0858                 *val = 0;
0859             return IIO_VAL_INT;
0860         default:
0861             return -EINVAL;
0862         }
0863     case IIO_CHAN_INFO_RAW:
0864         mutex_lock(&data->mutex);
0865         ret = bma400_get_accel_reg(data, chan, val);
0866         mutex_unlock(&data->mutex);
0867         return ret;
0868     case IIO_CHAN_INFO_SAMP_FREQ:
0869         switch (chan->type) {
0870         case IIO_ACCEL:
0871             if (data->sample_freq.hz < 0)
0872                 return -EINVAL;
0873 
0874             *val = data->sample_freq.hz;
0875             *val2 = data->sample_freq.uhz;
0876             return IIO_VAL_INT_PLUS_MICRO;
0877         case IIO_TEMP:
0878             /*
0879              * Runs at a fixed sampling frequency. See Section 4.4
0880              * of the datasheet.
0881              */
0882             *val = 6;
0883             *val2 = 250000;
0884             return IIO_VAL_INT_PLUS_MICRO;
0885         default:
0886             return -EINVAL;
0887         }
0888     case IIO_CHAN_INFO_SCALE:
0889         *val = 0;
0890         *val2 = data->scale;
0891         return IIO_VAL_INT_PLUS_MICRO;
0892     case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
0893         /*
0894          * TODO: We could avoid this logic and returning -EINVAL here if
0895          * we set both the low-power and normal mode OSR registers when
0896          * we configure the device.
0897          */
0898         if (data->oversampling_ratio < 0)
0899             return -EINVAL;
0900 
0901         *val = data->oversampling_ratio;
0902         return IIO_VAL_INT;
0903     case IIO_CHAN_INFO_ENABLE:
0904         *val = data->steps_enabled;
0905         return IIO_VAL_INT;
0906     default:
0907         return -EINVAL;
0908     }
0909 }
0910 
0911 static int bma400_read_avail(struct iio_dev *indio_dev,
0912                  struct iio_chan_spec const *chan,
0913                  const int **vals, int *type, int *length,
0914                  long mask)
0915 {
0916     switch (mask) {
0917     case IIO_CHAN_INFO_SCALE:
0918         *type = IIO_VAL_INT_PLUS_MICRO;
0919         *vals = bma400_scales;
0920         *length = ARRAY_SIZE(bma400_scales);
0921         return IIO_AVAIL_LIST;
0922     case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
0923         *type = IIO_VAL_INT;
0924         *vals = bma400_osr_range;
0925         *length = ARRAY_SIZE(bma400_osr_range);
0926         return IIO_AVAIL_RANGE;
0927     case IIO_CHAN_INFO_SAMP_FREQ:
0928         *type = IIO_VAL_INT_PLUS_MICRO;
0929         *vals = bma400_sample_freqs;
0930         *length = ARRAY_SIZE(bma400_sample_freqs);
0931         return IIO_AVAIL_LIST;
0932     default:
0933         return -EINVAL;
0934     }
0935 }
0936 
0937 static int bma400_write_raw(struct iio_dev *indio_dev,
0938                 struct iio_chan_spec const *chan, int val, int val2,
0939                 long mask)
0940 {
0941     struct bma400_data *data = iio_priv(indio_dev);
0942     int ret;
0943 
0944     switch (mask) {
0945     case IIO_CHAN_INFO_SAMP_FREQ:
0946         /*
0947          * The sample frequency is readonly for the temperature
0948          * register and a fixed value in low-power mode.
0949          */
0950         if (chan->type != IIO_ACCEL)
0951             return -EINVAL;
0952 
0953         mutex_lock(&data->mutex);
0954         ret = bma400_set_accel_output_data_rate(data, val, val2);
0955         mutex_unlock(&data->mutex);
0956         return ret;
0957     case IIO_CHAN_INFO_SCALE:
0958         if (val != 0 ||
0959             val2 < BMA400_SCALE_MIN || val2 > BMA400_SCALE_MAX)
0960             return -EINVAL;
0961 
0962         mutex_lock(&data->mutex);
0963         ret = bma400_set_accel_scale(data, val2);
0964         mutex_unlock(&data->mutex);
0965         return ret;
0966     case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
0967         mutex_lock(&data->mutex);
0968         ret = bma400_set_accel_oversampling_ratio(data, val);
0969         mutex_unlock(&data->mutex);
0970         return ret;
0971     case IIO_CHAN_INFO_ENABLE:
0972         mutex_lock(&data->mutex);
0973         ret = bma400_enable_steps(data, val);
0974         mutex_unlock(&data->mutex);
0975         return ret;
0976     default:
0977         return -EINVAL;
0978     }
0979 }
0980 
0981 static int bma400_write_raw_get_fmt(struct iio_dev *indio_dev,
0982                     struct iio_chan_spec const *chan,
0983                     long mask)
0984 {
0985     switch (mask) {
0986     case IIO_CHAN_INFO_SAMP_FREQ:
0987         return IIO_VAL_INT_PLUS_MICRO;
0988     case IIO_CHAN_INFO_SCALE:
0989         return IIO_VAL_INT_PLUS_MICRO;
0990     case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
0991         return IIO_VAL_INT;
0992     case IIO_CHAN_INFO_ENABLE:
0993         return IIO_VAL_INT;
0994     default:
0995         return -EINVAL;
0996     }
0997 }
0998 
0999 static int bma400_read_event_config(struct iio_dev *indio_dev,
1000                     const struct iio_chan_spec *chan,
1001                     enum iio_event_type type,
1002                     enum iio_event_direction dir)
1003 {
1004     struct bma400_data *data = iio_priv(indio_dev);
1005 
1006     switch (chan->type) {
1007     case IIO_ACCEL:
1008         switch (dir) {
1009         case IIO_EV_DIR_RISING:
1010             return FIELD_GET(BMA400_INT_GEN1_MSK,
1011                      data->generic_event_en);
1012         case IIO_EV_DIR_FALLING:
1013             return FIELD_GET(BMA400_INT_GEN2_MSK,
1014                      data->generic_event_en);
1015         default:
1016             return -EINVAL;
1017         }
1018     case IIO_STEPS:
1019         return data->step_event_en;
1020     case IIO_ACTIVITY:
1021         return data->activity_event_en;
1022     default:
1023         return -EINVAL;
1024     }
1025 }
1026 
1027 static int bma400_steps_event_enable(struct bma400_data *data, int state)
1028 {
1029     int ret;
1030 
1031     ret = bma400_enable_steps(data, 1);
1032     if (ret)
1033         return ret;
1034 
1035     ret = regmap_update_bits(data->regmap, BMA400_INT12_MAP_REG,
1036                  BMA400_STEP_INT_MSK,
1037                  FIELD_PREP(BMA400_STEP_INT_MSK,
1038                         state));
1039     if (ret)
1040         return ret;
1041     data->step_event_en = state;
1042     return 0;
1043 }
1044 
1045 static int bma400_activity_event_en(struct bma400_data *data,
1046                     enum iio_event_direction dir,
1047                     int state)
1048 {
1049     int ret, reg, msk, value, field_value;
1050 
1051     switch (dir) {
1052     case IIO_EV_DIR_RISING:
1053         reg = BMA400_GEN1INT_CONFIG0;
1054         msk = BMA400_INT_GEN1_MSK;
1055         value = 2;
1056         set_mask_bits(&field_value, BMA400_INT_GEN1_MSK,
1057                   FIELD_PREP(BMA400_INT_GEN1_MSK, state));
1058         break;
1059     case IIO_EV_DIR_FALLING:
1060         reg = BMA400_GEN2INT_CONFIG0;
1061         msk = BMA400_INT_GEN2_MSK;
1062         value = 0;
1063         set_mask_bits(&field_value, BMA400_INT_GEN2_MSK,
1064                   FIELD_PREP(BMA400_INT_GEN2_MSK, state));
1065         break;
1066     default:
1067         return -EINVAL;
1068     }
1069 
1070     /* Enabling all axis for interrupt evaluation */
1071     ret = regmap_write(data->regmap, reg, 0xF8);
1072     if (ret)
1073         return ret;
1074 
1075     /* OR combination of all axis for interrupt evaluation */
1076     ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG1_OFF, value);
1077     if (ret)
1078         return ret;
1079 
1080     /* Initial value to avoid interrupts while enabling*/
1081     ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG2_OFF, 0x0A);
1082     if (ret)
1083         return ret;
1084 
1085     /* Initial duration value to avoid interrupts while enabling*/
1086     ret = regmap_write(data->regmap, reg + BMA400_GEN_CONFIG31_OFF, 0x0F);
1087     if (ret)
1088         return ret;
1089 
1090     ret = regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG, msk,
1091                  field_value);
1092     if (ret)
1093         return ret;
1094 
1095     ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG, msk,
1096                  field_value);
1097     if (ret)
1098         return ret;
1099 
1100     set_mask_bits(&data->generic_event_en, msk, field_value);
1101     return 0;
1102 }
1103 
1104 static int bma400_write_event_config(struct iio_dev *indio_dev,
1105                      const struct iio_chan_spec *chan,
1106                      enum iio_event_type type,
1107                      enum iio_event_direction dir, int state)
1108 {
1109     struct bma400_data *data = iio_priv(indio_dev);
1110     int ret;
1111 
1112     switch (chan->type) {
1113     case IIO_ACCEL:
1114         mutex_lock(&data->mutex);
1115         ret = bma400_activity_event_en(data, dir, state);
1116         mutex_unlock(&data->mutex);
1117         return ret;
1118     case IIO_STEPS:
1119         mutex_lock(&data->mutex);
1120         ret = bma400_steps_event_enable(data, state);
1121         mutex_unlock(&data->mutex);
1122         return ret;
1123     case IIO_ACTIVITY:
1124         mutex_lock(&data->mutex);
1125         if (!data->step_event_en) {
1126             ret = bma400_steps_event_enable(data, true);
1127             if (ret) {
1128                 mutex_unlock(&data->mutex);
1129                 return ret;
1130             }
1131         }
1132         data->activity_event_en = state;
1133         mutex_unlock(&data->mutex);
1134         return 0;
1135     default:
1136         return -EINVAL;
1137     }
1138 }
1139 
1140 static int get_gen_config_reg(enum iio_event_direction dir)
1141 {
1142     switch (dir) {
1143     case IIO_EV_DIR_FALLING:
1144         return BMA400_GEN2INT_CONFIG0;
1145     case IIO_EV_DIR_RISING:
1146         return BMA400_GEN1INT_CONFIG0;
1147     default:
1148         return -EINVAL;
1149     }
1150 }
1151 
1152 static int bma400_read_event_value(struct iio_dev *indio_dev,
1153                    const struct iio_chan_spec *chan,
1154                    enum iio_event_type type,
1155                    enum iio_event_direction dir,
1156                    enum iio_event_info info,
1157                    int *val, int *val2)
1158 {
1159     struct bma400_data *data = iio_priv(indio_dev);
1160     int ret, reg;
1161 
1162     switch (chan->type) {
1163     case IIO_ACCEL:
1164         reg = get_gen_config_reg(dir);
1165         if (reg < 0)
1166             return -EINVAL;
1167 
1168         *val2 = 0;
1169         switch (info) {
1170         case IIO_EV_INFO_VALUE:
1171             ret = regmap_read(data->regmap,
1172                       reg + BMA400_GEN_CONFIG2_OFF,
1173                       val);
1174             if (ret)
1175                 return ret;
1176             return IIO_VAL_INT;
1177         case IIO_EV_INFO_PERIOD:
1178             mutex_lock(&data->mutex);
1179             ret = regmap_bulk_read(data->regmap,
1180                            reg + BMA400_GEN_CONFIG3_OFF,
1181                            &data->duration,
1182                            sizeof(data->duration));
1183             if (ret) {
1184                 mutex_unlock(&data->mutex);
1185                 return ret;
1186             }
1187             *val = be16_to_cpu(data->duration);
1188             mutex_unlock(&data->mutex);
1189             return IIO_VAL_INT;
1190         case IIO_EV_INFO_HYSTERESIS:
1191             ret = regmap_read(data->regmap, reg, val);
1192             if (ret)
1193                 return ret;
1194             *val = FIELD_GET(BMA400_GEN_HYST_MSK, *val);
1195             return IIO_VAL_INT;
1196         default:
1197             return -EINVAL;
1198         }
1199     default:
1200         return -EINVAL;
1201     }
1202 }
1203 
1204 static int bma400_write_event_value(struct iio_dev *indio_dev,
1205                     const struct iio_chan_spec *chan,
1206                     enum iio_event_type type,
1207                     enum iio_event_direction dir,
1208                     enum iio_event_info info,
1209                     int val, int val2)
1210 {
1211     struct bma400_data *data = iio_priv(indio_dev);
1212     int reg, ret;
1213 
1214     switch (chan->type) {
1215     case IIO_ACCEL:
1216         reg = get_gen_config_reg(dir);
1217         if (reg < 0)
1218             return -EINVAL;
1219 
1220         switch (info) {
1221         case IIO_EV_INFO_VALUE:
1222             if (val < 1 || val > 255)
1223                 return -EINVAL;
1224 
1225             return regmap_write(data->regmap,
1226                         reg + BMA400_GEN_CONFIG2_OFF,
1227                         val);
1228         case IIO_EV_INFO_PERIOD:
1229             if (val < 1 || val > 65535)
1230                 return -EINVAL;
1231 
1232             mutex_lock(&data->mutex);
1233             put_unaligned_be16(val, &data->duration);
1234             ret = regmap_bulk_write(data->regmap,
1235                         reg + BMA400_GEN_CONFIG3_OFF,
1236                         &data->duration,
1237                         sizeof(data->duration));
1238             mutex_unlock(&data->mutex);
1239             return ret;
1240         case IIO_EV_INFO_HYSTERESIS:
1241             if (val < 0 || val > 3)
1242                 return -EINVAL;
1243 
1244             return regmap_update_bits(data->regmap, reg,
1245                           BMA400_GEN_HYST_MSK,
1246                           FIELD_PREP(BMA400_GEN_HYST_MSK,
1247                                  val));
1248         default:
1249             return -EINVAL;
1250         }
1251     default:
1252         return -EINVAL;
1253     }
1254 }
1255 
1256 static int bma400_data_rdy_trigger_set_state(struct iio_trigger *trig,
1257                          bool state)
1258 {
1259     struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1260     struct bma400_data *data = iio_priv(indio_dev);
1261     int ret;
1262 
1263     ret = regmap_update_bits(data->regmap, BMA400_INT_CONFIG0_REG,
1264                  BMA400_INT_DRDY_MSK,
1265                  FIELD_PREP(BMA400_INT_DRDY_MSK, state));
1266     if (ret)
1267         return ret;
1268 
1269     return regmap_update_bits(data->regmap, BMA400_INT1_MAP_REG,
1270                   BMA400_INT_DRDY_MSK,
1271                   FIELD_PREP(BMA400_INT_DRDY_MSK, state));
1272 }
1273 
1274 static const unsigned long bma400_avail_scan_masks[] = {
1275     BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z),
1276     BIT(BMA400_ACCL_X) | BIT(BMA400_ACCL_Y) | BIT(BMA400_ACCL_Z)
1277     | BIT(BMA400_TEMP),
1278     0
1279 };
1280 
1281 static const struct iio_info bma400_info = {
1282     .read_raw          = bma400_read_raw,
1283     .read_avail        = bma400_read_avail,
1284     .write_raw         = bma400_write_raw,
1285     .write_raw_get_fmt = bma400_write_raw_get_fmt,
1286     .read_event_config = bma400_read_event_config,
1287     .write_event_config = bma400_write_event_config,
1288     .write_event_value = bma400_write_event_value,
1289     .read_event_value = bma400_read_event_value,
1290 };
1291 
1292 static const struct iio_trigger_ops bma400_trigger_ops = {
1293     .set_trigger_state = &bma400_data_rdy_trigger_set_state,
1294     .validate_device = &iio_trigger_validate_own_device,
1295 };
1296 
1297 static irqreturn_t bma400_trigger_handler(int irq, void *p)
1298 {
1299     struct iio_poll_func *pf = p;
1300     struct iio_dev *indio_dev = pf->indio_dev;
1301     struct bma400_data *data = iio_priv(indio_dev);
1302     int ret, temp;
1303 
1304     /* Lock to protect the data->buffer */
1305     mutex_lock(&data->mutex);
1306 
1307     /* bulk read six registers, with the base being the LSB register */
1308     ret = regmap_bulk_read(data->regmap, BMA400_X_AXIS_LSB_REG,
1309                    &data->buffer.buff, sizeof(data->buffer.buff));
1310     if (ret)
1311         goto unlock_err;
1312 
1313     if (test_bit(BMA400_TEMP, indio_dev->active_scan_mask)) {
1314         ret = regmap_read(data->regmap, BMA400_TEMP_DATA_REG, &temp);
1315         if (ret)
1316             goto unlock_err;
1317 
1318         data->buffer.temperature = temp;
1319     }
1320 
1321     iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1322                        iio_get_time_ns(indio_dev));
1323 
1324     mutex_unlock(&data->mutex);
1325     iio_trigger_notify_done(indio_dev->trig);
1326     return IRQ_HANDLED;
1327 
1328 unlock_err:
1329     mutex_unlock(&data->mutex);
1330     return IRQ_NONE;
1331 }
1332 
1333 static irqreturn_t bma400_interrupt(int irq, void *private)
1334 {
1335     struct iio_dev *indio_dev = private;
1336     struct bma400_data *data = iio_priv(indio_dev);
1337     s64 timestamp = iio_get_time_ns(indio_dev);
1338     unsigned int act, ev_dir = IIO_EV_DIR_NONE;
1339     int ret;
1340 
1341     /* Lock to protect the data->status */
1342     mutex_lock(&data->mutex);
1343     ret = regmap_bulk_read(data->regmap, BMA400_INT_STAT0_REG,
1344                    &data->status,
1345                    sizeof(data->status));
1346     /*
1347      * if none of the bit is set in the status register then it is
1348      * spurious interrupt.
1349      */
1350     if (ret || !data->status)
1351         goto unlock_err;
1352 
1353     if (FIELD_GET(BMA400_INT_GEN1_MSK, le16_to_cpu(data->status)))
1354         ev_dir = IIO_EV_DIR_RISING;
1355 
1356     if (FIELD_GET(BMA400_INT_GEN2_MSK, le16_to_cpu(data->status)))
1357         ev_dir = IIO_EV_DIR_FALLING;
1358 
1359     if (ev_dir != IIO_EV_DIR_NONE) {
1360         iio_push_event(indio_dev,
1361                    IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1362                           IIO_MOD_X_OR_Y_OR_Z,
1363                           IIO_EV_TYPE_MAG, ev_dir),
1364                    timestamp);
1365     }
1366 
1367     if (FIELD_GET(BMA400_STEP_STAT_MASK, le16_to_cpu(data->status))) {
1368         iio_push_event(indio_dev,
1369                    IIO_MOD_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD,
1370                           IIO_EV_TYPE_CHANGE,
1371                           IIO_EV_DIR_NONE),
1372                    timestamp);
1373 
1374         if (data->activity_event_en) {
1375             ret = regmap_read(data->regmap, BMA400_STEP_STAT_REG,
1376                       &act);
1377             if (ret)
1378                 goto unlock_err;
1379 
1380             iio_push_event(indio_dev,
1381                        IIO_MOD_EVENT_CODE(IIO_ACTIVITY, 0,
1382                               bma400_act_to_mod(act),
1383                               IIO_EV_TYPE_CHANGE,
1384                               IIO_EV_DIR_NONE),
1385                        timestamp);
1386         }
1387     }
1388 
1389     if (FIELD_GET(BMA400_INT_DRDY_MSK, le16_to_cpu(data->status))) {
1390         mutex_unlock(&data->mutex);
1391         iio_trigger_poll_chained(data->trig);
1392         return IRQ_HANDLED;
1393     }
1394 
1395     mutex_unlock(&data->mutex);
1396     return IRQ_HANDLED;
1397 
1398 unlock_err:
1399     mutex_unlock(&data->mutex);
1400     return IRQ_NONE;
1401 }
1402 
1403 int bma400_probe(struct device *dev, struct regmap *regmap, int irq,
1404          const char *name)
1405 {
1406     struct iio_dev *indio_dev;
1407     struct bma400_data *data;
1408     int ret;
1409 
1410     indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1411     if (!indio_dev)
1412         return -ENOMEM;
1413 
1414     data = iio_priv(indio_dev);
1415     data->regmap = regmap;
1416     data->dev = dev;
1417 
1418     ret = bma400_init(data);
1419     if (ret)
1420         return ret;
1421 
1422     ret = iio_read_mount_matrix(dev, &data->orientation);
1423     if (ret)
1424         return ret;
1425 
1426     mutex_init(&data->mutex);
1427     indio_dev->name = name;
1428     indio_dev->info = &bma400_info;
1429     indio_dev->channels = bma400_channels;
1430     indio_dev->num_channels = ARRAY_SIZE(bma400_channels);
1431     indio_dev->available_scan_masks = bma400_avail_scan_masks;
1432     indio_dev->modes = INDIO_DIRECT_MODE;
1433 
1434     if (irq > 0) {
1435         data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
1436                             indio_dev->name,
1437                             iio_device_id(indio_dev));
1438         if (!data->trig)
1439             return -ENOMEM;
1440 
1441         data->trig->ops = &bma400_trigger_ops;
1442         iio_trigger_set_drvdata(data->trig, indio_dev);
1443 
1444         ret = devm_iio_trigger_register(data->dev, data->trig);
1445         if (ret)
1446             return dev_err_probe(data->dev, ret,
1447                          "iio trigger register fail\n");
1448 
1449         indio_dev->trig = iio_trigger_get(data->trig);
1450         ret = devm_request_threaded_irq(dev, irq, NULL,
1451                         &bma400_interrupt,
1452                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1453                         indio_dev->name, indio_dev);
1454         if (ret)
1455             return dev_err_probe(data->dev, ret,
1456                          "request irq %d failed\n", irq);
1457     }
1458 
1459     ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
1460                           &bma400_trigger_handler, NULL);
1461     if (ret)
1462         return dev_err_probe(data->dev, ret,
1463                      "iio triggered buffer setup failed\n");
1464 
1465     return devm_iio_device_register(dev, indio_dev);
1466 }
1467 EXPORT_SYMBOL_NS(bma400_probe, IIO_BMA400);
1468 
1469 MODULE_AUTHOR("Dan Robertson <dan@dlrobertson.com>");
1470 MODULE_DESCRIPTION("Bosch BMA400 triaxial acceleration sensor core");
1471 MODULE_LICENSE("GPL");
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