iio/accel/adxl367_spi.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2021 Analog Devices, Inc.
0004  * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
0005  */
0006
0007 #include <linux/mod_devicetable.h>
0008 #include <linux/module.h>
0009 #include <linux/regmap.h>
0010 #include <linux/spi/spi.h>
0011
0012 #include <linux/iio/iio.h>
0013
0014 #include "adxl367.h"
0015
0016 #define ADXL367_SPI_WRITE_COMMAND   0x0A
0017 #define ADXL367_SPI_READ_COMMAND    0x0B
0018 #define ADXL367_SPI_FIFO_COMMAND    0x0D
0019
0020 struct adxl367_spi_state {
0021     struct spi_device   *spi;
0022
0023     struct spi_message  reg_write_msg;
0024     struct spi_transfer reg_write_xfer[2];
0025
0026     struct spi_message  reg_read_msg;
0027     struct spi_transfer reg_read_xfer[2];
0028
0029     struct spi_message  fifo_msg;
0030     struct spi_transfer fifo_xfer[2];
0031
0032     /*
0033      * DMA (thus cache coherency maintenance) may require the
0034      * transfer buffers live in their own cache lines.
0035      */
0036     u8          reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN);
0037     u8          reg_read_tx_buf[2];
0038     u8          fifo_tx_buf[1];
0039 };
0040
0041 static int adxl367_read_fifo(void *context, __be16 *fifo_buf,
0042                  unsigned int fifo_entries)
0043 {
0044     struct adxl367_spi_state *st = context;
0045
0046     st->fifo_xfer[1].rx_buf = fifo_buf;
0047     st->fifo_xfer[1].len = fifo_entries * sizeof(*fifo_buf);
0048
0049     return spi_sync(st->spi, &st->fifo_msg);
0050 }
0051
0052 static int adxl367_read(void *context, const void *reg_buf, size_t reg_size,
0053             void *val_buf, size_t val_size)
0054 {
0055     struct adxl367_spi_state *st = context;
0056     u8 reg = ((const u8 *)reg_buf)[0];
0057
0058     st->reg_read_tx_buf[1] = reg;
0059     st->reg_read_xfer[1].rx_buf = val_buf;
0060     st->reg_read_xfer[1].len = val_size;
0061
0062     return spi_sync(st->spi, &st->reg_read_msg);
0063 }
0064
0065 static int adxl367_write(void *context, const void *val_buf, size_t val_size)
0066 {
0067     struct adxl367_spi_state *st = context;
0068
0069     st->reg_write_xfer[1].tx_buf = val_buf;
0070     st->reg_write_xfer[1].len = val_size;
0071
0072     return spi_sync(st->spi, &st->reg_write_msg);
0073 }
0074
0075 static struct regmap_bus adxl367_spi_regmap_bus = {
0076     .read = adxl367_read,
0077     .write = adxl367_write,
0078 };
0079
0080 static const struct regmap_config adxl367_spi_regmap_config = {
0081     .reg_bits = 8,
0082     .val_bits = 8,
0083 };
0084
0085 static const struct adxl367_ops adxl367_spi_ops = {
0086     .read_fifo = adxl367_read_fifo,
0087 };
0088
0089 static int adxl367_spi_probe(struct spi_device *spi)
0090 {
0091     struct adxl367_spi_state *st;
0092     struct regmap *regmap;
0093
0094     st = devm_kzalloc(&spi->dev, sizeof(*st), GFP_KERNEL);
0095     if (!st)
0096         return -ENOMEM;
0097
0098     st->spi = spi;
0099
0100     /*
0101      * Xfer:   [XFR1] [           XFR2           ]
0102      * Master:  0x0A   ADDR DATA0 DATA1 ... DATAN
0103      * Slave:   ....   ..........................
0104      */
0105     st->reg_write_tx_buf[0] = ADXL367_SPI_WRITE_COMMAND;
0106     st->reg_write_xfer[0].tx_buf = st->reg_write_tx_buf;
0107     st->reg_write_xfer[0].len = sizeof(st->reg_write_tx_buf);
0108     spi_message_init_with_transfers(&st->reg_write_msg,
0109                     st->reg_write_xfer, 2);
0110
0111     /*
0112      * Xfer:   [   XFR1  ] [         XFR2        ]
0113      * Master:  0x0B ADDR   .....................
0114      * Slave:   .........   DATA0 DATA1 ... DATAN
0115      */
0116     st->reg_read_tx_buf[0] = ADXL367_SPI_READ_COMMAND;
0117     st->reg_read_xfer[0].tx_buf = st->reg_read_tx_buf;
0118     st->reg_read_xfer[0].len = sizeof(st->reg_read_tx_buf);
0119     spi_message_init_with_transfers(&st->reg_read_msg,
0120                     st->reg_read_xfer, 2);
0121
0122     /*
0123      * Xfer:   [XFR1] [         XFR2        ]
0124      * Master:  0x0D   .....................
0125      * Slave:   ....   DATA0 DATA1 ... DATAN
0126      */
0127     st->fifo_tx_buf[0] = ADXL367_SPI_FIFO_COMMAND;
0128     st->fifo_xfer[0].tx_buf = st->fifo_tx_buf;
0129     st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf);
0130     spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, 2);
0131
0132     regmap = devm_regmap_init(&spi->dev, &adxl367_spi_regmap_bus, st,
0133                   &adxl367_spi_regmap_config);
0134     if (IS_ERR(regmap))
0135         return PTR_ERR(regmap);
0136
0137     return adxl367_probe(&spi->dev, &adxl367_spi_ops, st, regmap, spi->irq);
0138 }
0139
0140 static const struct spi_device_id adxl367_spi_id[] = {
0141     { "adxl367", 0 },
0142     { },
0143 };
0144 MODULE_DEVICE_TABLE(spi, adxl367_spi_id);
0145
0146 static const struct of_device_id adxl367_of_match[] = {
0147     { .compatible = "adi,adxl367" },
0148     { },
0149 };
0150 MODULE_DEVICE_TABLE(of, adxl367_of_match);
0151
0152 static struct spi_driver adxl367_spi_driver = {
0153     .driver = {
0154         .name = "adxl367_spi",
0155         .of_match_table = adxl367_of_match,
0156     },
0157     .probe = adxl367_spi_probe,
0158     .id_table = adxl367_spi_id,
0159 };
0160
0161 module_spi_driver(adxl367_spi_driver);
0162
0163 MODULE_IMPORT_NS(IIO_ADXL367);
0164 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
0165 MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer SPI driver");
0166 MODULE_LICENSE("GPL");