Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Silvaco dual-role I3C master driver
0004  *
0005  * Copyright (C) 2020 Silvaco
0006  * Author: Miquel RAYNAL <miquel.raynal@bootlin.com>
0007  * Based on a work from: Conor Culhane <conor.culhane@silvaco.com>
0008  */
0009 
0010 #include <linux/bitfield.h>
0011 #include <linux/clk.h>
0012 #include <linux/completion.h>
0013 #include <linux/errno.h>
0014 #include <linux/i3c/master.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/iopoll.h>
0017 #include <linux/list.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/pinctrl/consumer.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pm_runtime.h>
0023 
0024 /* Master Mode Registers */
0025 #define SVC_I3C_MCONFIG      0x000
0026 #define   SVC_I3C_MCONFIG_MASTER_EN BIT(0)
0027 #define   SVC_I3C_MCONFIG_DISTO(x) FIELD_PREP(BIT(3), (x))
0028 #define   SVC_I3C_MCONFIG_HKEEP(x) FIELD_PREP(GENMASK(5, 4), (x))
0029 #define   SVC_I3C_MCONFIG_ODSTOP(x) FIELD_PREP(BIT(6), (x))
0030 #define   SVC_I3C_MCONFIG_PPBAUD(x) FIELD_PREP(GENMASK(11, 8), (x))
0031 #define   SVC_I3C_MCONFIG_PPLOW(x) FIELD_PREP(GENMASK(15, 12), (x))
0032 #define   SVC_I3C_MCONFIG_ODBAUD(x) FIELD_PREP(GENMASK(23, 16), (x))
0033 #define   SVC_I3C_MCONFIG_ODHPP(x) FIELD_PREP(BIT(24), (x))
0034 #define   SVC_I3C_MCONFIG_SKEW(x) FIELD_PREP(GENMASK(27, 25), (x))
0035 #define   SVC_I3C_MCONFIG_I2CBAUD(x) FIELD_PREP(GENMASK(31, 28), (x))
0036 
0037 #define SVC_I3C_MCTRL        0x084
0038 #define   SVC_I3C_MCTRL_REQUEST_MASK GENMASK(2, 0)
0039 #define   SVC_I3C_MCTRL_REQUEST_NONE 0
0040 #define   SVC_I3C_MCTRL_REQUEST_START_ADDR 1
0041 #define   SVC_I3C_MCTRL_REQUEST_STOP 2
0042 #define   SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK 3
0043 #define   SVC_I3C_MCTRL_REQUEST_PROC_DAA 4
0044 #define   SVC_I3C_MCTRL_REQUEST_AUTO_IBI 7
0045 #define   SVC_I3C_MCTRL_TYPE_I3C 0
0046 #define   SVC_I3C_MCTRL_TYPE_I2C BIT(4)
0047 #define   SVC_I3C_MCTRL_IBIRESP_AUTO 0
0048 #define   SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE 0
0049 #define   SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE BIT(7)
0050 #define   SVC_I3C_MCTRL_IBIRESP_NACK BIT(6)
0051 #define   SVC_I3C_MCTRL_IBIRESP_MANUAL GENMASK(7, 6)
0052 #define   SVC_I3C_MCTRL_DIR(x) FIELD_PREP(BIT(8), (x))
0053 #define   SVC_I3C_MCTRL_DIR_WRITE 0
0054 #define   SVC_I3C_MCTRL_DIR_READ 1
0055 #define   SVC_I3C_MCTRL_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x))
0056 #define   SVC_I3C_MCTRL_RDTERM(x) FIELD_PREP(GENMASK(23, 16), (x))
0057 
0058 #define SVC_I3C_MSTATUS      0x088
0059 #define   SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x))
0060 #define   SVC_I3C_MSTATUS_STATE_DAA(x) (SVC_I3C_MSTATUS_STATE(x) == 5)
0061 #define   SVC_I3C_MSTATUS_STATE_IDLE(x) (SVC_I3C_MSTATUS_STATE(x) == 0)
0062 #define   SVC_I3C_MSTATUS_BETWEEN(x) FIELD_GET(BIT(4), (x))
0063 #define   SVC_I3C_MSTATUS_NACKED(x) FIELD_GET(BIT(5), (x))
0064 #define   SVC_I3C_MSTATUS_IBITYPE(x) FIELD_GET(GENMASK(7, 6), (x))
0065 #define   SVC_I3C_MSTATUS_IBITYPE_IBI 1
0066 #define   SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST 2
0067 #define   SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN 3
0068 #define   SVC_I3C_MINT_SLVSTART BIT(8)
0069 #define   SVC_I3C_MINT_MCTRLDONE BIT(9)
0070 #define   SVC_I3C_MINT_COMPLETE BIT(10)
0071 #define   SVC_I3C_MINT_RXPEND BIT(11)
0072 #define   SVC_I3C_MINT_TXNOTFULL BIT(12)
0073 #define   SVC_I3C_MINT_IBIWON BIT(13)
0074 #define   SVC_I3C_MINT_ERRWARN BIT(15)
0075 #define   SVC_I3C_MSTATUS_SLVSTART(x) FIELD_GET(SVC_I3C_MINT_SLVSTART, (x))
0076 #define   SVC_I3C_MSTATUS_MCTRLDONE(x) FIELD_GET(SVC_I3C_MINT_MCTRLDONE, (x))
0077 #define   SVC_I3C_MSTATUS_COMPLETE(x) FIELD_GET(SVC_I3C_MINT_COMPLETE, (x))
0078 #define   SVC_I3C_MSTATUS_RXPEND(x) FIELD_GET(SVC_I3C_MINT_RXPEND, (x))
0079 #define   SVC_I3C_MSTATUS_TXNOTFULL(x) FIELD_GET(SVC_I3C_MINT_TXNOTFULL, (x))
0080 #define   SVC_I3C_MSTATUS_IBIWON(x) FIELD_GET(SVC_I3C_MINT_IBIWON, (x))
0081 #define   SVC_I3C_MSTATUS_ERRWARN(x) FIELD_GET(SVC_I3C_MINT_ERRWARN, (x))
0082 #define   SVC_I3C_MSTATUS_IBIADDR(x) FIELD_GET(GENMASK(30, 24), (x))
0083 
0084 #define SVC_I3C_IBIRULES     0x08C
0085 #define   SVC_I3C_IBIRULES_ADDR(slot, addr) FIELD_PREP(GENMASK(29, 0), \
0086                                ((addr) & 0x3F) << ((slot) * 6))
0087 #define   SVC_I3C_IBIRULES_ADDRS 5
0088 #define   SVC_I3C_IBIRULES_MSB0 BIT(30)
0089 #define   SVC_I3C_IBIRULES_NOBYTE BIT(31)
0090 #define   SVC_I3C_IBIRULES_MANDBYTE 0
0091 #define SVC_I3C_MINTSET      0x090
0092 #define SVC_I3C_MINTCLR      0x094
0093 #define SVC_I3C_MINTMASKED   0x098
0094 #define SVC_I3C_MERRWARN     0x09C
0095 #define SVC_I3C_MDMACTRL     0x0A0
0096 #define SVC_I3C_MDATACTRL    0x0AC
0097 #define   SVC_I3C_MDATACTRL_FLUSHTB BIT(0)
0098 #define   SVC_I3C_MDATACTRL_FLUSHRB BIT(1)
0099 #define   SVC_I3C_MDATACTRL_UNLOCK_TRIG BIT(3)
0100 #define   SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL GENMASK(5, 4)
0101 #define   SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY 0
0102 #define   SVC_I3C_MDATACTRL_RXCOUNT(x) FIELD_GET(GENMASK(28, 24), (x))
0103 #define   SVC_I3C_MDATACTRL_TXFULL BIT(30)
0104 #define   SVC_I3C_MDATACTRL_RXEMPTY BIT(31)
0105 
0106 #define SVC_I3C_MWDATAB      0x0B0
0107 #define   SVC_I3C_MWDATAB_END BIT(8)
0108 
0109 #define SVC_I3C_MWDATABE     0x0B4
0110 #define SVC_I3C_MWDATAH      0x0B8
0111 #define SVC_I3C_MWDATAHE     0x0BC
0112 #define SVC_I3C_MRDATAB      0x0C0
0113 #define SVC_I3C_MRDATAH      0x0C8
0114 #define SVC_I3C_MWMSG_SDR    0x0D0
0115 #define SVC_I3C_MRMSG_SDR    0x0D4
0116 #define SVC_I3C_MWMSG_DDR    0x0D8
0117 #define SVC_I3C_MRMSG_DDR    0x0DC
0118 
0119 #define SVC_I3C_MDYNADDR     0x0E4
0120 #define   SVC_MDYNADDR_VALID BIT(0)
0121 #define   SVC_MDYNADDR_ADDR(x) FIELD_PREP(GENMASK(7, 1), (x))
0122 
0123 #define SVC_I3C_MAX_DEVS 32
0124 #define SVC_I3C_PM_TIMEOUT_MS 1000
0125 
0126 /* This parameter depends on the implementation and may be tuned */
0127 #define SVC_I3C_FIFO_SIZE 16
0128 
0129 struct svc_i3c_cmd {
0130     u8 addr;
0131     bool rnw;
0132     u8 *in;
0133     const void *out;
0134     unsigned int len;
0135     unsigned int read_len;
0136     bool continued;
0137 };
0138 
0139 struct svc_i3c_xfer {
0140     struct list_head node;
0141     struct completion comp;
0142     int ret;
0143     unsigned int type;
0144     unsigned int ncmds;
0145     struct svc_i3c_cmd cmds[];
0146 };
0147 
0148 /**
0149  * struct svc_i3c_master - Silvaco I3C Master structure
0150  * @base: I3C master controller
0151  * @dev: Corresponding device
0152  * @regs: Memory mapping
0153  * @free_slots: Bit array of available slots
0154  * @addrs: Array containing the dynamic addresses of each attached device
0155  * @descs: Array of descriptors, one per attached device
0156  * @hj_work: Hot-join work
0157  * @ibi_work: IBI work
0158  * @irq: Main interrupt
0159  * @pclk: System clock
0160  * @fclk: Fast clock (bus)
0161  * @sclk: Slow clock (other events)
0162  * @xferqueue: Transfer queue structure
0163  * @xferqueue.list: List member
0164  * @xferqueue.cur: Current ongoing transfer
0165  * @xferqueue.lock: Queue lock
0166  * @ibi: IBI structure
0167  * @ibi.num_slots: Number of slots available in @ibi.slots
0168  * @ibi.slots: Available IBI slots
0169  * @ibi.tbq_slot: To be queued IBI slot
0170  * @ibi.lock: IBI lock
0171  */
0172 struct svc_i3c_master {
0173     struct i3c_master_controller base;
0174     struct device *dev;
0175     void __iomem *regs;
0176     u32 free_slots;
0177     u8 addrs[SVC_I3C_MAX_DEVS];
0178     struct i3c_dev_desc *descs[SVC_I3C_MAX_DEVS];
0179     struct work_struct hj_work;
0180     struct work_struct ibi_work;
0181     int irq;
0182     struct clk *pclk;
0183     struct clk *fclk;
0184     struct clk *sclk;
0185     struct {
0186         struct list_head list;
0187         struct svc_i3c_xfer *cur;
0188         /* Prevent races between transfers */
0189         spinlock_t lock;
0190     } xferqueue;
0191     struct {
0192         unsigned int num_slots;
0193         struct i3c_dev_desc **slots;
0194         struct i3c_ibi_slot *tbq_slot;
0195         /* Prevent races within IBI handlers */
0196         spinlock_t lock;
0197     } ibi;
0198 };
0199 
0200 /**
0201  * struct svc_i3c_i2c_dev_data - Device specific data
0202  * @index: Index in the master tables corresponding to this device
0203  * @ibi: IBI slot index in the master structure
0204  * @ibi_pool: IBI pool associated to this device
0205  */
0206 struct svc_i3c_i2c_dev_data {
0207     u8 index;
0208     int ibi;
0209     struct i3c_generic_ibi_pool *ibi_pool;
0210 };
0211 
0212 static bool svc_i3c_master_error(struct svc_i3c_master *master)
0213 {
0214     u32 mstatus, merrwarn;
0215 
0216     mstatus = readl(master->regs + SVC_I3C_MSTATUS);
0217     if (SVC_I3C_MSTATUS_ERRWARN(mstatus)) {
0218         merrwarn = readl(master->regs + SVC_I3C_MERRWARN);
0219         writel(merrwarn, master->regs + SVC_I3C_MERRWARN);
0220         dev_err(master->dev,
0221             "Error condition: MSTATUS 0x%08x, MERRWARN 0x%08x\n",
0222             mstatus, merrwarn);
0223 
0224         return true;
0225     }
0226 
0227     return false;
0228 }
0229 
0230 static void svc_i3c_master_enable_interrupts(struct svc_i3c_master *master, u32 mask)
0231 {
0232     writel(mask, master->regs + SVC_I3C_MINTSET);
0233 }
0234 
0235 static void svc_i3c_master_disable_interrupts(struct svc_i3c_master *master)
0236 {
0237     u32 mask = readl(master->regs + SVC_I3C_MINTSET);
0238 
0239     writel(mask, master->regs + SVC_I3C_MINTCLR);
0240 }
0241 
0242 static void svc_i3c_master_clear_merrwarn(struct svc_i3c_master *master)
0243 {
0244     /* Clear pending warnings */
0245     writel(readl(master->regs + SVC_I3C_MERRWARN),
0246            master->regs + SVC_I3C_MERRWARN);
0247 }
0248 
0249 static void svc_i3c_master_flush_fifo(struct svc_i3c_master *master)
0250 {
0251     /* Flush FIFOs */
0252     writel(SVC_I3C_MDATACTRL_FLUSHTB | SVC_I3C_MDATACTRL_FLUSHRB,
0253            master->regs + SVC_I3C_MDATACTRL);
0254 }
0255 
0256 static void svc_i3c_master_reset_fifo_trigger(struct svc_i3c_master *master)
0257 {
0258     u32 reg;
0259 
0260     /* Set RX and TX tigger levels, flush FIFOs */
0261     reg = SVC_I3C_MDATACTRL_FLUSHTB |
0262           SVC_I3C_MDATACTRL_FLUSHRB |
0263           SVC_I3C_MDATACTRL_UNLOCK_TRIG |
0264           SVC_I3C_MDATACTRL_TXTRIG_FIFO_NOT_FULL |
0265           SVC_I3C_MDATACTRL_RXTRIG_FIFO_NOT_EMPTY;
0266     writel(reg, master->regs + SVC_I3C_MDATACTRL);
0267 }
0268 
0269 static void svc_i3c_master_reset(struct svc_i3c_master *master)
0270 {
0271     svc_i3c_master_clear_merrwarn(master);
0272     svc_i3c_master_reset_fifo_trigger(master);
0273     svc_i3c_master_disable_interrupts(master);
0274 }
0275 
0276 static inline struct svc_i3c_master *
0277 to_svc_i3c_master(struct i3c_master_controller *master)
0278 {
0279     return container_of(master, struct svc_i3c_master, base);
0280 }
0281 
0282 static void svc_i3c_master_hj_work(struct work_struct *work)
0283 {
0284     struct svc_i3c_master *master;
0285 
0286     master = container_of(work, struct svc_i3c_master, hj_work);
0287     i3c_master_do_daa(&master->base);
0288 }
0289 
0290 static struct i3c_dev_desc *
0291 svc_i3c_master_dev_from_addr(struct svc_i3c_master *master,
0292                  unsigned int ibiaddr)
0293 {
0294     int i;
0295 
0296     for (i = 0; i < SVC_I3C_MAX_DEVS; i++)
0297         if (master->addrs[i] == ibiaddr)
0298             break;
0299 
0300     if (i == SVC_I3C_MAX_DEVS)
0301         return NULL;
0302 
0303     return master->descs[i];
0304 }
0305 
0306 static void svc_i3c_master_emit_stop(struct svc_i3c_master *master)
0307 {
0308     writel(SVC_I3C_MCTRL_REQUEST_STOP, master->regs + SVC_I3C_MCTRL);
0309 
0310     /*
0311      * This delay is necessary after the emission of a stop, otherwise eg.
0312      * repeating IBIs do not get detected. There is a note in the manual
0313      * about it, stating that the stop condition might not be settled
0314      * correctly if a start condition follows too rapidly.
0315      */
0316     udelay(1);
0317 }
0318 
0319 static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master,
0320                      struct i3c_dev_desc *dev)
0321 {
0322     struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
0323     struct i3c_ibi_slot *slot;
0324     unsigned int count;
0325     u32 mdatactrl;
0326     u8 *buf;
0327 
0328     slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
0329     if (!slot)
0330         return -ENOSPC;
0331 
0332     slot->len = 0;
0333     buf = slot->data;
0334 
0335     while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS))  &&
0336            slot->len < SVC_I3C_FIFO_SIZE) {
0337         mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL);
0338         count = SVC_I3C_MDATACTRL_RXCOUNT(mdatactrl);
0339         readsl(master->regs + SVC_I3C_MRDATAB, buf, count);
0340         slot->len += count;
0341         buf += count;
0342     }
0343 
0344     master->ibi.tbq_slot = slot;
0345 
0346     return 0;
0347 }
0348 
0349 static void svc_i3c_master_ack_ibi(struct svc_i3c_master *master,
0350                    bool mandatory_byte)
0351 {
0352     unsigned int ibi_ack_nack;
0353 
0354     ibi_ack_nack = SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK;
0355     if (mandatory_byte)
0356         ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITH_BYTE;
0357     else
0358         ibi_ack_nack |= SVC_I3C_MCTRL_IBIRESP_ACK_WITHOUT_BYTE;
0359 
0360     writel(ibi_ack_nack, master->regs + SVC_I3C_MCTRL);
0361 }
0362 
0363 static void svc_i3c_master_nack_ibi(struct svc_i3c_master *master)
0364 {
0365     writel(SVC_I3C_MCTRL_REQUEST_IBI_ACKNACK |
0366            SVC_I3C_MCTRL_IBIRESP_NACK,
0367            master->regs + SVC_I3C_MCTRL);
0368 }
0369 
0370 static void svc_i3c_master_ibi_work(struct work_struct *work)
0371 {
0372     struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work);
0373     struct svc_i3c_i2c_dev_data *data;
0374     unsigned int ibitype, ibiaddr;
0375     struct i3c_dev_desc *dev;
0376     u32 status, val;
0377     int ret;
0378 
0379     /* Acknowledge the incoming interrupt with the AUTOIBI mechanism */
0380     writel(SVC_I3C_MCTRL_REQUEST_AUTO_IBI |
0381            SVC_I3C_MCTRL_IBIRESP_AUTO,
0382            master->regs + SVC_I3C_MCTRL);
0383 
0384     /* Wait for IBIWON, should take approximately 100us */
0385     ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
0386                      SVC_I3C_MSTATUS_IBIWON(val), 0, 1000);
0387     if (ret) {
0388         dev_err(master->dev, "Timeout when polling for IBIWON\n");
0389         goto reenable_ibis;
0390     }
0391 
0392     /* Clear the interrupt status */
0393     writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
0394 
0395     status = readl(master->regs + SVC_I3C_MSTATUS);
0396     ibitype = SVC_I3C_MSTATUS_IBITYPE(status);
0397     ibiaddr = SVC_I3C_MSTATUS_IBIADDR(status);
0398 
0399     /* Handle the critical responses to IBI's */
0400     switch (ibitype) {
0401     case SVC_I3C_MSTATUS_IBITYPE_IBI:
0402         dev = svc_i3c_master_dev_from_addr(master, ibiaddr);
0403         if (!dev)
0404             svc_i3c_master_nack_ibi(master);
0405         else
0406             svc_i3c_master_handle_ibi(master, dev);
0407         break;
0408     case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN:
0409         svc_i3c_master_ack_ibi(master, false);
0410         break;
0411     case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:
0412         svc_i3c_master_nack_ibi(master);
0413         break;
0414     default:
0415         break;
0416     }
0417 
0418     /*
0419      * If an error happened, we probably got interrupted and the exchange
0420      * timedout. In this case we just drop everything, emit a stop and wait
0421      * for the slave to interrupt again.
0422      */
0423     if (svc_i3c_master_error(master)) {
0424         if (master->ibi.tbq_slot) {
0425             data = i3c_dev_get_master_data(dev);
0426             i3c_generic_ibi_recycle_slot(data->ibi_pool,
0427                              master->ibi.tbq_slot);
0428             master->ibi.tbq_slot = NULL;
0429         }
0430 
0431         svc_i3c_master_emit_stop(master);
0432 
0433         goto reenable_ibis;
0434     }
0435 
0436     /* Handle the non critical tasks */
0437     switch (ibitype) {
0438     case SVC_I3C_MSTATUS_IBITYPE_IBI:
0439         if (dev) {
0440             i3c_master_queue_ibi(dev, master->ibi.tbq_slot);
0441             master->ibi.tbq_slot = NULL;
0442         }
0443         svc_i3c_master_emit_stop(master);
0444         break;
0445     case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN:
0446         queue_work(master->base.wq, &master->hj_work);
0447         break;
0448     case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST:
0449     default:
0450         break;
0451     }
0452 
0453 reenable_ibis:
0454     svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
0455 }
0456 
0457 static irqreturn_t svc_i3c_master_irq_handler(int irq, void *dev_id)
0458 {
0459     struct svc_i3c_master *master = (struct svc_i3c_master *)dev_id;
0460     u32 active = readl(master->regs + SVC_I3C_MINTMASKED);
0461 
0462     if (!SVC_I3C_MSTATUS_SLVSTART(active))
0463         return IRQ_NONE;
0464 
0465     /* Clear the interrupt status */
0466     writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS);
0467 
0468     svc_i3c_master_disable_interrupts(master);
0469 
0470     /* Handle the interrupt in a non atomic context */
0471     queue_work(master->base.wq, &master->ibi_work);
0472 
0473     return IRQ_HANDLED;
0474 }
0475 
0476 static int svc_i3c_master_bus_init(struct i3c_master_controller *m)
0477 {
0478     struct svc_i3c_master *master = to_svc_i3c_master(m);
0479     struct i3c_bus *bus = i3c_master_get_bus(m);
0480     struct i3c_device_info info = {};
0481     unsigned long fclk_rate, fclk_period_ns;
0482     unsigned int high_period_ns, od_low_period_ns;
0483     u32 ppbaud, pplow, odhpp, odbaud, odstop, i2cbaud, reg;
0484     int ret;
0485 
0486     ret = pm_runtime_resume_and_get(master->dev);
0487     if (ret < 0) {
0488         dev_err(master->dev,
0489             "<%s> cannot resume i3c bus master, err: %d\n",
0490             __func__, ret);
0491         return ret;
0492     }
0493 
0494     /* Timings derivation */
0495     fclk_rate = clk_get_rate(master->fclk);
0496     if (!fclk_rate) {
0497         ret = -EINVAL;
0498         goto rpm_out;
0499     }
0500 
0501     fclk_period_ns = DIV_ROUND_UP(1000000000, fclk_rate);
0502 
0503     /*
0504      * Using I3C Push-Pull mode, target is 12.5MHz/80ns period.
0505      * Simplest configuration is using a 50% duty-cycle of 40ns.
0506      */
0507     ppbaud = DIV_ROUND_UP(40, fclk_period_ns) - 1;
0508     pplow = 0;
0509 
0510     /*
0511      * Using I3C Open-Drain mode, target is 4.17MHz/240ns with a
0512      * duty-cycle tuned so that high levels are filetered out by
0513      * the 50ns filter (target being 40ns).
0514      */
0515     odhpp = 1;
0516     high_period_ns = (ppbaud + 1) * fclk_period_ns;
0517     odbaud = DIV_ROUND_UP(240 - high_period_ns, high_period_ns) - 1;
0518     od_low_period_ns = (odbaud + 1) * high_period_ns;
0519 
0520     switch (bus->mode) {
0521     case I3C_BUS_MODE_PURE:
0522         i2cbaud = 0;
0523         odstop = 0;
0524         break;
0525     case I3C_BUS_MODE_MIXED_FAST:
0526     case I3C_BUS_MODE_MIXED_LIMITED:
0527         /*
0528          * Using I2C Fm+ mode, target is 1MHz/1000ns, the difference
0529          * between the high and low period does not really matter.
0530          */
0531         i2cbaud = DIV_ROUND_UP(1000, od_low_period_ns) - 2;
0532         odstop = 1;
0533         break;
0534     case I3C_BUS_MODE_MIXED_SLOW:
0535         /*
0536          * Using I2C Fm mode, target is 0.4MHz/2500ns, with the same
0537          * constraints as the FM+ mode.
0538          */
0539         i2cbaud = DIV_ROUND_UP(2500, od_low_period_ns) - 2;
0540         odstop = 1;
0541         break;
0542     default:
0543         goto rpm_out;
0544     }
0545 
0546     reg = SVC_I3C_MCONFIG_MASTER_EN |
0547           SVC_I3C_MCONFIG_DISTO(0) |
0548           SVC_I3C_MCONFIG_HKEEP(0) |
0549           SVC_I3C_MCONFIG_ODSTOP(odstop) |
0550           SVC_I3C_MCONFIG_PPBAUD(ppbaud) |
0551           SVC_I3C_MCONFIG_PPLOW(pplow) |
0552           SVC_I3C_MCONFIG_ODBAUD(odbaud) |
0553           SVC_I3C_MCONFIG_ODHPP(odhpp) |
0554           SVC_I3C_MCONFIG_SKEW(0) |
0555           SVC_I3C_MCONFIG_I2CBAUD(i2cbaud);
0556     writel(reg, master->regs + SVC_I3C_MCONFIG);
0557 
0558     /* Master core's registration */
0559     ret = i3c_master_get_free_addr(m, 0);
0560     if (ret < 0)
0561         goto rpm_out;
0562 
0563     info.dyn_addr = ret;
0564 
0565     writel(SVC_MDYNADDR_VALID | SVC_MDYNADDR_ADDR(info.dyn_addr),
0566            master->regs + SVC_I3C_MDYNADDR);
0567 
0568     ret = i3c_master_set_info(&master->base, &info);
0569     if (ret)
0570         goto rpm_out;
0571 
0572 rpm_out:
0573     pm_runtime_mark_last_busy(master->dev);
0574     pm_runtime_put_autosuspend(master->dev);
0575 
0576     return ret;
0577 }
0578 
0579 static void svc_i3c_master_bus_cleanup(struct i3c_master_controller *m)
0580 {
0581     struct svc_i3c_master *master = to_svc_i3c_master(m);
0582     int ret;
0583 
0584     ret = pm_runtime_resume_and_get(master->dev);
0585     if (ret < 0) {
0586         dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
0587         return;
0588     }
0589 
0590     svc_i3c_master_disable_interrupts(master);
0591 
0592     /* Disable master */
0593     writel(0, master->regs + SVC_I3C_MCONFIG);
0594 
0595     pm_runtime_mark_last_busy(master->dev);
0596     pm_runtime_put_autosuspend(master->dev);
0597 }
0598 
0599 static int svc_i3c_master_reserve_slot(struct svc_i3c_master *master)
0600 {
0601     unsigned int slot;
0602 
0603     if (!(master->free_slots & GENMASK(SVC_I3C_MAX_DEVS - 1, 0)))
0604         return -ENOSPC;
0605 
0606     slot = ffs(master->free_slots) - 1;
0607 
0608     master->free_slots &= ~BIT(slot);
0609 
0610     return slot;
0611 }
0612 
0613 static void svc_i3c_master_release_slot(struct svc_i3c_master *master,
0614                     unsigned int slot)
0615 {
0616     master->free_slots |= BIT(slot);
0617 }
0618 
0619 static int svc_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
0620 {
0621     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0622     struct svc_i3c_master *master = to_svc_i3c_master(m);
0623     struct svc_i3c_i2c_dev_data *data;
0624     int slot;
0625 
0626     slot = svc_i3c_master_reserve_slot(master);
0627     if (slot < 0)
0628         return slot;
0629 
0630     data = kzalloc(sizeof(*data), GFP_KERNEL);
0631     if (!data) {
0632         svc_i3c_master_release_slot(master, slot);
0633         return -ENOMEM;
0634     }
0635 
0636     data->ibi = -1;
0637     data->index = slot;
0638     master->addrs[slot] = dev->info.dyn_addr ? dev->info.dyn_addr :
0639                            dev->info.static_addr;
0640     master->descs[slot] = dev;
0641 
0642     i3c_dev_set_master_data(dev, data);
0643 
0644     return 0;
0645 }
0646 
0647 static int svc_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
0648                        u8 old_dyn_addr)
0649 {
0650     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0651     struct svc_i3c_master *master = to_svc_i3c_master(m);
0652     struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
0653 
0654     master->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr :
0655                               dev->info.static_addr;
0656 
0657     return 0;
0658 }
0659 
0660 static void svc_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
0661 {
0662     struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
0663     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0664     struct svc_i3c_master *master = to_svc_i3c_master(m);
0665 
0666     master->addrs[data->index] = 0;
0667     svc_i3c_master_release_slot(master, data->index);
0668 
0669     kfree(data);
0670 }
0671 
0672 static int svc_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
0673 {
0674     struct i3c_master_controller *m = i2c_dev_get_master(dev);
0675     struct svc_i3c_master *master = to_svc_i3c_master(m);
0676     struct svc_i3c_i2c_dev_data *data;
0677     int slot;
0678 
0679     slot = svc_i3c_master_reserve_slot(master);
0680     if (slot < 0)
0681         return slot;
0682 
0683     data = kzalloc(sizeof(*data), GFP_KERNEL);
0684     if (!data) {
0685         svc_i3c_master_release_slot(master, slot);
0686         return -ENOMEM;
0687     }
0688 
0689     data->index = slot;
0690     master->addrs[slot] = dev->addr;
0691 
0692     i2c_dev_set_master_data(dev, data);
0693 
0694     return 0;
0695 }
0696 
0697 static void svc_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
0698 {
0699     struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
0700     struct i3c_master_controller *m = i2c_dev_get_master(dev);
0701     struct svc_i3c_master *master = to_svc_i3c_master(m);
0702 
0703     svc_i3c_master_release_slot(master, data->index);
0704 
0705     kfree(data);
0706 }
0707 
0708 static int svc_i3c_master_readb(struct svc_i3c_master *master, u8 *dst,
0709                 unsigned int len)
0710 {
0711     int ret, i;
0712     u32 reg;
0713 
0714     for (i = 0; i < len; i++) {
0715         ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
0716                         reg,
0717                         SVC_I3C_MSTATUS_RXPEND(reg),
0718                         0, 1000);
0719         if (ret)
0720             return ret;
0721 
0722         dst[i] = readl(master->regs + SVC_I3C_MRDATAB);
0723     }
0724 
0725     return 0;
0726 }
0727 
0728 static int svc_i3c_master_do_daa_locked(struct svc_i3c_master *master,
0729                     u8 *addrs, unsigned int *count)
0730 {
0731     u64 prov_id[SVC_I3C_MAX_DEVS] = {}, nacking_prov_id = 0;
0732     unsigned int dev_nb = 0, last_addr = 0;
0733     u32 reg;
0734     int ret, i;
0735 
0736     while (true) {
0737         /* Enter/proceed with DAA */
0738         writel(SVC_I3C_MCTRL_REQUEST_PROC_DAA |
0739                SVC_I3C_MCTRL_TYPE_I3C |
0740                SVC_I3C_MCTRL_IBIRESP_NACK |
0741                SVC_I3C_MCTRL_DIR(SVC_I3C_MCTRL_DIR_WRITE),
0742                master->regs + SVC_I3C_MCTRL);
0743 
0744         /*
0745          * Either one slave will send its ID, or the assignment process
0746          * is done.
0747          */
0748         ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
0749                         reg,
0750                         SVC_I3C_MSTATUS_RXPEND(reg) |
0751                         SVC_I3C_MSTATUS_MCTRLDONE(reg),
0752                         1, 1000);
0753         if (ret)
0754             return ret;
0755 
0756         if (SVC_I3C_MSTATUS_RXPEND(reg)) {
0757             u8 data[6];
0758 
0759             /*
0760              * We only care about the 48-bit provisional ID yet to
0761              * be sure a device does not nack an address twice.
0762              * Otherwise, we would just need to flush the RX FIFO.
0763              */
0764             ret = svc_i3c_master_readb(master, data, 6);
0765             if (ret)
0766                 return ret;
0767 
0768             for (i = 0; i < 6; i++)
0769                 prov_id[dev_nb] |= (u64)(data[i]) << (8 * (5 - i));
0770 
0771             /* We do not care about the BCR and DCR yet */
0772             ret = svc_i3c_master_readb(master, data, 2);
0773             if (ret)
0774                 return ret;
0775         } else if (SVC_I3C_MSTATUS_MCTRLDONE(reg)) {
0776             if (SVC_I3C_MSTATUS_STATE_IDLE(reg) &&
0777                 SVC_I3C_MSTATUS_COMPLETE(reg)) {
0778                 /*
0779                  * All devices received and acked they dynamic
0780                  * address, this is the natural end of the DAA
0781                  * procedure.
0782                  */
0783                 break;
0784             } else if (SVC_I3C_MSTATUS_NACKED(reg)) {
0785                 /*
0786                  * A slave device nacked the address, this is
0787                  * allowed only once, DAA will be stopped and
0788                  * then resumed. The same device is supposed to
0789                  * answer again immediately and shall ack the
0790                  * address this time.
0791                  */
0792                 if (prov_id[dev_nb] == nacking_prov_id)
0793                     return -EIO;
0794 
0795                 dev_nb--;
0796                 nacking_prov_id = prov_id[dev_nb];
0797                 svc_i3c_master_emit_stop(master);
0798 
0799                 continue;
0800             } else {
0801                 return -EIO;
0802             }
0803         }
0804 
0805         /* Wait for the slave to be ready to receive its address */
0806         ret = readl_poll_timeout_atomic(master->regs + SVC_I3C_MSTATUS,
0807                         reg,
0808                         SVC_I3C_MSTATUS_MCTRLDONE(reg) &&
0809                         SVC_I3C_MSTATUS_STATE_DAA(reg) &&
0810                         SVC_I3C_MSTATUS_BETWEEN(reg),
0811                         0, 1000);
0812         if (ret)
0813             return ret;
0814 
0815         /* Give the slave device a suitable dynamic address */
0816         ret = i3c_master_get_free_addr(&master->base, last_addr + 1);
0817         if (ret < 0)
0818             return ret;
0819 
0820         addrs[dev_nb] = ret;
0821         dev_dbg(master->dev, "DAA: device %d assigned to 0x%02x\n",
0822             dev_nb, addrs[dev_nb]);
0823 
0824         writel(addrs[dev_nb], master->regs + SVC_I3C_MWDATAB);
0825         last_addr = addrs[dev_nb++];
0826     }
0827 
0828     *count = dev_nb;
0829 
0830     return 0;
0831 }
0832 
0833 static int svc_i3c_update_ibirules(struct svc_i3c_master *master)
0834 {
0835     struct i3c_dev_desc *dev;
0836     u32 reg_mbyte = 0, reg_nobyte = SVC_I3C_IBIRULES_NOBYTE;
0837     unsigned int mbyte_addr_ok = 0, mbyte_addr_ko = 0, nobyte_addr_ok = 0,
0838         nobyte_addr_ko = 0;
0839     bool list_mbyte = false, list_nobyte = false;
0840 
0841     /* Create the IBIRULES register for both cases */
0842     i3c_bus_for_each_i3cdev(&master->base.bus, dev) {
0843         if (I3C_BCR_DEVICE_ROLE(dev->info.bcr) == I3C_BCR_I3C_MASTER)
0844             continue;
0845 
0846         if (dev->info.bcr & I3C_BCR_IBI_PAYLOAD) {
0847             reg_mbyte |= SVC_I3C_IBIRULES_ADDR(mbyte_addr_ok,
0848                                dev->info.dyn_addr);
0849 
0850             /* IBI rules cannot be applied to devices with MSb=1 */
0851             if (dev->info.dyn_addr & BIT(7))
0852                 mbyte_addr_ko++;
0853             else
0854                 mbyte_addr_ok++;
0855         } else {
0856             reg_nobyte |= SVC_I3C_IBIRULES_ADDR(nobyte_addr_ok,
0857                                 dev->info.dyn_addr);
0858 
0859             /* IBI rules cannot be applied to devices with MSb=1 */
0860             if (dev->info.dyn_addr & BIT(7))
0861                 nobyte_addr_ko++;
0862             else
0863                 nobyte_addr_ok++;
0864         }
0865     }
0866 
0867     /* Device list cannot be handled by hardware */
0868     if (!mbyte_addr_ko && mbyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS)
0869         list_mbyte = true;
0870 
0871     if (!nobyte_addr_ko && nobyte_addr_ok <= SVC_I3C_IBIRULES_ADDRS)
0872         list_nobyte = true;
0873 
0874     /* No list can be properly handled, return an error */
0875     if (!list_mbyte && !list_nobyte)
0876         return -ERANGE;
0877 
0878     /* Pick the first list that can be handled by hardware, randomly */
0879     if (list_mbyte)
0880         writel(reg_mbyte, master->regs + SVC_I3C_IBIRULES);
0881     else
0882         writel(reg_nobyte, master->regs + SVC_I3C_IBIRULES);
0883 
0884     return 0;
0885 }
0886 
0887 static int svc_i3c_master_do_daa(struct i3c_master_controller *m)
0888 {
0889     struct svc_i3c_master *master = to_svc_i3c_master(m);
0890     u8 addrs[SVC_I3C_MAX_DEVS];
0891     unsigned long flags;
0892     unsigned int dev_nb;
0893     int ret, i;
0894 
0895     ret = pm_runtime_resume_and_get(master->dev);
0896     if (ret < 0) {
0897         dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
0898         return ret;
0899     }
0900 
0901     spin_lock_irqsave(&master->xferqueue.lock, flags);
0902     ret = svc_i3c_master_do_daa_locked(master, addrs, &dev_nb);
0903     spin_unlock_irqrestore(&master->xferqueue.lock, flags);
0904     if (ret) {
0905         svc_i3c_master_emit_stop(master);
0906         svc_i3c_master_clear_merrwarn(master);
0907         goto rpm_out;
0908     }
0909 
0910     /* Register all devices who participated to the core */
0911     for (i = 0; i < dev_nb; i++) {
0912         ret = i3c_master_add_i3c_dev_locked(m, addrs[i]);
0913         if (ret)
0914             goto rpm_out;
0915     }
0916 
0917     /* Configure IBI auto-rules */
0918     ret = svc_i3c_update_ibirules(master);
0919     if (ret)
0920         dev_err(master->dev, "Cannot handle such a list of devices");
0921 
0922 rpm_out:
0923     pm_runtime_mark_last_busy(master->dev);
0924     pm_runtime_put_autosuspend(master->dev);
0925 
0926     return ret;
0927 }
0928 
0929 static int svc_i3c_master_read(struct svc_i3c_master *master,
0930                    u8 *in, unsigned int len)
0931 {
0932     int offset = 0, i;
0933     u32 mdctrl, mstatus;
0934     bool completed = false;
0935     unsigned int count;
0936     unsigned long start = jiffies;
0937 
0938     while (!completed) {
0939         mstatus = readl(master->regs + SVC_I3C_MSTATUS);
0940         if (SVC_I3C_MSTATUS_COMPLETE(mstatus) != 0)
0941             completed = true;
0942 
0943         if (time_after(jiffies, start + msecs_to_jiffies(1000))) {
0944             dev_dbg(master->dev, "I3C read timeout\n");
0945             return -ETIMEDOUT;
0946         }
0947 
0948         mdctrl = readl(master->regs + SVC_I3C_MDATACTRL);
0949         count = SVC_I3C_MDATACTRL_RXCOUNT(mdctrl);
0950         if (offset + count > len) {
0951             dev_err(master->dev, "I3C receive length too long!\n");
0952             return -EINVAL;
0953         }
0954         for (i = 0; i < count; i++)
0955             in[offset + i] = readl(master->regs + SVC_I3C_MRDATAB);
0956 
0957         offset += count;
0958     }
0959 
0960     return offset;
0961 }
0962 
0963 static int svc_i3c_master_write(struct svc_i3c_master *master,
0964                 const u8 *out, unsigned int len)
0965 {
0966     int offset = 0, ret;
0967     u32 mdctrl;
0968 
0969     while (offset < len) {
0970         ret = readl_poll_timeout(master->regs + SVC_I3C_MDATACTRL,
0971                      mdctrl,
0972                      !(mdctrl & SVC_I3C_MDATACTRL_TXFULL),
0973                      0, 1000);
0974         if (ret)
0975             return ret;
0976 
0977         /*
0978          * The last byte to be sent over the bus must either have the
0979          * "end" bit set or be written in MWDATABE.
0980          */
0981         if (likely(offset < (len - 1)))
0982             writel(out[offset++], master->regs + SVC_I3C_MWDATAB);
0983         else
0984             writel(out[offset++], master->regs + SVC_I3C_MWDATABE);
0985     }
0986 
0987     return 0;
0988 }
0989 
0990 static int svc_i3c_master_xfer(struct svc_i3c_master *master,
0991                    bool rnw, unsigned int xfer_type, u8 addr,
0992                    u8 *in, const u8 *out, unsigned int xfer_len,
0993                    unsigned int *read_len, bool continued)
0994 {
0995     u32 reg;
0996     int ret;
0997 
0998     writel(SVC_I3C_MCTRL_REQUEST_START_ADDR |
0999            xfer_type |
1000            SVC_I3C_MCTRL_IBIRESP_NACK |
1001            SVC_I3C_MCTRL_DIR(rnw) |
1002            SVC_I3C_MCTRL_ADDR(addr) |
1003            SVC_I3C_MCTRL_RDTERM(*read_len),
1004            master->regs + SVC_I3C_MCTRL);
1005 
1006     ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1007                  SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000);
1008     if (ret)
1009         goto emit_stop;
1010 
1011     if (rnw)
1012         ret = svc_i3c_master_read(master, in, xfer_len);
1013     else
1014         ret = svc_i3c_master_write(master, out, xfer_len);
1015     if (ret < 0)
1016         goto emit_stop;
1017 
1018     if (rnw)
1019         *read_len = ret;
1020 
1021     ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1022                  SVC_I3C_MSTATUS_COMPLETE(reg), 0, 1000);
1023     if (ret)
1024         goto emit_stop;
1025 
1026     writel(SVC_I3C_MINT_COMPLETE, master->regs + SVC_I3C_MSTATUS);
1027 
1028     if (!continued) {
1029         svc_i3c_master_emit_stop(master);
1030 
1031         /* Wait idle if stop is sent. */
1032         readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
1033                    SVC_I3C_MSTATUS_STATE_IDLE(reg), 0, 1000);
1034     }
1035 
1036     return 0;
1037 
1038 emit_stop:
1039     svc_i3c_master_emit_stop(master);
1040     svc_i3c_master_clear_merrwarn(master);
1041 
1042     return ret;
1043 }
1044 
1045 static struct svc_i3c_xfer *
1046 svc_i3c_master_alloc_xfer(struct svc_i3c_master *master, unsigned int ncmds)
1047 {
1048     struct svc_i3c_xfer *xfer;
1049 
1050     xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
1051     if (!xfer)
1052         return NULL;
1053 
1054     INIT_LIST_HEAD(&xfer->node);
1055     xfer->ncmds = ncmds;
1056     xfer->ret = -ETIMEDOUT;
1057 
1058     return xfer;
1059 }
1060 
1061 static void svc_i3c_master_free_xfer(struct svc_i3c_xfer *xfer)
1062 {
1063     kfree(xfer);
1064 }
1065 
1066 static void svc_i3c_master_dequeue_xfer_locked(struct svc_i3c_master *master,
1067                            struct svc_i3c_xfer *xfer)
1068 {
1069     if (master->xferqueue.cur == xfer)
1070         master->xferqueue.cur = NULL;
1071     else
1072         list_del_init(&xfer->node);
1073 }
1074 
1075 static void svc_i3c_master_dequeue_xfer(struct svc_i3c_master *master,
1076                     struct svc_i3c_xfer *xfer)
1077 {
1078     unsigned long flags;
1079 
1080     spin_lock_irqsave(&master->xferqueue.lock, flags);
1081     svc_i3c_master_dequeue_xfer_locked(master, xfer);
1082     spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1083 }
1084 
1085 static void svc_i3c_master_start_xfer_locked(struct svc_i3c_master *master)
1086 {
1087     struct svc_i3c_xfer *xfer = master->xferqueue.cur;
1088     int ret, i;
1089 
1090     if (!xfer)
1091         return;
1092 
1093     ret = pm_runtime_resume_and_get(master->dev);
1094     if (ret < 0) {
1095         dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1096         return;
1097     }
1098 
1099     svc_i3c_master_clear_merrwarn(master);
1100     svc_i3c_master_flush_fifo(master);
1101 
1102     for (i = 0; i < xfer->ncmds; i++) {
1103         struct svc_i3c_cmd *cmd = &xfer->cmds[i];
1104 
1105         ret = svc_i3c_master_xfer(master, cmd->rnw, xfer->type,
1106                       cmd->addr, cmd->in, cmd->out,
1107                       cmd->len, &cmd->read_len,
1108                       cmd->continued);
1109         if (ret)
1110             break;
1111     }
1112 
1113     pm_runtime_mark_last_busy(master->dev);
1114     pm_runtime_put_autosuspend(master->dev);
1115 
1116     xfer->ret = ret;
1117     complete(&xfer->comp);
1118 
1119     if (ret < 0)
1120         svc_i3c_master_dequeue_xfer_locked(master, xfer);
1121 
1122     xfer = list_first_entry_or_null(&master->xferqueue.list,
1123                     struct svc_i3c_xfer,
1124                     node);
1125     if (xfer)
1126         list_del_init(&xfer->node);
1127 
1128     master->xferqueue.cur = xfer;
1129     svc_i3c_master_start_xfer_locked(master);
1130 }
1131 
1132 static void svc_i3c_master_enqueue_xfer(struct svc_i3c_master *master,
1133                     struct svc_i3c_xfer *xfer)
1134 {
1135     unsigned long flags;
1136 
1137     init_completion(&xfer->comp);
1138     spin_lock_irqsave(&master->xferqueue.lock, flags);
1139     if (master->xferqueue.cur) {
1140         list_add_tail(&xfer->node, &master->xferqueue.list);
1141     } else {
1142         master->xferqueue.cur = xfer;
1143         svc_i3c_master_start_xfer_locked(master);
1144     }
1145     spin_unlock_irqrestore(&master->xferqueue.lock, flags);
1146 }
1147 
1148 static bool
1149 svc_i3c_master_supports_ccc_cmd(struct i3c_master_controller *master,
1150                 const struct i3c_ccc_cmd *cmd)
1151 {
1152     /* No software support for CCC commands targeting more than one slave */
1153     return (cmd->ndests == 1);
1154 }
1155 
1156 static int svc_i3c_master_send_bdcast_ccc_cmd(struct svc_i3c_master *master,
1157                           struct i3c_ccc_cmd *ccc)
1158 {
1159     unsigned int xfer_len = ccc->dests[0].payload.len + 1;
1160     struct svc_i3c_xfer *xfer;
1161     struct svc_i3c_cmd *cmd;
1162     u8 *buf;
1163     int ret;
1164 
1165     xfer = svc_i3c_master_alloc_xfer(master, 1);
1166     if (!xfer)
1167         return -ENOMEM;
1168 
1169     buf = kmalloc(xfer_len, GFP_KERNEL);
1170     if (!buf) {
1171         svc_i3c_master_free_xfer(xfer);
1172         return -ENOMEM;
1173     }
1174 
1175     buf[0] = ccc->id;
1176     memcpy(&buf[1], ccc->dests[0].payload.data, ccc->dests[0].payload.len);
1177 
1178     xfer->type = SVC_I3C_MCTRL_TYPE_I3C;
1179 
1180     cmd = &xfer->cmds[0];
1181     cmd->addr = ccc->dests[0].addr;
1182     cmd->rnw = ccc->rnw;
1183     cmd->in = NULL;
1184     cmd->out = buf;
1185     cmd->len = xfer_len;
1186     cmd->read_len = 0;
1187     cmd->continued = false;
1188 
1189     svc_i3c_master_enqueue_xfer(master, xfer);
1190     if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1191         svc_i3c_master_dequeue_xfer(master, xfer);
1192 
1193     ret = xfer->ret;
1194     kfree(buf);
1195     svc_i3c_master_free_xfer(xfer);
1196 
1197     return ret;
1198 }
1199 
1200 static int svc_i3c_master_send_direct_ccc_cmd(struct svc_i3c_master *master,
1201                           struct i3c_ccc_cmd *ccc)
1202 {
1203     unsigned int xfer_len = ccc->dests[0].payload.len;
1204     unsigned int read_len = ccc->rnw ? xfer_len : 0;
1205     struct svc_i3c_xfer *xfer;
1206     struct svc_i3c_cmd *cmd;
1207     int ret;
1208 
1209     xfer = svc_i3c_master_alloc_xfer(master, 2);
1210     if (!xfer)
1211         return -ENOMEM;
1212 
1213     xfer->type = SVC_I3C_MCTRL_TYPE_I3C;
1214 
1215     /* Broadcasted message */
1216     cmd = &xfer->cmds[0];
1217     cmd->addr = I3C_BROADCAST_ADDR;
1218     cmd->rnw = 0;
1219     cmd->in = NULL;
1220     cmd->out = &ccc->id;
1221     cmd->len = 1;
1222     cmd->read_len = 0;
1223     cmd->continued = true;
1224 
1225     /* Directed message */
1226     cmd = &xfer->cmds[1];
1227     cmd->addr = ccc->dests[0].addr;
1228     cmd->rnw = ccc->rnw;
1229     cmd->in = ccc->rnw ? ccc->dests[0].payload.data : NULL;
1230     cmd->out = ccc->rnw ? NULL : ccc->dests[0].payload.data,
1231     cmd->len = xfer_len;
1232     cmd->read_len = read_len;
1233     cmd->continued = false;
1234 
1235     svc_i3c_master_enqueue_xfer(master, xfer);
1236     if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1237         svc_i3c_master_dequeue_xfer(master, xfer);
1238 
1239     if (cmd->read_len != xfer_len)
1240         ccc->dests[0].payload.len = cmd->read_len;
1241 
1242     ret = xfer->ret;
1243     svc_i3c_master_free_xfer(xfer);
1244 
1245     return ret;
1246 }
1247 
1248 static int svc_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
1249                        struct i3c_ccc_cmd *cmd)
1250 {
1251     struct svc_i3c_master *master = to_svc_i3c_master(m);
1252     bool broadcast = cmd->id < 0x80;
1253 
1254     if (broadcast)
1255         return svc_i3c_master_send_bdcast_ccc_cmd(master, cmd);
1256     else
1257         return svc_i3c_master_send_direct_ccc_cmd(master, cmd);
1258 }
1259 
1260 static int svc_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
1261                      struct i3c_priv_xfer *xfers,
1262                      int nxfers)
1263 {
1264     struct i3c_master_controller *m = i3c_dev_get_master(dev);
1265     struct svc_i3c_master *master = to_svc_i3c_master(m);
1266     struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1267     struct svc_i3c_xfer *xfer;
1268     int ret, i;
1269 
1270     xfer = svc_i3c_master_alloc_xfer(master, nxfers);
1271     if (!xfer)
1272         return -ENOMEM;
1273 
1274     xfer->type = SVC_I3C_MCTRL_TYPE_I3C;
1275 
1276     for (i = 0; i < nxfers; i++) {
1277         struct svc_i3c_cmd *cmd = &xfer->cmds[i];
1278 
1279         cmd->addr = master->addrs[data->index];
1280         cmd->rnw = xfers[i].rnw;
1281         cmd->in = xfers[i].rnw ? xfers[i].data.in : NULL;
1282         cmd->out = xfers[i].rnw ? NULL : xfers[i].data.out;
1283         cmd->len = xfers[i].len;
1284         cmd->read_len = xfers[i].rnw ? xfers[i].len : 0;
1285         cmd->continued = (i + 1) < nxfers;
1286     }
1287 
1288     svc_i3c_master_enqueue_xfer(master, xfer);
1289     if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1290         svc_i3c_master_dequeue_xfer(master, xfer);
1291 
1292     ret = xfer->ret;
1293     svc_i3c_master_free_xfer(xfer);
1294 
1295     return ret;
1296 }
1297 
1298 static int svc_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
1299                     const struct i2c_msg *xfers,
1300                     int nxfers)
1301 {
1302     struct i3c_master_controller *m = i2c_dev_get_master(dev);
1303     struct svc_i3c_master *master = to_svc_i3c_master(m);
1304     struct svc_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1305     struct svc_i3c_xfer *xfer;
1306     int ret, i;
1307 
1308     xfer = svc_i3c_master_alloc_xfer(master, nxfers);
1309     if (!xfer)
1310         return -ENOMEM;
1311 
1312     xfer->type = SVC_I3C_MCTRL_TYPE_I2C;
1313 
1314     for (i = 0; i < nxfers; i++) {
1315         struct svc_i3c_cmd *cmd = &xfer->cmds[i];
1316 
1317         cmd->addr = master->addrs[data->index];
1318         cmd->rnw = xfers[i].flags & I2C_M_RD;
1319         cmd->in = cmd->rnw ? xfers[i].buf : NULL;
1320         cmd->out = cmd->rnw ? NULL : xfers[i].buf;
1321         cmd->len = xfers[i].len;
1322         cmd->read_len = cmd->rnw ? xfers[i].len : 0;
1323         cmd->continued = (i + 1 < nxfers);
1324     }
1325 
1326     svc_i3c_master_enqueue_xfer(master, xfer);
1327     if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000)))
1328         svc_i3c_master_dequeue_xfer(master, xfer);
1329 
1330     ret = xfer->ret;
1331     svc_i3c_master_free_xfer(xfer);
1332 
1333     return ret;
1334 }
1335 
1336 static int svc_i3c_master_request_ibi(struct i3c_dev_desc *dev,
1337                       const struct i3c_ibi_setup *req)
1338 {
1339     struct i3c_master_controller *m = i3c_dev_get_master(dev);
1340     struct svc_i3c_master *master = to_svc_i3c_master(m);
1341     struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1342     unsigned long flags;
1343     unsigned int i;
1344 
1345     if (dev->ibi->max_payload_len > SVC_I3C_FIFO_SIZE) {
1346         dev_err(master->dev, "IBI max payload %d should be < %d\n",
1347             dev->ibi->max_payload_len, SVC_I3C_FIFO_SIZE);
1348         return -ERANGE;
1349     }
1350 
1351     data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req);
1352     if (IS_ERR(data->ibi_pool))
1353         return PTR_ERR(data->ibi_pool);
1354 
1355     spin_lock_irqsave(&master->ibi.lock, flags);
1356     for (i = 0; i < master->ibi.num_slots; i++) {
1357         if (!master->ibi.slots[i]) {
1358             data->ibi = i;
1359             master->ibi.slots[i] = dev;
1360             break;
1361         }
1362     }
1363     spin_unlock_irqrestore(&master->ibi.lock, flags);
1364 
1365     if (i < master->ibi.num_slots)
1366         return 0;
1367 
1368     i3c_generic_ibi_free_pool(data->ibi_pool);
1369     data->ibi_pool = NULL;
1370 
1371     return -ENOSPC;
1372 }
1373 
1374 static void svc_i3c_master_free_ibi(struct i3c_dev_desc *dev)
1375 {
1376     struct i3c_master_controller *m = i3c_dev_get_master(dev);
1377     struct svc_i3c_master *master = to_svc_i3c_master(m);
1378     struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1379     unsigned long flags;
1380 
1381     spin_lock_irqsave(&master->ibi.lock, flags);
1382     master->ibi.slots[data->ibi] = NULL;
1383     data->ibi = -1;
1384     spin_unlock_irqrestore(&master->ibi.lock, flags);
1385 
1386     i3c_generic_ibi_free_pool(data->ibi_pool);
1387 }
1388 
1389 static int svc_i3c_master_enable_ibi(struct i3c_dev_desc *dev)
1390 {
1391     struct i3c_master_controller *m = i3c_dev_get_master(dev);
1392     struct svc_i3c_master *master = to_svc_i3c_master(m);
1393     int ret;
1394 
1395     ret = pm_runtime_resume_and_get(master->dev);
1396     if (ret < 0) {
1397         dev_err(master->dev, "<%s> Cannot get runtime PM.\n", __func__);
1398         return ret;
1399     }
1400 
1401     svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART);
1402 
1403     return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1404 }
1405 
1406 static int svc_i3c_master_disable_ibi(struct i3c_dev_desc *dev)
1407 {
1408     struct i3c_master_controller *m = i3c_dev_get_master(dev);
1409     struct svc_i3c_master *master = to_svc_i3c_master(m);
1410     int ret;
1411 
1412     svc_i3c_master_disable_interrupts(master);
1413 
1414     ret = i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
1415 
1416     pm_runtime_mark_last_busy(master->dev);
1417     pm_runtime_put_autosuspend(master->dev);
1418 
1419     return ret;
1420 }
1421 
1422 static void svc_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev,
1423                         struct i3c_ibi_slot *slot)
1424 {
1425     struct svc_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
1426 
1427     i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
1428 }
1429 
1430 static const struct i3c_master_controller_ops svc_i3c_master_ops = {
1431     .bus_init = svc_i3c_master_bus_init,
1432     .bus_cleanup = svc_i3c_master_bus_cleanup,
1433     .attach_i3c_dev = svc_i3c_master_attach_i3c_dev,
1434     .detach_i3c_dev = svc_i3c_master_detach_i3c_dev,
1435     .reattach_i3c_dev = svc_i3c_master_reattach_i3c_dev,
1436     .attach_i2c_dev = svc_i3c_master_attach_i2c_dev,
1437     .detach_i2c_dev = svc_i3c_master_detach_i2c_dev,
1438     .do_daa = svc_i3c_master_do_daa,
1439     .supports_ccc_cmd = svc_i3c_master_supports_ccc_cmd,
1440     .send_ccc_cmd = svc_i3c_master_send_ccc_cmd,
1441     .priv_xfers = svc_i3c_master_priv_xfers,
1442     .i2c_xfers = svc_i3c_master_i2c_xfers,
1443     .request_ibi = svc_i3c_master_request_ibi,
1444     .free_ibi = svc_i3c_master_free_ibi,
1445     .recycle_ibi_slot = svc_i3c_master_recycle_ibi_slot,
1446     .enable_ibi = svc_i3c_master_enable_ibi,
1447     .disable_ibi = svc_i3c_master_disable_ibi,
1448 };
1449 
1450 static int svc_i3c_master_prepare_clks(struct svc_i3c_master *master)
1451 {
1452     int ret = 0;
1453 
1454     ret = clk_prepare_enable(master->pclk);
1455     if (ret)
1456         return ret;
1457 
1458     ret = clk_prepare_enable(master->fclk);
1459     if (ret) {
1460         clk_disable_unprepare(master->pclk);
1461         return ret;
1462     }
1463 
1464     ret = clk_prepare_enable(master->sclk);
1465     if (ret) {
1466         clk_disable_unprepare(master->pclk);
1467         clk_disable_unprepare(master->fclk);
1468         return ret;
1469     }
1470 
1471     return 0;
1472 }
1473 
1474 static void svc_i3c_master_unprepare_clks(struct svc_i3c_master *master)
1475 {
1476     clk_disable_unprepare(master->pclk);
1477     clk_disable_unprepare(master->fclk);
1478     clk_disable_unprepare(master->sclk);
1479 }
1480 
1481 static int svc_i3c_master_probe(struct platform_device *pdev)
1482 {
1483     struct device *dev = &pdev->dev;
1484     struct svc_i3c_master *master;
1485     int ret;
1486 
1487     master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
1488     if (!master)
1489         return -ENOMEM;
1490 
1491     master->regs = devm_platform_ioremap_resource(pdev, 0);
1492     if (IS_ERR(master->regs))
1493         return PTR_ERR(master->regs);
1494 
1495     master->pclk = devm_clk_get(dev, "pclk");
1496     if (IS_ERR(master->pclk))
1497         return PTR_ERR(master->pclk);
1498 
1499     master->fclk = devm_clk_get(dev, "fast_clk");
1500     if (IS_ERR(master->fclk))
1501         return PTR_ERR(master->fclk);
1502 
1503     master->sclk = devm_clk_get(dev, "slow_clk");
1504     if (IS_ERR(master->sclk))
1505         return PTR_ERR(master->sclk);
1506 
1507     master->irq = platform_get_irq(pdev, 0);
1508     if (master->irq <= 0)
1509         return -ENOENT;
1510 
1511     master->dev = dev;
1512 
1513     ret = svc_i3c_master_prepare_clks(master);
1514     if (ret)
1515         return ret;
1516 
1517     INIT_WORK(&master->hj_work, svc_i3c_master_hj_work);
1518     INIT_WORK(&master->ibi_work, svc_i3c_master_ibi_work);
1519     ret = devm_request_irq(dev, master->irq, svc_i3c_master_irq_handler,
1520                    IRQF_NO_SUSPEND, "svc-i3c-irq", master);
1521     if (ret)
1522         goto err_disable_clks;
1523 
1524     master->free_slots = GENMASK(SVC_I3C_MAX_DEVS - 1, 0);
1525 
1526     spin_lock_init(&master->xferqueue.lock);
1527     INIT_LIST_HEAD(&master->xferqueue.list);
1528 
1529     spin_lock_init(&master->ibi.lock);
1530     master->ibi.num_slots = SVC_I3C_MAX_DEVS;
1531     master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots,
1532                      sizeof(*master->ibi.slots),
1533                      GFP_KERNEL);
1534     if (!master->ibi.slots) {
1535         ret = -ENOMEM;
1536         goto err_disable_clks;
1537     }
1538 
1539     platform_set_drvdata(pdev, master);
1540 
1541     pm_runtime_set_autosuspend_delay(&pdev->dev, SVC_I3C_PM_TIMEOUT_MS);
1542     pm_runtime_use_autosuspend(&pdev->dev);
1543     pm_runtime_get_noresume(&pdev->dev);
1544     pm_runtime_set_active(&pdev->dev);
1545     pm_runtime_enable(&pdev->dev);
1546 
1547     svc_i3c_master_reset(master);
1548 
1549     /* Register the master */
1550     ret = i3c_master_register(&master->base, &pdev->dev,
1551                   &svc_i3c_master_ops, false);
1552     if (ret)
1553         goto rpm_disable;
1554 
1555     pm_runtime_mark_last_busy(&pdev->dev);
1556     pm_runtime_put_autosuspend(&pdev->dev);
1557 
1558     return 0;
1559 
1560 rpm_disable:
1561     pm_runtime_dont_use_autosuspend(&pdev->dev);
1562     pm_runtime_put_noidle(&pdev->dev);
1563     pm_runtime_set_suspended(&pdev->dev);
1564     pm_runtime_disable(&pdev->dev);
1565 
1566 err_disable_clks:
1567     svc_i3c_master_unprepare_clks(master);
1568 
1569     return ret;
1570 }
1571 
1572 static int svc_i3c_master_remove(struct platform_device *pdev)
1573 {
1574     struct svc_i3c_master *master = platform_get_drvdata(pdev);
1575     int ret;
1576 
1577     ret = i3c_master_unregister(&master->base);
1578     if (ret)
1579         return ret;
1580 
1581     pm_runtime_dont_use_autosuspend(&pdev->dev);
1582     pm_runtime_disable(&pdev->dev);
1583 
1584     return 0;
1585 }
1586 
1587 static int __maybe_unused svc_i3c_runtime_suspend(struct device *dev)
1588 {
1589     struct svc_i3c_master *master = dev_get_drvdata(dev);
1590 
1591     svc_i3c_master_unprepare_clks(master);
1592     pinctrl_pm_select_sleep_state(dev);
1593 
1594     return 0;
1595 }
1596 
1597 static int __maybe_unused svc_i3c_runtime_resume(struct device *dev)
1598 {
1599     struct svc_i3c_master *master = dev_get_drvdata(dev);
1600 
1601     pinctrl_pm_select_default_state(dev);
1602     svc_i3c_master_prepare_clks(master);
1603 
1604     return 0;
1605 }
1606 
1607 static const struct dev_pm_ops svc_i3c_pm_ops = {
1608     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1609                       pm_runtime_force_resume)
1610     SET_RUNTIME_PM_OPS(svc_i3c_runtime_suspend,
1611                svc_i3c_runtime_resume, NULL)
1612 };
1613 
1614 static const struct of_device_id svc_i3c_master_of_match_tbl[] = {
1615     { .compatible = "silvaco,i3c-master" },
1616     { /* sentinel */ },
1617 };
1618 MODULE_DEVICE_TABLE(of, svc_i3c_master_of_match_tbl);
1619 
1620 static struct platform_driver svc_i3c_master = {
1621     .probe = svc_i3c_master_probe,
1622     .remove = svc_i3c_master_remove,
1623     .driver = {
1624         .name = "silvaco-i3c-master",
1625         .of_match_table = svc_i3c_master_of_match_tbl,
1626         .pm = &svc_i3c_pm_ops,
1627     },
1628 };
1629 module_platform_driver(svc_i3c_master);
1630 
1631 MODULE_AUTHOR("Conor Culhane <conor.culhane@silvaco.com>");
1632 MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>");
1633 MODULE_DESCRIPTION("Silvaco dual-role I3C master driver");
1634 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!