master/mipi-i3c-hci/xfer_mode_rate.h

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002 /*
0003  * Copyright (c) 2020, MIPI Alliance, Inc.
0004  *
0005  * Author: Nicolas Pitre <npitre@baylibre.com>
0006  *
0007  * Transfer Mode/Rate Table definitions as found in extended capability
0008  * sections 0x04 and 0x08.
0009  * This applies starting from I3C HCI v2.0.
0010  */
0011
0012 #ifndef XFER_MODE_RATE_H
0013 #define XFER_MODE_RATE_H
0014
0015 /*
0016  * Master Transfer Mode Table Fixed Indexes.
0017  *
0018  * Indexes 0x0 and 0x8 are mandatory. Availability for the rest must be
0019  * obtained from the mode table in the extended capability area.
0020  * Presence and definitions for indexes beyond these ones may vary.
0021  */
0022 #define XFERMODE_IDX_I3C_SDR        0x00    /* I3C SDR Mode */
0023 #define XFERMODE_IDX_I3C_HDR_DDR    0x01    /* I3C HDR-DDR Mode */
0024 #define XFERMODE_IDX_I3C_HDR_T      0x02    /* I3C HDR-Ternary Mode */
0025 #define XFERMODE_IDX_I3C_HDR_BT     0x03    /* I3C HDR-BT Mode */
0026 #define XFERMODE_IDX_I2C        0x08    /* Legacy I2C Mode */
0027
0028 /*
0029  * Transfer Mode Table Entry Bits Definitions
0030  */
0031 #define XFERMODE_VALID_XFER_ADD_FUNC    GENMASK(21, 16)
0032 #define XFERMODE_ML_DATA_XFER_CODING    GENMASK(15, 11)
0033 #define XFERMODE_ML_ADDL_LANES      GENMASK(10, 8)
0034 #define XFERMODE_SUPPORTED      BIT(7)
0035 #define XFERMODE_MODE           GENMASK(3, 0)
0036
0037 /*
0038  * Master Data Transfer Rate Selector Values.
0039  *
0040  * These are the values to be used in the command descriptor XFER_RATE field
0041  * and found in the RATE_ID field below.
0042  * The I3C_SDR0, I3C_SDR1, I3C_SDR2, I3C_SDR3, I3C_SDR4 and I2C_FM rates
0043  * are required, everything else is optional and discoverable in the
0044  * Data Transfer Rate Table. Indicated are typical rates. The actual
0045  * rates may vary slightly and are also specified in the Data Transfer
0046  * Rate Table.
0047  */
0048 #define XFERRATE_I3C_SDR0       0x00    /* 12.5 MHz */
0049 #define XFERRATE_I3C_SDR1       0x01    /* 8 MHz */
0050 #define XFERRATE_I3C_SDR2       0x02    /* 6 MHz */
0051 #define XFERRATE_I3C_SDR3       0x03    /* 4 MHz */
0052 #define XFERRATE_I3C_SDR4       0x04    /* 2 MHz */
0053 #define XFERRATE_I3C_SDR_FM_FMP     0x05    /* 400 KHz / 1 MHz */
0054 #define XFERRATE_I3C_SDR_USER6      0x06    /* User Defined */
0055 #define XFERRATE_I3C_SDR_USER7      0x07    /* User Defined */
0056
0057 #define XFERRATE_I2C_FM         0x00    /* 400 KHz */
0058 #define XFERRATE_I2C_FMP        0x01    /* 1 MHz */
0059 #define XFERRATE_I2C_USER2      0x02    /* User Defined */
0060 #define XFERRATE_I2C_USER3      0x03    /* User Defined */
0061 #define XFERRATE_I2C_USER4      0x04    /* User Defined */
0062 #define XFERRATE_I2C_USER5      0x05    /* User Defined */
0063 #define XFERRATE_I2C_USER6      0x06    /* User Defined */
0064 #define XFERRATE_I2C_USER7      0x07    /* User Defined */
0065
0066 /*
0067  * Master Data Transfer Rate Table Mode ID values.
0068  */
0069 #define XFERRATE_MODE_I3C       0x00
0070 #define XFERRATE_MODE_I2C       0x08
0071
0072 /*
0073  * Master Data Transfer Rate Table Entry Bits Definitions
0074  */
0075 #define XFERRATE_MODE_ID        GENMASK(31, 28)
0076 #define XFERRATE_RATE_ID        GENMASK(22, 20)
0077 #define XFERRATE_ACTUAL_RATE_KHZ    GENMASK(19, 0)
0078
0079 #endif