master/mipi-i3c-hci/hci.h

0001 /* SPDX-License-Identifier: BSD-3-Clause */
0002 /*
0003  * Copyright (c) 2020, MIPI Alliance, Inc.
0004  *
0005  * Author: Nicolas Pitre <npitre@baylibre.com>
0006  *
0007  * Common HCI stuff
0008  */
0009
0010 #ifndef HCI_H
0011 #define HCI_H
0012
0013
0014 /* Handy logging macro to save on line length */
0015 #define DBG(x, ...) pr_devel("%s: " x "\n", __func__, ##__VA_ARGS__)
0016
0017 /* 32-bit word aware bit and mask macros */
0018 #define W0_MASK(h, l)  GENMASK((h) - 0,  (l) - 0)
0019 #define W1_MASK(h, l)  GENMASK((h) - 32, (l) - 32)
0020 #define W2_MASK(h, l)  GENMASK((h) - 64, (l) - 64)
0021 #define W3_MASK(h, l)  GENMASK((h) - 96, (l) - 96)
0022
0023 /* Same for single bit macros (trailing _ to align with W*_MASK width) */
0024 #define W0_BIT_(x)  BIT((x) - 0)
0025 #define W1_BIT_(x)  BIT((x) - 32)
0026 #define W2_BIT_(x)  BIT((x) - 64)
0027 #define W3_BIT_(x)  BIT((x) - 96)
0028
0029
0030 struct hci_cmd_ops;
0031
0032 /* Our main structure */
0033 struct i3c_hci {
0034     struct i3c_master_controller master;
0035     void __iomem *base_regs;
0036     void __iomem *DAT_regs;
0037     void __iomem *DCT_regs;
0038     void __iomem *RHS_regs;
0039     void __iomem *PIO_regs;
0040     void __iomem *EXTCAPS_regs;
0041     void __iomem *AUTOCMD_regs;
0042     void __iomem *DEBUG_regs;
0043     const struct hci_io_ops *io;
0044     void *io_data;
0045     const struct hci_cmd_ops *cmd;
0046     atomic_t next_cmd_tid;
0047     u32 caps;
0048     unsigned int quirks;
0049     unsigned int DAT_entries;
0050     unsigned int DAT_entry_size;
0051     void *DAT_data;
0052     unsigned int DCT_entries;
0053     unsigned int DCT_entry_size;
0054     u8 version_major;
0055     u8 version_minor;
0056     u8 revision;
0057     u32 vendor_mipi_id;
0058     u32 vendor_version_id;
0059     u32 vendor_product_id;
0060     void *vendor_data;
0061 };
0062
0063
0064 /*
0065  * Structure to represent a master initiated transfer.
0066  * The rnw, data and data_len fields must be initialized before calling any
0067  * hci->cmd->*() method. The cmd method will initialize cmd_desc[] and
0068  * possibly modify (clear) the data field. Then xfer->cmd_desc[0] can
0069  * be augmented with CMD_0_ROC and/or CMD_0_TOC.
0070  * The completion field needs to be initialized before queueing with
0071  * hci->io->queue_xfer(), and requires CMD_0_ROC to be set.
0072  */
0073 struct hci_xfer {
0074     u32 cmd_desc[4];
0075     u32 response;
0076     bool rnw;
0077     void *data;
0078     unsigned int data_len;
0079     unsigned int cmd_tid;
0080     struct completion *completion;
0081     union {
0082         struct {
0083             /* PIO specific */
0084             struct hci_xfer *next_xfer;
0085             struct hci_xfer *next_data;
0086             struct hci_xfer *next_resp;
0087             unsigned int data_left;
0088             u32 data_word_before_partial;
0089         };
0090         struct {
0091             /* DMA specific */
0092             dma_addr_t data_dma;
0093             int ring_number;
0094             int ring_entry;
0095         };
0096     };
0097 };
0098
0099 static inline struct hci_xfer *hci_alloc_xfer(unsigned int n)
0100 {
0101     return kcalloc(n, sizeof(struct hci_xfer), GFP_KERNEL);
0102 }
0103
0104 static inline void hci_free_xfer(struct hci_xfer *xfer, unsigned int n)
0105 {
0106     kfree(xfer);
0107 }
0108
0109
0110 /* This abstracts PIO vs DMA operations */
0111 struct hci_io_ops {
0112     bool (*irq_handler)(struct i3c_hci *hci, unsigned int mask);
0113     int (*queue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
0114     bool (*dequeue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
0115     int (*request_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
0116                const struct i3c_ibi_setup *req);
0117     void (*free_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev);
0118     void (*recycle_ibi_slot)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
0119                 struct i3c_ibi_slot *slot);
0120     int (*init)(struct i3c_hci *hci);
0121     void (*cleanup)(struct i3c_hci *hci);
0122 };
0123
0124 extern const struct hci_io_ops mipi_i3c_hci_pio;
0125 extern const struct hci_io_ops mipi_i3c_hci_dma;
0126
0127
0128 /* Our per device master private data */
0129 struct i3c_hci_dev_data {
0130     int dat_idx;
0131     void *ibi_data;
0132 };
0133
0134
0135 /* list of quirks */
0136 #define HCI_QUIRK_RAW_CCC   BIT(1)  /* CCC framing must be explicit */
0137
0138
0139 /* global functions */
0140 void mipi_i3c_hci_resume(struct i3c_hci *hci);
0141 void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
0142 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
0143
0144 #endif