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0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003  * Copyright (c) 2020, MIPI Alliance, Inc.
0004  *
0005  * Author: Nicolas Pitre <npitre@baylibre.com>
0006  *
0007  * Core driver code with main interface to the I3C subsystem.
0008  */
0009 
0010 #include <linux/bitfield.h>
0011 #include <linux/device.h>
0012 #include <linux/errno.h>
0013 #include <linux/i3c/master.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/iopoll.h>
0017 #include <linux/module.h>
0018 #include <linux/platform_device.h>
0019 
0020 #include "hci.h"
0021 #include "ext_caps.h"
0022 #include "cmd.h"
0023 #include "dat.h"
0024 
0025 
0026 /*
0027  * Host Controller Capabilities and Operation Registers
0028  */
0029 
0030 #define reg_read(r)     readl(hci->base_regs + (r))
0031 #define reg_write(r, v)     writel(v, hci->base_regs + (r))
0032 #define reg_set(r, v)       reg_write(r, reg_read(r) | (v))
0033 #define reg_clear(r, v)     reg_write(r, reg_read(r) & ~(v))
0034 
0035 #define HCI_VERSION         0x00    /* HCI Version (in BCD) */
0036 
0037 #define HC_CONTROL          0x04
0038 #define HC_CONTROL_BUS_ENABLE       BIT(31)
0039 #define HC_CONTROL_RESUME       BIT(30)
0040 #define HC_CONTROL_ABORT        BIT(29)
0041 #define HC_CONTROL_HALT_ON_CMD_TIMEOUT  BIT(12)
0042 #define HC_CONTROL_HOT_JOIN_CTRL    BIT(8)  /* Hot-Join ACK/NACK Control */
0043 #define HC_CONTROL_I2C_TARGET_PRESENT   BIT(7)
0044 #define HC_CONTROL_PIO_MODE     BIT(6)  /* DMA/PIO Mode Selector */
0045 #define HC_CONTROL_DATA_BIG_ENDIAN  BIT(4)
0046 #define HC_CONTROL_IBA_INCLUDE      BIT(0)  /* Include I3C Broadcast Address */
0047 
0048 #define MASTER_DEVICE_ADDR      0x08    /* Master Device Address */
0049 #define MASTER_DYNAMIC_ADDR_VALID   BIT(31) /* Dynamic Address is Valid */
0050 #define MASTER_DYNAMIC_ADDR(v)      FIELD_PREP(GENMASK(22, 16), v)
0051 
0052 #define HC_CAPABILITIES         0x0c
0053 #define HC_CAP_SG_DC_EN         BIT(30)
0054 #define HC_CAP_SG_IBI_EN        BIT(29)
0055 #define HC_CAP_SG_CR_EN         BIT(28)
0056 #define HC_CAP_MAX_DATA_LENGTH      GENMASK(24, 22)
0057 #define HC_CAP_CMD_SIZE         GENMASK(21, 20)
0058 #define HC_CAP_DIRECT_COMMANDS_EN   BIT(18)
0059 #define HC_CAP_MULTI_LANE_EN        BIT(15)
0060 #define HC_CAP_CMD_CCC_DEFBYTE      BIT(10)
0061 #define HC_CAP_HDR_BT_EN        BIT(8)
0062 #define HC_CAP_HDR_TS_EN        BIT(7)
0063 #define HC_CAP_HDR_DDR_EN       BIT(6)
0064 #define HC_CAP_NON_CURRENT_MASTER_CAP   BIT(5)  /* master handoff capable */
0065 #define HC_CAP_DATA_BYTE_CFG_EN     BIT(4)  /* endian selection possible */
0066 #define HC_CAP_AUTO_COMMAND     BIT(3)
0067 #define HC_CAP_COMBO_COMMAND        BIT(2)
0068 
0069 #define RESET_CONTROL           0x10
0070 #define BUS_RESET           BIT(31)
0071 #define BUS_RESET_TYPE          GENMASK(30, 29)
0072 #define IBI_QUEUE_RST           BIT(5)
0073 #define RX_FIFO_RST         BIT(4)
0074 #define TX_FIFO_RST         BIT(3)
0075 #define RESP_QUEUE_RST          BIT(2)
0076 #define CMD_QUEUE_RST           BIT(1)
0077 #define SOFT_RST            BIT(0)  /* Core Reset */
0078 
0079 #define PRESENT_STATE           0x14
0080 #define STATE_CURRENT_MASTER        BIT(2)
0081 
0082 #define INTR_STATUS         0x20
0083 #define INTR_STATUS_ENABLE      0x24
0084 #define INTR_SIGNAL_ENABLE      0x28
0085 #define INTR_FORCE          0x2c
0086 #define INTR_HC_CMD_SEQ_UFLOW_STAT  BIT(12) /* Cmd Sequence Underflow */
0087 #define INTR_HC_RESET_CANCEL        BIT(11) /* HC Cancelled Reset */
0088 #define INTR_HC_INTERNAL_ERR        BIT(10) /* HC Internal Error */
0089 #define INTR_HC_PIO         BIT(8)  /* cascaded PIO interrupt */
0090 #define INTR_HC_RINGS           GENMASK(7, 0)
0091 
0092 #define DAT_SECTION         0x30    /* Device Address Table */
0093 #define DAT_ENTRY_SIZE          GENMASK(31, 28)
0094 #define DAT_TABLE_SIZE          GENMASK(18, 12)
0095 #define DAT_TABLE_OFFSET        GENMASK(11, 0)
0096 
0097 #define DCT_SECTION         0x34    /* Device Characteristics Table */
0098 #define DCT_ENTRY_SIZE          GENMASK(31, 28)
0099 #define DCT_TABLE_INDEX         GENMASK(23, 19)
0100 #define DCT_TABLE_SIZE          GENMASK(18, 12)
0101 #define DCT_TABLE_OFFSET        GENMASK(11, 0)
0102 
0103 #define RING_HEADERS_SECTION        0x38
0104 #define RING_HEADERS_OFFSET     GENMASK(15, 0)
0105 
0106 #define PIO_SECTION         0x3c
0107 #define PIO_REGS_OFFSET         GENMASK(15, 0)  /* PIO Offset */
0108 
0109 #define EXT_CAPS_SECTION        0x40
0110 #define EXT_CAPS_OFFSET         GENMASK(15, 0)
0111 
0112 #define IBI_NOTIFY_CTRL         0x58    /* IBI Notify Control */
0113 #define IBI_NOTIFY_SIR_REJECTED     BIT(3)  /* Rejected Target Interrupt Request */
0114 #define IBI_NOTIFY_MR_REJECTED      BIT(1)  /* Rejected Master Request Control */
0115 #define IBI_NOTIFY_HJ_REJECTED      BIT(0)  /* Rejected Hot-Join Control */
0116 
0117 #define DEV_CTX_BASE_LO         0x60
0118 #define DEV_CTX_BASE_HI         0x64
0119 
0120 
0121 static inline struct i3c_hci *to_i3c_hci(struct i3c_master_controller *m)
0122 {
0123     return container_of(m, struct i3c_hci, master);
0124 }
0125 
0126 static int i3c_hci_bus_init(struct i3c_master_controller *m)
0127 {
0128     struct i3c_hci *hci = to_i3c_hci(m);
0129     struct i3c_device_info info;
0130     int ret;
0131 
0132     DBG("");
0133 
0134     if (hci->cmd == &mipi_i3c_hci_cmd_v1) {
0135         ret = mipi_i3c_hci_dat_v1.init(hci);
0136         if (ret)
0137             return ret;
0138     }
0139 
0140     ret = i3c_master_get_free_addr(m, 0);
0141     if (ret < 0)
0142         return ret;
0143     reg_write(MASTER_DEVICE_ADDR,
0144           MASTER_DYNAMIC_ADDR(ret) | MASTER_DYNAMIC_ADDR_VALID);
0145     memset(&info, 0, sizeof(info));
0146     info.dyn_addr = ret;
0147     ret = i3c_master_set_info(m, &info);
0148     if (ret)
0149         return ret;
0150 
0151     ret = hci->io->init(hci);
0152     if (ret)
0153         return ret;
0154 
0155     reg_set(HC_CONTROL, HC_CONTROL_BUS_ENABLE);
0156     DBG("HC_CONTROL = %#x", reg_read(HC_CONTROL));
0157 
0158     return 0;
0159 }
0160 
0161 static void i3c_hci_bus_cleanup(struct i3c_master_controller *m)
0162 {
0163     struct i3c_hci *hci = to_i3c_hci(m);
0164 
0165     DBG("");
0166 
0167     reg_clear(HC_CONTROL, HC_CONTROL_BUS_ENABLE);
0168     hci->io->cleanup(hci);
0169     if (hci->cmd == &mipi_i3c_hci_cmd_v1)
0170         mipi_i3c_hci_dat_v1.cleanup(hci);
0171 }
0172 
0173 void mipi_i3c_hci_resume(struct i3c_hci *hci)
0174 {
0175     /* the HC_CONTROL_RESUME bit is R/W1C so just read and write back */
0176     reg_write(HC_CONTROL, reg_read(HC_CONTROL));
0177 }
0178 
0179 /* located here rather than pio.c because needed bits are in core reg space */
0180 void mipi_i3c_hci_pio_reset(struct i3c_hci *hci)
0181 {
0182     reg_write(RESET_CONTROL, RX_FIFO_RST | TX_FIFO_RST | RESP_QUEUE_RST);
0183 }
0184 
0185 /* located here rather than dct.c because needed bits are in core reg space */
0186 void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci)
0187 {
0188     reg_write(DCT_SECTION, FIELD_PREP(DCT_TABLE_INDEX, 0));
0189 }
0190 
0191 static int i3c_hci_send_ccc_cmd(struct i3c_master_controller *m,
0192                 struct i3c_ccc_cmd *ccc)
0193 {
0194     struct i3c_hci *hci = to_i3c_hci(m);
0195     struct hci_xfer *xfer;
0196     bool raw = !!(hci->quirks & HCI_QUIRK_RAW_CCC);
0197     bool prefixed = raw && !!(ccc->id & I3C_CCC_DIRECT);
0198     unsigned int nxfers = ccc->ndests + prefixed;
0199     DECLARE_COMPLETION_ONSTACK(done);
0200     int i, last, ret = 0;
0201 
0202     DBG("cmd=%#x rnw=%d ndests=%d data[0].len=%d",
0203         ccc->id, ccc->rnw, ccc->ndests, ccc->dests[0].payload.len);
0204 
0205     xfer = hci_alloc_xfer(nxfers);
0206     if (!xfer)
0207         return -ENOMEM;
0208 
0209     if (prefixed) {
0210         xfer->data = NULL;
0211         xfer->data_len = 0;
0212         xfer->rnw = false;
0213         hci->cmd->prep_ccc(hci, xfer, I3C_BROADCAST_ADDR,
0214                    ccc->id, true);
0215         xfer++;
0216     }
0217 
0218     for (i = 0; i < nxfers - prefixed; i++) {
0219         xfer[i].data = ccc->dests[i].payload.data;
0220         xfer[i].data_len = ccc->dests[i].payload.len;
0221         xfer[i].rnw = ccc->rnw;
0222         ret = hci->cmd->prep_ccc(hci, &xfer[i], ccc->dests[i].addr,
0223                      ccc->id, raw);
0224         if (ret)
0225             goto out;
0226         xfer[i].cmd_desc[0] |= CMD_0_ROC;
0227     }
0228     last = i - 1;
0229     xfer[last].cmd_desc[0] |= CMD_0_TOC;
0230     xfer[last].completion = &done;
0231 
0232     if (prefixed)
0233         xfer--;
0234 
0235     ret = hci->io->queue_xfer(hci, xfer, nxfers);
0236     if (ret)
0237         goto out;
0238     if (!wait_for_completion_timeout(&done, HZ) &&
0239         hci->io->dequeue_xfer(hci, xfer, nxfers)) {
0240         ret = -ETIME;
0241         goto out;
0242     }
0243     for (i = prefixed; i < nxfers; i++) {
0244         if (ccc->rnw)
0245             ccc->dests[i - prefixed].payload.len =
0246                 RESP_DATA_LENGTH(xfer[i].response);
0247         if (RESP_STATUS(xfer[i].response) != RESP_SUCCESS) {
0248             ret = -EIO;
0249             goto out;
0250         }
0251     }
0252 
0253     if (ccc->rnw)
0254         DBG("got: %*ph",
0255             ccc->dests[0].payload.len, ccc->dests[0].payload.data);
0256 
0257 out:
0258     hci_free_xfer(xfer, nxfers);
0259     return ret;
0260 }
0261 
0262 static int i3c_hci_daa(struct i3c_master_controller *m)
0263 {
0264     struct i3c_hci *hci = to_i3c_hci(m);
0265 
0266     DBG("");
0267 
0268     return hci->cmd->perform_daa(hci);
0269 }
0270 
0271 static int i3c_hci_priv_xfers(struct i3c_dev_desc *dev,
0272                   struct i3c_priv_xfer *i3c_xfers,
0273                   int nxfers)
0274 {
0275     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0276     struct i3c_hci *hci = to_i3c_hci(m);
0277     struct hci_xfer *xfer;
0278     DECLARE_COMPLETION_ONSTACK(done);
0279     unsigned int size_limit;
0280     int i, last, ret = 0;
0281 
0282     DBG("nxfers = %d", nxfers);
0283 
0284     xfer = hci_alloc_xfer(nxfers);
0285     if (!xfer)
0286         return -ENOMEM;
0287 
0288     size_limit = 1U << (16 + FIELD_GET(HC_CAP_MAX_DATA_LENGTH, hci->caps));
0289 
0290     for (i = 0; i < nxfers; i++) {
0291         xfer[i].data_len = i3c_xfers[i].len;
0292         ret = -EFBIG;
0293         if (xfer[i].data_len >= size_limit)
0294             goto out;
0295         xfer[i].rnw = i3c_xfers[i].rnw;
0296         if (i3c_xfers[i].rnw) {
0297             xfer[i].data = i3c_xfers[i].data.in;
0298         } else {
0299             /* silence the const qualifier warning with a cast */
0300             xfer[i].data = (void *) i3c_xfers[i].data.out;
0301         }
0302         hci->cmd->prep_i3c_xfer(hci, dev, &xfer[i]);
0303         xfer[i].cmd_desc[0] |= CMD_0_ROC;
0304     }
0305     last = i - 1;
0306     xfer[last].cmd_desc[0] |= CMD_0_TOC;
0307     xfer[last].completion = &done;
0308 
0309     ret = hci->io->queue_xfer(hci, xfer, nxfers);
0310     if (ret)
0311         goto out;
0312     if (!wait_for_completion_timeout(&done, HZ) &&
0313         hci->io->dequeue_xfer(hci, xfer, nxfers)) {
0314         ret = -ETIME;
0315         goto out;
0316     }
0317     for (i = 0; i < nxfers; i++) {
0318         if (i3c_xfers[i].rnw)
0319             i3c_xfers[i].len = RESP_DATA_LENGTH(xfer[i].response);
0320         if (RESP_STATUS(xfer[i].response) != RESP_SUCCESS) {
0321             ret = -EIO;
0322             goto out;
0323         }
0324     }
0325 
0326 out:
0327     hci_free_xfer(xfer, nxfers);
0328     return ret;
0329 }
0330 
0331 static int i3c_hci_i2c_xfers(struct i2c_dev_desc *dev,
0332                  const struct i2c_msg *i2c_xfers, int nxfers)
0333 {
0334     struct i3c_master_controller *m = i2c_dev_get_master(dev);
0335     struct i3c_hci *hci = to_i3c_hci(m);
0336     struct hci_xfer *xfer;
0337     DECLARE_COMPLETION_ONSTACK(done);
0338     int i, last, ret = 0;
0339 
0340     DBG("nxfers = %d", nxfers);
0341 
0342     xfer = hci_alloc_xfer(nxfers);
0343     if (!xfer)
0344         return -ENOMEM;
0345 
0346     for (i = 0; i < nxfers; i++) {
0347         xfer[i].data = i2c_xfers[i].buf;
0348         xfer[i].data_len = i2c_xfers[i].len;
0349         xfer[i].rnw = i2c_xfers[i].flags & I2C_M_RD;
0350         hci->cmd->prep_i2c_xfer(hci, dev, &xfer[i]);
0351         xfer[i].cmd_desc[0] |= CMD_0_ROC;
0352     }
0353     last = i - 1;
0354     xfer[last].cmd_desc[0] |= CMD_0_TOC;
0355     xfer[last].completion = &done;
0356 
0357     ret = hci->io->queue_xfer(hci, xfer, nxfers);
0358     if (ret)
0359         goto out;
0360     if (!wait_for_completion_timeout(&done, HZ) &&
0361         hci->io->dequeue_xfer(hci, xfer, nxfers)) {
0362         ret = -ETIME;
0363         goto out;
0364     }
0365     for (i = 0; i < nxfers; i++) {
0366         if (RESP_STATUS(xfer[i].response) != RESP_SUCCESS) {
0367             ret = -EIO;
0368             goto out;
0369         }
0370     }
0371 
0372 out:
0373     hci_free_xfer(xfer, nxfers);
0374     return ret;
0375 }
0376 
0377 static int i3c_hci_attach_i3c_dev(struct i3c_dev_desc *dev)
0378 {
0379     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0380     struct i3c_hci *hci = to_i3c_hci(m);
0381     struct i3c_hci_dev_data *dev_data;
0382     int ret;
0383 
0384     DBG("");
0385 
0386     dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
0387     if (!dev_data)
0388         return -ENOMEM;
0389     if (hci->cmd == &mipi_i3c_hci_cmd_v1) {
0390         ret = mipi_i3c_hci_dat_v1.alloc_entry(hci);
0391         if (ret < 0) {
0392             kfree(dev_data);
0393             return ret;
0394         }
0395         mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, ret, dev->info.dyn_addr);
0396         dev_data->dat_idx = ret;
0397     }
0398     i3c_dev_set_master_data(dev, dev_data);
0399     return 0;
0400 }
0401 
0402 static int i3c_hci_reattach_i3c_dev(struct i3c_dev_desc *dev, u8 old_dyn_addr)
0403 {
0404     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0405     struct i3c_hci *hci = to_i3c_hci(m);
0406     struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev);
0407 
0408     DBG("");
0409 
0410     if (hci->cmd == &mipi_i3c_hci_cmd_v1)
0411         mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, dev_data->dat_idx,
0412                          dev->info.dyn_addr);
0413     return 0;
0414 }
0415 
0416 static void i3c_hci_detach_i3c_dev(struct i3c_dev_desc *dev)
0417 {
0418     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0419     struct i3c_hci *hci = to_i3c_hci(m);
0420     struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev);
0421 
0422     DBG("");
0423 
0424     i3c_dev_set_master_data(dev, NULL);
0425     if (hci->cmd == &mipi_i3c_hci_cmd_v1)
0426         mipi_i3c_hci_dat_v1.free_entry(hci, dev_data->dat_idx);
0427     kfree(dev_data);
0428 }
0429 
0430 static int i3c_hci_attach_i2c_dev(struct i2c_dev_desc *dev)
0431 {
0432     struct i3c_master_controller *m = i2c_dev_get_master(dev);
0433     struct i3c_hci *hci = to_i3c_hci(m);
0434     struct i3c_hci_dev_data *dev_data;
0435     int ret;
0436 
0437     DBG("");
0438 
0439     if (hci->cmd != &mipi_i3c_hci_cmd_v1)
0440         return 0;
0441     dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
0442     if (!dev_data)
0443         return -ENOMEM;
0444     ret = mipi_i3c_hci_dat_v1.alloc_entry(hci);
0445     if (ret < 0) {
0446         kfree(dev_data);
0447         return ret;
0448     }
0449     mipi_i3c_hci_dat_v1.set_static_addr(hci, ret, dev->addr);
0450     mipi_i3c_hci_dat_v1.set_flags(hci, ret, DAT_0_I2C_DEVICE, 0);
0451     dev_data->dat_idx = ret;
0452     i2c_dev_set_master_data(dev, dev_data);
0453     return 0;
0454 }
0455 
0456 static void i3c_hci_detach_i2c_dev(struct i2c_dev_desc *dev)
0457 {
0458     struct i3c_master_controller *m = i2c_dev_get_master(dev);
0459     struct i3c_hci *hci = to_i3c_hci(m);
0460     struct i3c_hci_dev_data *dev_data = i2c_dev_get_master_data(dev);
0461 
0462     DBG("");
0463 
0464     if (dev_data) {
0465         i2c_dev_set_master_data(dev, NULL);
0466         if (hci->cmd == &mipi_i3c_hci_cmd_v1)
0467             mipi_i3c_hci_dat_v1.free_entry(hci, dev_data->dat_idx);
0468         kfree(dev_data);
0469     }
0470 }
0471 
0472 static int i3c_hci_request_ibi(struct i3c_dev_desc *dev,
0473                    const struct i3c_ibi_setup *req)
0474 {
0475     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0476     struct i3c_hci *hci = to_i3c_hci(m);
0477     struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev);
0478     unsigned int dat_idx = dev_data->dat_idx;
0479 
0480     if (req->max_payload_len != 0)
0481         mipi_i3c_hci_dat_v1.set_flags(hci, dat_idx, DAT_0_IBI_PAYLOAD, 0);
0482     else
0483         mipi_i3c_hci_dat_v1.clear_flags(hci, dat_idx, DAT_0_IBI_PAYLOAD, 0);
0484     return hci->io->request_ibi(hci, dev, req);
0485 }
0486 
0487 static void i3c_hci_free_ibi(struct i3c_dev_desc *dev)
0488 {
0489     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0490     struct i3c_hci *hci = to_i3c_hci(m);
0491 
0492     hci->io->free_ibi(hci, dev);
0493 }
0494 
0495 static int i3c_hci_enable_ibi(struct i3c_dev_desc *dev)
0496 {
0497     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0498     struct i3c_hci *hci = to_i3c_hci(m);
0499     struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev);
0500 
0501     mipi_i3c_hci_dat_v1.clear_flags(hci, dev_data->dat_idx, DAT_0_SIR_REJECT, 0);
0502     return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
0503 }
0504 
0505 static int i3c_hci_disable_ibi(struct i3c_dev_desc *dev)
0506 {
0507     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0508     struct i3c_hci *hci = to_i3c_hci(m);
0509     struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev);
0510 
0511     mipi_i3c_hci_dat_v1.set_flags(hci, dev_data->dat_idx, DAT_0_SIR_REJECT, 0);
0512     return i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR);
0513 }
0514 
0515 static void i3c_hci_recycle_ibi_slot(struct i3c_dev_desc *dev,
0516                      struct i3c_ibi_slot *slot)
0517 {
0518     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0519     struct i3c_hci *hci = to_i3c_hci(m);
0520 
0521     hci->io->recycle_ibi_slot(hci, dev, slot);
0522 }
0523 
0524 static const struct i3c_master_controller_ops i3c_hci_ops = {
0525     .bus_init       = i3c_hci_bus_init,
0526     .bus_cleanup        = i3c_hci_bus_cleanup,
0527     .do_daa         = i3c_hci_daa,
0528     .send_ccc_cmd       = i3c_hci_send_ccc_cmd,
0529     .priv_xfers     = i3c_hci_priv_xfers,
0530     .i2c_xfers      = i3c_hci_i2c_xfers,
0531     .attach_i3c_dev     = i3c_hci_attach_i3c_dev,
0532     .reattach_i3c_dev   = i3c_hci_reattach_i3c_dev,
0533     .detach_i3c_dev     = i3c_hci_detach_i3c_dev,
0534     .attach_i2c_dev     = i3c_hci_attach_i2c_dev,
0535     .detach_i2c_dev     = i3c_hci_detach_i2c_dev,
0536     .request_ibi        = i3c_hci_request_ibi,
0537     .free_ibi       = i3c_hci_free_ibi,
0538     .enable_ibi     = i3c_hci_enable_ibi,
0539     .disable_ibi        = i3c_hci_disable_ibi,
0540     .recycle_ibi_slot   = i3c_hci_recycle_ibi_slot,
0541 };
0542 
0543 static irqreturn_t i3c_hci_irq_handler(int irq, void *dev_id)
0544 {
0545     struct i3c_hci *hci = dev_id;
0546     irqreturn_t result = IRQ_NONE;
0547     u32 val;
0548 
0549     val = reg_read(INTR_STATUS);
0550     DBG("INTR_STATUS = %#x", val);
0551 
0552     if (val) {
0553         reg_write(INTR_STATUS, val);
0554     } else {
0555         /* v1.0 does not have PIO cascaded notification bits */
0556         val |= INTR_HC_PIO;
0557     }
0558 
0559     if (val & INTR_HC_RESET_CANCEL) {
0560         DBG("cancelled reset");
0561         val &= ~INTR_HC_RESET_CANCEL;
0562     }
0563     if (val & INTR_HC_INTERNAL_ERR) {
0564         dev_err(&hci->master.dev, "Host Controller Internal Error\n");
0565         val &= ~INTR_HC_INTERNAL_ERR;
0566     }
0567     if (val & INTR_HC_PIO) {
0568         hci->io->irq_handler(hci, 0);
0569         val &= ~INTR_HC_PIO;
0570     }
0571     if (val & INTR_HC_RINGS) {
0572         hci->io->irq_handler(hci, val & INTR_HC_RINGS);
0573         val &= ~INTR_HC_RINGS;
0574     }
0575     if (val)
0576         dev_err(&hci->master.dev, "unexpected INTR_STATUS %#x\n", val);
0577     else
0578         result = IRQ_HANDLED;
0579 
0580     return result;
0581 }
0582 
0583 static int i3c_hci_init(struct i3c_hci *hci)
0584 {
0585     u32 regval, offset;
0586     int ret;
0587 
0588     /* Validate HCI hardware version */
0589     regval = reg_read(HCI_VERSION);
0590     hci->version_major = (regval >> 8) & 0xf;
0591     hci->version_minor = (regval >> 4) & 0xf;
0592     hci->revision = regval & 0xf;
0593     dev_notice(&hci->master.dev, "MIPI I3C HCI v%u.%u r%02u\n",
0594            hci->version_major, hci->version_minor, hci->revision);
0595     /* known versions */
0596     switch (regval & ~0xf) {
0597     case 0x100: /* version 1.0 */
0598     case 0x110: /* version 1.1 */
0599     case 0x200: /* version 2.0 */
0600         break;
0601     default:
0602         dev_err(&hci->master.dev, "unsupported HCI version\n");
0603         return -EPROTONOSUPPORT;
0604     }
0605 
0606     hci->caps = reg_read(HC_CAPABILITIES);
0607     DBG("caps = %#x", hci->caps);
0608 
0609     regval = reg_read(DAT_SECTION);
0610     offset = FIELD_GET(DAT_TABLE_OFFSET, regval);
0611     hci->DAT_regs = offset ? hci->base_regs + offset : NULL;
0612     hci->DAT_entries = FIELD_GET(DAT_TABLE_SIZE, regval);
0613     hci->DAT_entry_size = FIELD_GET(DAT_ENTRY_SIZE, regval);
0614     dev_info(&hci->master.dev, "DAT: %u %u-bytes entries at offset %#x\n",
0615          hci->DAT_entries, hci->DAT_entry_size * 4, offset);
0616 
0617     regval = reg_read(DCT_SECTION);
0618     offset = FIELD_GET(DCT_TABLE_OFFSET, regval);
0619     hci->DCT_regs = offset ? hci->base_regs + offset : NULL;
0620     hci->DCT_entries = FIELD_GET(DCT_TABLE_SIZE, regval);
0621     hci->DCT_entry_size = FIELD_GET(DCT_ENTRY_SIZE, regval);
0622     dev_info(&hci->master.dev, "DCT: %u %u-bytes entries at offset %#x\n",
0623          hci->DCT_entries, hci->DCT_entry_size * 4, offset);
0624 
0625     regval = reg_read(RING_HEADERS_SECTION);
0626     offset = FIELD_GET(RING_HEADERS_OFFSET, regval);
0627     hci->RHS_regs = offset ? hci->base_regs + offset : NULL;
0628     dev_info(&hci->master.dev, "Ring Headers at offset %#x\n", offset);
0629 
0630     regval = reg_read(PIO_SECTION);
0631     offset = FIELD_GET(PIO_REGS_OFFSET, regval);
0632     hci->PIO_regs = offset ? hci->base_regs + offset : NULL;
0633     dev_info(&hci->master.dev, "PIO section at offset %#x\n", offset);
0634 
0635     regval = reg_read(EXT_CAPS_SECTION);
0636     offset = FIELD_GET(EXT_CAPS_OFFSET, regval);
0637     hci->EXTCAPS_regs = offset ? hci->base_regs + offset : NULL;
0638     dev_info(&hci->master.dev, "Extended Caps at offset %#x\n", offset);
0639 
0640     ret = i3c_hci_parse_ext_caps(hci);
0641     if (ret)
0642         return ret;
0643 
0644     /*
0645      * Now let's reset the hardware.
0646      * SOFT_RST must be clear before we write to it.
0647      * Then we must wait until it clears again.
0648      */
0649     ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval,
0650                  !(regval & SOFT_RST), 1, 10000);
0651     if (ret)
0652         return -ENXIO;
0653     reg_write(RESET_CONTROL, SOFT_RST);
0654     ret = readx_poll_timeout(reg_read, RESET_CONTROL, regval,
0655                  !(regval & SOFT_RST), 1, 10000);
0656     if (ret)
0657         return -ENXIO;
0658 
0659     /* Disable all interrupts and allow all signal updates */
0660     reg_write(INTR_SIGNAL_ENABLE, 0x0);
0661     reg_write(INTR_STATUS_ENABLE, 0xffffffff);
0662 
0663     /* Make sure our data ordering fits the host's */
0664     regval = reg_read(HC_CONTROL);
0665     if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
0666         if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
0667             regval |= HC_CONTROL_DATA_BIG_ENDIAN;
0668             reg_write(HC_CONTROL, regval);
0669             regval = reg_read(HC_CONTROL);
0670             if (!(regval & HC_CONTROL_DATA_BIG_ENDIAN)) {
0671                 dev_err(&hci->master.dev, "cannot set BE mode\n");
0672                 return -EOPNOTSUPP;
0673             }
0674         }
0675     } else {
0676         if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
0677             regval &= ~HC_CONTROL_DATA_BIG_ENDIAN;
0678             reg_write(HC_CONTROL, regval);
0679             regval = reg_read(HC_CONTROL);
0680             if (regval & HC_CONTROL_DATA_BIG_ENDIAN) {
0681                 dev_err(&hci->master.dev, "cannot clear BE mode\n");
0682                 return -EOPNOTSUPP;
0683             }
0684         }
0685     }
0686 
0687     /* Select our command descriptor model */
0688     switch (FIELD_GET(HC_CAP_CMD_SIZE, hci->caps)) {
0689     case 0:
0690         hci->cmd = &mipi_i3c_hci_cmd_v1;
0691         break;
0692     case 1:
0693         hci->cmd = &mipi_i3c_hci_cmd_v2;
0694         break;
0695     default:
0696         dev_err(&hci->master.dev, "wrong CMD_SIZE capability value\n");
0697         return -EINVAL;
0698     }
0699 
0700     /* Try activating DMA operations first */
0701     if (hci->RHS_regs) {
0702         reg_clear(HC_CONTROL, HC_CONTROL_PIO_MODE);
0703         if (reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE) {
0704             dev_err(&hci->master.dev, "PIO mode is stuck\n");
0705             ret = -EIO;
0706         } else {
0707             hci->io = &mipi_i3c_hci_dma;
0708             dev_info(&hci->master.dev, "Using DMA\n");
0709         }
0710     }
0711 
0712     /* If no DMA, try PIO */
0713     if (!hci->io && hci->PIO_regs) {
0714         reg_set(HC_CONTROL, HC_CONTROL_PIO_MODE);
0715         if (!(reg_read(HC_CONTROL) & HC_CONTROL_PIO_MODE)) {
0716             dev_err(&hci->master.dev, "DMA mode is stuck\n");
0717             ret = -EIO;
0718         } else {
0719             hci->io = &mipi_i3c_hci_pio;
0720             dev_info(&hci->master.dev, "Using PIO\n");
0721         }
0722     }
0723 
0724     if (!hci->io) {
0725         dev_err(&hci->master.dev, "neither DMA nor PIO can be used\n");
0726         if (!ret)
0727             ret = -EINVAL;
0728         return ret;
0729     }
0730 
0731     return 0;
0732 }
0733 
0734 static int i3c_hci_probe(struct platform_device *pdev)
0735 {
0736     struct i3c_hci *hci;
0737     int irq, ret;
0738 
0739     hci = devm_kzalloc(&pdev->dev, sizeof(*hci), GFP_KERNEL);
0740     if (!hci)
0741         return -ENOMEM;
0742     hci->base_regs = devm_platform_ioremap_resource(pdev, 0);
0743     if (IS_ERR(hci->base_regs))
0744         return PTR_ERR(hci->base_regs);
0745 
0746     platform_set_drvdata(pdev, hci);
0747     /* temporary for dev_printk's, to be replaced in i3c_master_register */
0748     hci->master.dev.init_name = dev_name(&pdev->dev);
0749 
0750     ret = i3c_hci_init(hci);
0751     if (ret)
0752         return ret;
0753 
0754     irq = platform_get_irq(pdev, 0);
0755     ret = devm_request_irq(&pdev->dev, irq, i3c_hci_irq_handler,
0756                    0, NULL, hci);
0757     if (ret)
0758         return ret;
0759 
0760     ret = i3c_master_register(&hci->master, &pdev->dev,
0761                   &i3c_hci_ops, false);
0762     if (ret)
0763         return ret;
0764 
0765     return 0;
0766 }
0767 
0768 static int i3c_hci_remove(struct platform_device *pdev)
0769 {
0770     struct i3c_hci *hci = platform_get_drvdata(pdev);
0771 
0772     return i3c_master_unregister(&hci->master);
0773 }
0774 
0775 static const __maybe_unused struct of_device_id i3c_hci_of_match[] = {
0776     { .compatible = "mipi-i3c-hci", },
0777     {},
0778 };
0779 MODULE_DEVICE_TABLE(of, i3c_hci_of_match);
0780 
0781 static struct platform_driver i3c_hci_driver = {
0782     .probe = i3c_hci_probe,
0783     .remove = i3c_hci_remove,
0784     .driver = {
0785         .name = "mipi-i3c-hci",
0786         .of_match_table = of_match_ptr(i3c_hci_of_match),
0787     },
0788 };
0789 module_platform_driver(i3c_hci_driver);
0790 
0791 MODULE_AUTHOR("Nicolas Pitre <npitre@baylibre.com>");
0792 MODULE_DESCRIPTION("MIPI I3C HCI driver");
0793 MODULE_LICENSE("Dual BSD/GPL");
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