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0001 // SPDX-License-Identifier: BSD-3-Clause
0002 /*
0003  * Copyright (c) 2020, MIPI Alliance, Inc.
0004  *
0005  * Author: Nicolas Pitre <npitre@baylibre.com>
0006  *
0007  * I3C HCI v2.0 Command Descriptor Handling
0008  *
0009  * Note: The I3C HCI v2.0 spec is still in flux. The code here will change.
0010  */
0011 
0012 #include <linux/bitfield.h>
0013 #include <linux/i3c/master.h>
0014 
0015 #include "hci.h"
0016 #include "cmd.h"
0017 #include "xfer_mode_rate.h"
0018 
0019 
0020 /*
0021  * Unified Data Transfer Command
0022  */
0023 
0024 #define CMD_0_ATTR_U            FIELD_PREP(CMD_0_ATTR, 0x4)
0025 
0026 #define CMD_U3_HDR_TSP_ML_CTRL(v)   FIELD_PREP(W3_MASK(107, 104), v)
0027 #define CMD_U3_IDB4(v)          FIELD_PREP(W3_MASK(103,  96), v)
0028 #define CMD_U3_HDR_CMD(v)       FIELD_PREP(W3_MASK(103,  96), v)
0029 #define CMD_U2_IDB3(v)          FIELD_PREP(W2_MASK( 95,  88), v)
0030 #define CMD_U2_HDR_BT(v)        FIELD_PREP(W2_MASK( 95,  88), v)
0031 #define CMD_U2_IDB2(v)          FIELD_PREP(W2_MASK( 87,  80), v)
0032 #define CMD_U2_BT_CMD2(v)       FIELD_PREP(W2_MASK( 87,  80), v)
0033 #define CMD_U2_IDB1(v)          FIELD_PREP(W2_MASK( 79,  72), v)
0034 #define CMD_U2_BT_CMD1(v)       FIELD_PREP(W2_MASK( 79,  72), v)
0035 #define CMD_U2_IDB0(v)          FIELD_PREP(W2_MASK( 71,  64), v)
0036 #define CMD_U2_BT_CMD0(v)       FIELD_PREP(W2_MASK( 71,  64), v)
0037 #define CMD_U1_ERR_HANDLING(v)      FIELD_PREP(W1_MASK( 63,  62), v)
0038 #define CMD_U1_ADD_FUNC(v)      FIELD_PREP(W1_MASK( 61,  56), v)
0039 #define CMD_U1_COMBO_XFER              W1_BIT_( 55)
0040 #define CMD_U1_DATA_LENGTH(v)       FIELD_PREP(W1_MASK( 53,  32), v)
0041 #define CMD_U0_TOC                 W0_BIT_( 31)
0042 #define CMD_U0_ROC                 W0_BIT_( 30)
0043 #define CMD_U0_MAY_YIELD               W0_BIT_( 29)
0044 #define CMD_U0_NACK_RCNT(v)     FIELD_PREP(W0_MASK( 28,  27), v)
0045 #define CMD_U0_IDB_COUNT(v)     FIELD_PREP(W0_MASK( 26,  24), v)
0046 #define CMD_U0_MODE_INDEX(v)        FIELD_PREP(W0_MASK( 22,  18), v)
0047 #define CMD_U0_XFER_RATE(v)     FIELD_PREP(W0_MASK( 17,  15), v)
0048 #define CMD_U0_DEV_ADDRESS(v)       FIELD_PREP(W0_MASK( 14,   8), v)
0049 #define CMD_U0_RnW                 W0_BIT_(  7)
0050 #define CMD_U0_TID(v)           FIELD_PREP(W0_MASK(  6,   3), v)
0051 
0052 /*
0053  * Address Assignment Command
0054  */
0055 
0056 #define CMD_0_ATTR_A            FIELD_PREP(CMD_0_ATTR, 0x2)
0057 
0058 #define CMD_A1_DATA_LENGTH(v)       FIELD_PREP(W1_MASK( 53,  32), v)
0059 #define CMD_A0_TOC                 W0_BIT_( 31)
0060 #define CMD_A0_ROC                 W0_BIT_( 30)
0061 #define CMD_A0_XFER_RATE(v)     FIELD_PREP(W0_MASK( 17,  15), v)
0062 #define CMD_A0_ASSIGN_ADDRESS(v)    FIELD_PREP(W0_MASK( 14,   8), v)
0063 #define CMD_A0_TID(v)           FIELD_PREP(W0_MASK(  6,   3), v)
0064 
0065 
0066 static unsigned int get_i3c_rate_idx(struct i3c_hci *hci)
0067 {
0068     struct i3c_bus *bus = i3c_master_get_bus(&hci->master);
0069 
0070     if (bus->scl_rate.i3c >= 12000000)
0071         return XFERRATE_I3C_SDR0;
0072     if (bus->scl_rate.i3c > 8000000)
0073         return XFERRATE_I3C_SDR1;
0074     if (bus->scl_rate.i3c > 6000000)
0075         return XFERRATE_I3C_SDR2;
0076     if (bus->scl_rate.i3c > 4000000)
0077         return XFERRATE_I3C_SDR3;
0078     if (bus->scl_rate.i3c > 2000000)
0079         return XFERRATE_I3C_SDR4;
0080     return XFERRATE_I3C_SDR_FM_FMP;
0081 }
0082 
0083 static unsigned int get_i2c_rate_idx(struct i3c_hci *hci)
0084 {
0085     struct i3c_bus *bus = i3c_master_get_bus(&hci->master);
0086 
0087     if (bus->scl_rate.i2c >= 1000000)
0088         return XFERRATE_I2C_FMP;
0089     return XFERRATE_I2C_FM;
0090 }
0091 
0092 static void hci_cmd_v2_prep_private_xfer(struct i3c_hci *hci,
0093                      struct hci_xfer *xfer,
0094                      u8 addr, unsigned int mode,
0095                      unsigned int rate)
0096 {
0097     u8 *data = xfer->data;
0098     unsigned int data_len = xfer->data_len;
0099     bool rnw = xfer->rnw;
0100 
0101     xfer->cmd_tid = hci_get_tid();
0102 
0103     if (!rnw && data_len <= 5) {
0104         xfer->cmd_desc[0] =
0105             CMD_0_ATTR_U |
0106             CMD_U0_TID(xfer->cmd_tid) |
0107             CMD_U0_DEV_ADDRESS(addr) |
0108             CMD_U0_XFER_RATE(rate) |
0109             CMD_U0_MODE_INDEX(mode) |
0110             CMD_U0_IDB_COUNT(data_len);
0111         xfer->cmd_desc[1] =
0112             CMD_U1_DATA_LENGTH(0);
0113         xfer->cmd_desc[2] = 0;
0114         xfer->cmd_desc[3] = 0;
0115         switch (data_len) {
0116         case 5:
0117             xfer->cmd_desc[3] |= CMD_U3_IDB4(data[4]);
0118             fallthrough;
0119         case 4:
0120             xfer->cmd_desc[2] |= CMD_U2_IDB3(data[3]);
0121             fallthrough;
0122         case 3:
0123             xfer->cmd_desc[2] |= CMD_U2_IDB2(data[2]);
0124             fallthrough;
0125         case 2:
0126             xfer->cmd_desc[2] |= CMD_U2_IDB1(data[1]);
0127             fallthrough;
0128         case 1:
0129             xfer->cmd_desc[2] |= CMD_U2_IDB0(data[0]);
0130             fallthrough;
0131         case 0:
0132             break;
0133         }
0134         /* we consumed all the data with the cmd descriptor */
0135         xfer->data = NULL;
0136     } else {
0137         xfer->cmd_desc[0] =
0138             CMD_0_ATTR_U |
0139             CMD_U0_TID(xfer->cmd_tid) |
0140             (rnw ? CMD_U0_RnW : 0) |
0141             CMD_U0_DEV_ADDRESS(addr) |
0142             CMD_U0_XFER_RATE(rate) |
0143             CMD_U0_MODE_INDEX(mode);
0144         xfer->cmd_desc[1] =
0145             CMD_U1_DATA_LENGTH(data_len);
0146         xfer->cmd_desc[2] = 0;
0147         xfer->cmd_desc[3] = 0;
0148     }
0149 }
0150 
0151 static int hci_cmd_v2_prep_ccc(struct i3c_hci *hci, struct hci_xfer *xfer,
0152                    u8 ccc_addr, u8 ccc_cmd, bool raw)
0153 {
0154     unsigned int mode = XFERMODE_IDX_I3C_SDR;
0155     unsigned int rate = get_i3c_rate_idx(hci);
0156     u8 *data = xfer->data;
0157     unsigned int data_len = xfer->data_len;
0158     bool rnw = xfer->rnw;
0159 
0160     if (raw && ccc_addr != I3C_BROADCAST_ADDR) {
0161         hci_cmd_v2_prep_private_xfer(hci, xfer, ccc_addr, mode, rate);
0162         return 0;
0163     }
0164 
0165     xfer->cmd_tid = hci_get_tid();
0166 
0167     if (!rnw && data_len <= 4) {
0168         xfer->cmd_desc[0] =
0169             CMD_0_ATTR_U |
0170             CMD_U0_TID(xfer->cmd_tid) |
0171             CMD_U0_DEV_ADDRESS(ccc_addr) |
0172             CMD_U0_XFER_RATE(rate) |
0173             CMD_U0_MODE_INDEX(mode) |
0174             CMD_U0_IDB_COUNT(data_len + (!raw ? 0 : 1));
0175         xfer->cmd_desc[1] =
0176             CMD_U1_DATA_LENGTH(0);
0177         xfer->cmd_desc[2] =
0178             CMD_U2_IDB0(ccc_cmd);
0179         xfer->cmd_desc[3] = 0;
0180         switch (data_len) {
0181         case 4:
0182             xfer->cmd_desc[3] |= CMD_U3_IDB4(data[3]);
0183             fallthrough;
0184         case 3:
0185             xfer->cmd_desc[2] |= CMD_U2_IDB3(data[2]);
0186             fallthrough;
0187         case 2:
0188             xfer->cmd_desc[2] |= CMD_U2_IDB2(data[1]);
0189             fallthrough;
0190         case 1:
0191             xfer->cmd_desc[2] |= CMD_U2_IDB1(data[0]);
0192             fallthrough;
0193         case 0:
0194             break;
0195         }
0196         /* we consumed all the data with the cmd descriptor */
0197         xfer->data = NULL;
0198     } else {
0199         xfer->cmd_desc[0] =
0200             CMD_0_ATTR_U |
0201             CMD_U0_TID(xfer->cmd_tid) |
0202             (rnw ? CMD_U0_RnW : 0) |
0203             CMD_U0_DEV_ADDRESS(ccc_addr) |
0204             CMD_U0_XFER_RATE(rate) |
0205             CMD_U0_MODE_INDEX(mode) |
0206             CMD_U0_IDB_COUNT(!raw ? 0 : 1);
0207         xfer->cmd_desc[1] =
0208             CMD_U1_DATA_LENGTH(data_len);
0209         xfer->cmd_desc[2] =
0210             CMD_U2_IDB0(ccc_cmd);
0211         xfer->cmd_desc[3] = 0;
0212     }
0213 
0214     return 0;
0215 }
0216 
0217 static void hci_cmd_v2_prep_i3c_xfer(struct i3c_hci *hci,
0218                      struct i3c_dev_desc *dev,
0219                      struct hci_xfer *xfer)
0220 {
0221     unsigned int mode = XFERMODE_IDX_I3C_SDR;
0222     unsigned int rate = get_i3c_rate_idx(hci);
0223     u8 addr = dev->info.dyn_addr;
0224 
0225     hci_cmd_v2_prep_private_xfer(hci, xfer, addr, mode, rate);
0226 }
0227 
0228 static void hci_cmd_v2_prep_i2c_xfer(struct i3c_hci *hci,
0229                      struct i2c_dev_desc *dev,
0230                      struct hci_xfer *xfer)
0231 {
0232     unsigned int mode = XFERMODE_IDX_I2C;
0233     unsigned int rate = get_i2c_rate_idx(hci);
0234     u8 addr = dev->addr;
0235 
0236     hci_cmd_v2_prep_private_xfer(hci, xfer, addr, mode, rate);
0237 }
0238 
0239 static int hci_cmd_v2_daa(struct i3c_hci *hci)
0240 {
0241     struct hci_xfer *xfer;
0242     int ret;
0243     u8 next_addr = 0;
0244     u32 device_id[2];
0245     u64 pid;
0246     unsigned int dcr, bcr;
0247     DECLARE_COMPLETION_ONSTACK(done);
0248 
0249     xfer = hci_alloc_xfer(2);
0250     if (!xfer)
0251         return -ENOMEM;
0252 
0253     xfer[0].data = &device_id;
0254     xfer[0].data_len = 8;
0255     xfer[0].rnw = true;
0256     xfer[0].cmd_desc[1] = CMD_A1_DATA_LENGTH(8);
0257     xfer[1].completion = &done;
0258 
0259     for (;;) {
0260         ret = i3c_master_get_free_addr(&hci->master, next_addr);
0261         if (ret < 0)
0262             break;
0263         next_addr = ret;
0264         DBG("next_addr = 0x%02x", next_addr);
0265         xfer[0].cmd_tid = hci_get_tid();
0266         xfer[0].cmd_desc[0] =
0267             CMD_0_ATTR_A |
0268             CMD_A0_TID(xfer[0].cmd_tid) |
0269             CMD_A0_ROC;
0270         xfer[1].cmd_tid = hci_get_tid();
0271         xfer[1].cmd_desc[0] =
0272             CMD_0_ATTR_A |
0273             CMD_A0_TID(xfer[1].cmd_tid) |
0274             CMD_A0_ASSIGN_ADDRESS(next_addr) |
0275             CMD_A0_ROC |
0276             CMD_A0_TOC;
0277         hci->io->queue_xfer(hci, xfer, 2);
0278         if (!wait_for_completion_timeout(&done, HZ) &&
0279             hci->io->dequeue_xfer(hci, xfer, 2)) {
0280             ret = -ETIME;
0281             break;
0282         }
0283         if (RESP_STATUS(xfer[0].response) != RESP_SUCCESS) {
0284             ret = 0;  /* no more devices to be assigned */
0285             break;
0286         }
0287         if (RESP_STATUS(xfer[1].response) != RESP_SUCCESS) {
0288             ret = -EIO;
0289             break;
0290         }
0291 
0292         pid = FIELD_GET(W1_MASK(47, 32), device_id[1]);
0293         pid = (pid << 32) | device_id[0];
0294         bcr = FIELD_GET(W1_MASK(55, 48), device_id[1]);
0295         dcr = FIELD_GET(W1_MASK(63, 56), device_id[1]);
0296         DBG("assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x",
0297             next_addr, pid, dcr, bcr);
0298         /*
0299          * TODO: Extend the subsystem layer to allow for registering
0300          * new device and provide BCR/DCR/PID at the same time.
0301          */
0302         ret = i3c_master_add_i3c_dev_locked(&hci->master, next_addr);
0303         if (ret)
0304             break;
0305     }
0306 
0307     hci_free_xfer(xfer, 2);
0308     return ret;
0309 }
0310 
0311 const struct hci_cmd_ops mipi_i3c_hci_cmd_v2 = {
0312     .prep_ccc       = hci_cmd_v2_prep_ccc,
0313     .prep_i3c_xfer      = hci_cmd_v2_prep_i3c_xfer,
0314     .prep_i2c_xfer      = hci_cmd_v2_prep_i2c_xfer,
0315     .perform_daa        = hci_cmd_v2_daa,
0316 };
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