0001
0002
0003
0004
0005
0006
0007
0008
0009
0010 #ifndef CMD_H
0011 #define CMD_H
0012
0013
0014
0015
0016
0017 #define CMD_0_TOC W0_BIT_(31)
0018 #define CMD_0_ROC W0_BIT_(30)
0019 #define CMD_0_ATTR W0_MASK(2, 0)
0020
0021
0022
0023
0024 #define RESP_STATUS(resp) FIELD_GET(GENMASK(31, 28), resp)
0025 #define RESP_TID(resp) FIELD_GET(GENMASK(27, 24), resp)
0026 #define RESP_DATA_LENGTH(resp) FIELD_GET(GENMASK(21, 0), resp)
0027
0028 #define RESP_ERR_FIELD GENMASK(31, 28)
0029
0030 enum hci_resp_err {
0031 RESP_SUCCESS = 0x0,
0032 RESP_ERR_CRC = 0x1,
0033 RESP_ERR_PARITY = 0x2,
0034 RESP_ERR_FRAME = 0x3,
0035 RESP_ERR_ADDR_HEADER = 0x4,
0036 RESP_ERR_BCAST_NACK_7E = 0x4,
0037 RESP_ERR_NACK = 0x5,
0038 RESP_ERR_OVL = 0x6,
0039 RESP_ERR_I3C_SHORT_READ = 0x7,
0040 RESP_ERR_HC_TERMINATED = 0x8,
0041 RESP_ERR_I2C_WR_DATA_NACK = 0x9,
0042 RESP_ERR_BUS_XFER_ABORTED = 0x9,
0043 RESP_ERR_NOT_SUPPORTED = 0xa,
0044 RESP_ERR_ABORTED_WITH_CRC = 0xb,
0045
0046 };
0047
0048
0049 #define hci_get_tid(bits) \
0050 (atomic_inc_return_relaxed(&hci->next_cmd_tid) % (1U << 4))
0051
0052
0053 struct hci_cmd_ops {
0054 int (*prep_ccc)(struct i3c_hci *hci, struct hci_xfer *xfer,
0055 u8 ccc_addr, u8 ccc_cmd, bool raw);
0056 void (*prep_i3c_xfer)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
0057 struct hci_xfer *xfer);
0058 void (*prep_i2c_xfer)(struct i3c_hci *hci, struct i2c_dev_desc *dev,
0059 struct hci_xfer *xfer);
0060 int (*perform_daa)(struct i3c_hci *hci);
0061 };
0062
0063
0064 extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v1;
0065 extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v2;
0066
0067 #endif