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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates.
0004  *
0005  * Author: Vitor Soares <vitor.soares@synopsys.com>
0006  */
0007 
0008 #include <linux/bitops.h>
0009 #include <linux/clk.h>
0010 #include <linux/completion.h>
0011 #include <linux/err.h>
0012 #include <linux/errno.h>
0013 #include <linux/i3c/master.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/ioport.h>
0016 #include <linux/iopoll.h>
0017 #include <linux/list.h>
0018 #include <linux/module.h>
0019 #include <linux/of.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/reset.h>
0022 #include <linux/slab.h>
0023 
0024 #define DEVICE_CTRL         0x0
0025 #define DEV_CTRL_ENABLE         BIT(31)
0026 #define DEV_CTRL_RESUME         BIT(30)
0027 #define DEV_CTRL_HOT_JOIN_NACK      BIT(8)
0028 #define DEV_CTRL_I2C_SLAVE_PRESENT  BIT(7)
0029 
0030 #define DEVICE_ADDR         0x4
0031 #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31)
0032 #define DEV_ADDR_DYNAMIC(x)     (((x) << 16) & GENMASK(22, 16))
0033 
0034 #define HW_CAPABILITY           0x8
0035 #define COMMAND_QUEUE_PORT      0xc
0036 #define COMMAND_PORT_TOC        BIT(30)
0037 #define COMMAND_PORT_READ_TRANSFER  BIT(28)
0038 #define COMMAND_PORT_SDAP       BIT(27)
0039 #define COMMAND_PORT_ROC        BIT(26)
0040 #define COMMAND_PORT_SPEED(x)       (((x) << 21) & GENMASK(23, 21))
0041 #define COMMAND_PORT_DEV_INDEX(x)   (((x) << 16) & GENMASK(20, 16))
0042 #define COMMAND_PORT_CP         BIT(15)
0043 #define COMMAND_PORT_CMD(x)     (((x) << 7) & GENMASK(14, 7))
0044 #define COMMAND_PORT_TID(x)     (((x) << 3) & GENMASK(6, 3))
0045 
0046 #define COMMAND_PORT_ARG_DATA_LEN(x)    (((x) << 16) & GENMASK(31, 16))
0047 #define COMMAND_PORT_ARG_DATA_LEN_MAX   65536
0048 #define COMMAND_PORT_TRANSFER_ARG   0x01
0049 
0050 #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24))
0051 #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16))
0052 #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8))
0053 #define COMMAND_PORT_SDA_BYTE_STRB_3    BIT(5)
0054 #define COMMAND_PORT_SDA_BYTE_STRB_2    BIT(4)
0055 #define COMMAND_PORT_SDA_BYTE_STRB_1    BIT(3)
0056 #define COMMAND_PORT_SHORT_DATA_ARG 0x02
0057 
0058 #define COMMAND_PORT_DEV_COUNT(x)   (((x) << 21) & GENMASK(25, 21))
0059 #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03
0060 
0061 #define RESPONSE_QUEUE_PORT     0x10
0062 #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28)
0063 #define RESPONSE_NO_ERROR       0
0064 #define RESPONSE_ERROR_CRC      1
0065 #define RESPONSE_ERROR_PARITY       2
0066 #define RESPONSE_ERROR_FRAME        3
0067 #define RESPONSE_ERROR_IBA_NACK     4
0068 #define RESPONSE_ERROR_ADDRESS_NACK 5
0069 #define RESPONSE_ERROR_OVER_UNDER_FLOW  6
0070 #define RESPONSE_ERROR_TRANSF_ABORT 8
0071 #define RESPONSE_ERROR_I2C_W_NACK_ERR   9
0072 #define RESPONSE_PORT_TID(x)        (((x) & GENMASK(27, 24)) >> 24)
0073 #define RESPONSE_PORT_DATA_LEN(x)   ((x) & GENMASK(15, 0))
0074 
0075 #define RX_TX_DATA_PORT         0x14
0076 #define IBI_QUEUE_STATUS        0x18
0077 #define QUEUE_THLD_CTRL         0x1c
0078 #define QUEUE_THLD_CTRL_RESP_BUF_MASK   GENMASK(15, 8)
0079 #define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8)
0080 
0081 #define DATA_BUFFER_THLD_CTRL       0x20
0082 #define DATA_BUFFER_THLD_CTRL_RX_BUF    GENMASK(11, 8)
0083 
0084 #define IBI_QUEUE_CTRL          0x24
0085 #define IBI_MR_REQ_REJECT       0x2C
0086 #define IBI_SIR_REQ_REJECT      0x30
0087 #define IBI_REQ_REJECT_ALL      GENMASK(31, 0)
0088 
0089 #define RESET_CTRL          0x34
0090 #define RESET_CTRL_IBI_QUEUE        BIT(5)
0091 #define RESET_CTRL_RX_FIFO      BIT(4)
0092 #define RESET_CTRL_TX_FIFO      BIT(3)
0093 #define RESET_CTRL_RESP_QUEUE       BIT(2)
0094 #define RESET_CTRL_CMD_QUEUE        BIT(1)
0095 #define RESET_CTRL_SOFT         BIT(0)
0096 
0097 #define SLV_EVENT_CTRL          0x38
0098 #define INTR_STATUS         0x3c
0099 #define INTR_STATUS_EN          0x40
0100 #define INTR_SIGNAL_EN          0x44
0101 #define INTR_FORCE          0x48
0102 #define INTR_BUSOWNER_UPDATE_STAT   BIT(13)
0103 #define INTR_IBI_UPDATED_STAT       BIT(12)
0104 #define INTR_READ_REQ_RECV_STAT     BIT(11)
0105 #define INTR_DEFSLV_STAT        BIT(10)
0106 #define INTR_TRANSFER_ERR_STAT      BIT(9)
0107 #define INTR_DYN_ADDR_ASSGN_STAT    BIT(8)
0108 #define INTR_CCC_UPDATED_STAT       BIT(6)
0109 #define INTR_TRANSFER_ABORT_STAT    BIT(5)
0110 #define INTR_RESP_READY_STAT        BIT(4)
0111 #define INTR_CMD_QUEUE_READY_STAT   BIT(3)
0112 #define INTR_IBI_THLD_STAT      BIT(2)
0113 #define INTR_RX_THLD_STAT       BIT(1)
0114 #define INTR_TX_THLD_STAT       BIT(0)
0115 #define INTR_ALL            (INTR_BUSOWNER_UPDATE_STAT |    \
0116                     INTR_IBI_UPDATED_STAT |     \
0117                     INTR_READ_REQ_RECV_STAT |   \
0118                     INTR_DEFSLV_STAT |      \
0119                     INTR_TRANSFER_ERR_STAT |    \
0120                     INTR_DYN_ADDR_ASSGN_STAT |  \
0121                     INTR_CCC_UPDATED_STAT |     \
0122                     INTR_TRANSFER_ABORT_STAT |  \
0123                     INTR_RESP_READY_STAT |      \
0124                     INTR_CMD_QUEUE_READY_STAT | \
0125                     INTR_IBI_THLD_STAT |        \
0126                     INTR_TX_THLD_STAT |     \
0127                     INTR_RX_THLD_STAT)
0128 
0129 #define INTR_MASTER_MASK        (INTR_TRANSFER_ERR_STAT |   \
0130                      INTR_RESP_READY_STAT)
0131 
0132 #define QUEUE_STATUS_LEVEL      0x4c
0133 #define QUEUE_STATUS_IBI_STATUS_CNT(x)  (((x) & GENMASK(28, 24)) >> 24)
0134 #define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16)
0135 #define QUEUE_STATUS_LEVEL_RESP(x)  (((x) & GENMASK(15, 8)) >> 8)
0136 #define QUEUE_STATUS_LEVEL_CMD(x)   ((x) & GENMASK(7, 0))
0137 
0138 #define DATA_BUFFER_STATUS_LEVEL    0x50
0139 #define DATA_BUFFER_STATUS_LEVEL_TX(x)  ((x) & GENMASK(7, 0))
0140 
0141 #define PRESENT_STATE           0x54
0142 #define CCC_DEVICE_STATUS       0x58
0143 #define DEVICE_ADDR_TABLE_POINTER   0x5c
0144 #define DEVICE_ADDR_TABLE_DEPTH(x)  (((x) & GENMASK(31, 16)) >> 16)
0145 #define DEVICE_ADDR_TABLE_ADDR(x)   ((x) & GENMASK(7, 0))
0146 
0147 #define DEV_CHAR_TABLE_POINTER      0x60
0148 #define VENDOR_SPECIFIC_REG_POINTER 0x6c
0149 #define SLV_PID_VALUE           0x74
0150 #define SLV_CHAR_CTRL           0x78
0151 #define SLV_MAX_LEN         0x7c
0152 #define MAX_READ_TURNAROUND     0x80
0153 #define MAX_DATA_SPEED          0x84
0154 #define SLV_DEBUG_STATUS        0x88
0155 #define SLV_INTR_REQ            0x8c
0156 #define DEVICE_CTRL_EXTENDED        0xb0
0157 #define SCL_I3C_OD_TIMING       0xb4
0158 #define SCL_I3C_PP_TIMING       0xb8
0159 #define SCL_I3C_TIMING_HCNT(x)      (((x) << 16) & GENMASK(23, 16))
0160 #define SCL_I3C_TIMING_LCNT(x)      ((x) & GENMASK(7, 0))
0161 #define SCL_I3C_TIMING_CNT_MIN      5
0162 
0163 #define SCL_I2C_FM_TIMING       0xbc
0164 #define SCL_I2C_FM_TIMING_HCNT(x)   (((x) << 16) & GENMASK(31, 16))
0165 #define SCL_I2C_FM_TIMING_LCNT(x)   ((x) & GENMASK(15, 0))
0166 
0167 #define SCL_I2C_FMP_TIMING      0xc0
0168 #define SCL_I2C_FMP_TIMING_HCNT(x)  (((x) << 16) & GENMASK(23, 16))
0169 #define SCL_I2C_FMP_TIMING_LCNT(x)  ((x) & GENMASK(15, 0))
0170 
0171 #define SCL_EXT_LCNT_TIMING     0xc8
0172 #define SCL_EXT_LCNT_4(x)       (((x) << 24) & GENMASK(31, 24))
0173 #define SCL_EXT_LCNT_3(x)       (((x) << 16) & GENMASK(23, 16))
0174 #define SCL_EXT_LCNT_2(x)       (((x) << 8) & GENMASK(15, 8))
0175 #define SCL_EXT_LCNT_1(x)       ((x) & GENMASK(7, 0))
0176 
0177 #define SCL_EXT_TERMN_LCNT_TIMING   0xcc
0178 #define BUS_FREE_TIMING         0xd4
0179 #define BUS_I3C_MST_FREE(x)     ((x) & GENMASK(15, 0))
0180 
0181 #define BUS_IDLE_TIMING         0xd8
0182 #define I3C_VER_ID          0xe0
0183 #define I3C_VER_TYPE            0xe4
0184 #define EXTENDED_CAPABILITY     0xe8
0185 #define SLAVE_CONFIG            0xec
0186 
0187 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV   BIT(31)
0188 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x)  (((x) << 16) & GENMASK(23, 16))
0189 #define DEV_ADDR_TABLE_STATIC_ADDR(x)   ((x) & GENMASK(6, 0))
0190 #define DEV_ADDR_TABLE_LOC(start, idx)  ((start) + ((idx) << 2))
0191 
0192 #define MAX_DEVS 32
0193 
0194 #define I3C_BUS_SDR1_SCL_RATE       8000000
0195 #define I3C_BUS_SDR2_SCL_RATE       6000000
0196 #define I3C_BUS_SDR3_SCL_RATE       4000000
0197 #define I3C_BUS_SDR4_SCL_RATE       2000000
0198 #define I3C_BUS_I2C_FM_TLOW_MIN_NS  1300
0199 #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500
0200 #define I3C_BUS_THIGH_MAX_NS        41
0201 
0202 #define XFER_TIMEOUT (msecs_to_jiffies(1000))
0203 
0204 struct dw_i3c_master_caps {
0205     u8 cmdfifodepth;
0206     u8 datafifodepth;
0207 };
0208 
0209 struct dw_i3c_cmd {
0210     u32 cmd_lo;
0211     u32 cmd_hi;
0212     u16 tx_len;
0213     const void *tx_buf;
0214     u16 rx_len;
0215     void *rx_buf;
0216     u8 error;
0217 };
0218 
0219 struct dw_i3c_xfer {
0220     struct list_head node;
0221     struct completion comp;
0222     int ret;
0223     unsigned int ncmds;
0224     struct dw_i3c_cmd cmds[];
0225 };
0226 
0227 struct dw_i3c_master {
0228     struct i3c_master_controller base;
0229     u16 maxdevs;
0230     u16 datstartaddr;
0231     u32 free_pos;
0232     struct {
0233         struct list_head list;
0234         struct dw_i3c_xfer *cur;
0235         spinlock_t lock;
0236     } xferqueue;
0237     struct dw_i3c_master_caps caps;
0238     void __iomem *regs;
0239     struct reset_control *core_rst;
0240     struct clk *core_clk;
0241     char version[5];
0242     char type[5];
0243     u8 addrs[MAX_DEVS];
0244 };
0245 
0246 struct dw_i3c_i2c_dev_data {
0247     u8 index;
0248 };
0249 
0250 static u8 even_parity(u8 p)
0251 {
0252     p ^= p >> 4;
0253     p &= 0xf;
0254 
0255     return (0x9669 >> p) & 1;
0256 }
0257 
0258 static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m,
0259                        const struct i3c_ccc_cmd *cmd)
0260 {
0261     if (cmd->ndests > 1)
0262         return false;
0263 
0264     switch (cmd->id) {
0265     case I3C_CCC_ENEC(true):
0266     case I3C_CCC_ENEC(false):
0267     case I3C_CCC_DISEC(true):
0268     case I3C_CCC_DISEC(false):
0269     case I3C_CCC_ENTAS(0, true):
0270     case I3C_CCC_ENTAS(0, false):
0271     case I3C_CCC_RSTDAA(true):
0272     case I3C_CCC_RSTDAA(false):
0273     case I3C_CCC_ENTDAA:
0274     case I3C_CCC_SETMWL(true):
0275     case I3C_CCC_SETMWL(false):
0276     case I3C_CCC_SETMRL(true):
0277     case I3C_CCC_SETMRL(false):
0278     case I3C_CCC_ENTHDR(0):
0279     case I3C_CCC_SETDASA:
0280     case I3C_CCC_SETNEWDA:
0281     case I3C_CCC_GETMWL:
0282     case I3C_CCC_GETMRL:
0283     case I3C_CCC_GETPID:
0284     case I3C_CCC_GETBCR:
0285     case I3C_CCC_GETDCR:
0286     case I3C_CCC_GETSTATUS:
0287     case I3C_CCC_GETMXDS:
0288     case I3C_CCC_GETHDRCAP:
0289         return true;
0290     default:
0291         return false;
0292     }
0293 }
0294 
0295 static inline struct dw_i3c_master *
0296 to_dw_i3c_master(struct i3c_master_controller *master)
0297 {
0298     return container_of(master, struct dw_i3c_master, base);
0299 }
0300 
0301 static void dw_i3c_master_disable(struct dw_i3c_master *master)
0302 {
0303     writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE,
0304            master->regs + DEVICE_CTRL);
0305 }
0306 
0307 static void dw_i3c_master_enable(struct dw_i3c_master *master)
0308 {
0309     writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE,
0310            master->regs + DEVICE_CTRL);
0311 }
0312 
0313 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr)
0314 {
0315     int pos;
0316 
0317     for (pos = 0; pos < master->maxdevs; pos++) {
0318         if (addr == master->addrs[pos])
0319             return pos;
0320     }
0321 
0322     return -EINVAL;
0323 }
0324 
0325 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master)
0326 {
0327     if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0)))
0328         return -ENOSPC;
0329 
0330     return ffs(master->free_pos) - 1;
0331 }
0332 
0333 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master,
0334                      const u8 *bytes, int nbytes)
0335 {
0336     writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
0337     if (nbytes & 3) {
0338         u32 tmp = 0;
0339 
0340         memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
0341         writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
0342     }
0343 }
0344 
0345 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
0346                        u8 *bytes, int nbytes)
0347 {
0348     readsl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
0349     if (nbytes & 3) {
0350         u32 tmp;
0351 
0352         readsl(master->regs + RX_TX_DATA_PORT, &tmp, 1);
0353         memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3);
0354     }
0355 }
0356 
0357 static struct dw_i3c_xfer *
0358 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds)
0359 {
0360     struct dw_i3c_xfer *xfer;
0361 
0362     xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
0363     if (!xfer)
0364         return NULL;
0365 
0366     INIT_LIST_HEAD(&xfer->node);
0367     xfer->ncmds = ncmds;
0368     xfer->ret = -ETIMEDOUT;
0369 
0370     return xfer;
0371 }
0372 
0373 static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer)
0374 {
0375     kfree(xfer);
0376 }
0377 
0378 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master)
0379 {
0380     struct dw_i3c_xfer *xfer = master->xferqueue.cur;
0381     unsigned int i;
0382     u32 thld_ctrl;
0383 
0384     if (!xfer)
0385         return;
0386 
0387     for (i = 0; i < xfer->ncmds; i++) {
0388         struct dw_i3c_cmd *cmd = &xfer->cmds[i];
0389 
0390         dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len);
0391     }
0392 
0393     thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
0394     thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
0395     thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds);
0396     writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
0397 
0398     for (i = 0; i < xfer->ncmds; i++) {
0399         struct dw_i3c_cmd *cmd = &xfer->cmds[i];
0400 
0401         writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT);
0402         writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT);
0403     }
0404 }
0405 
0406 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master,
0407                        struct dw_i3c_xfer *xfer)
0408 {
0409     unsigned long flags;
0410 
0411     init_completion(&xfer->comp);
0412     spin_lock_irqsave(&master->xferqueue.lock, flags);
0413     if (master->xferqueue.cur) {
0414         list_add_tail(&xfer->node, &master->xferqueue.list);
0415     } else {
0416         master->xferqueue.cur = xfer;
0417         dw_i3c_master_start_xfer_locked(master);
0418     }
0419     spin_unlock_irqrestore(&master->xferqueue.lock, flags);
0420 }
0421 
0422 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master,
0423                           struct dw_i3c_xfer *xfer)
0424 {
0425     if (master->xferqueue.cur == xfer) {
0426         u32 status;
0427 
0428         master->xferqueue.cur = NULL;
0429 
0430         writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO |
0431                RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE,
0432                master->regs + RESET_CTRL);
0433 
0434         readl_poll_timeout_atomic(master->regs + RESET_CTRL, status,
0435                       !status, 10, 1000000);
0436     } else {
0437         list_del_init(&xfer->node);
0438     }
0439 }
0440 
0441 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master,
0442                        struct dw_i3c_xfer *xfer)
0443 {
0444     unsigned long flags;
0445 
0446     spin_lock_irqsave(&master->xferqueue.lock, flags);
0447     dw_i3c_master_dequeue_xfer_locked(master, xfer);
0448     spin_unlock_irqrestore(&master->xferqueue.lock, flags);
0449 }
0450 
0451 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr)
0452 {
0453     struct dw_i3c_xfer *xfer = master->xferqueue.cur;
0454     int i, ret = 0;
0455     u32 nresp;
0456 
0457     if (!xfer)
0458         return;
0459 
0460     nresp = readl(master->regs + QUEUE_STATUS_LEVEL);
0461     nresp = QUEUE_STATUS_LEVEL_RESP(nresp);
0462 
0463     for (i = 0; i < nresp; i++) {
0464         struct dw_i3c_cmd *cmd;
0465         u32 resp;
0466 
0467         resp = readl(master->regs + RESPONSE_QUEUE_PORT);
0468 
0469         cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)];
0470         cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp);
0471         cmd->error = RESPONSE_PORT_ERR_STATUS(resp);
0472         if (cmd->rx_len && !cmd->error)
0473             dw_i3c_master_read_rx_fifo(master, cmd->rx_buf,
0474                            cmd->rx_len);
0475     }
0476 
0477     for (i = 0; i < nresp; i++) {
0478         switch (xfer->cmds[i].error) {
0479         case RESPONSE_NO_ERROR:
0480             break;
0481         case RESPONSE_ERROR_PARITY:
0482         case RESPONSE_ERROR_IBA_NACK:
0483         case RESPONSE_ERROR_TRANSF_ABORT:
0484         case RESPONSE_ERROR_CRC:
0485         case RESPONSE_ERROR_FRAME:
0486             ret = -EIO;
0487             break;
0488         case RESPONSE_ERROR_OVER_UNDER_FLOW:
0489             ret = -ENOSPC;
0490             break;
0491         case RESPONSE_ERROR_I2C_W_NACK_ERR:
0492         case RESPONSE_ERROR_ADDRESS_NACK:
0493         default:
0494             ret = -EINVAL;
0495             break;
0496         }
0497     }
0498 
0499     xfer->ret = ret;
0500     complete(&xfer->comp);
0501 
0502     if (ret < 0) {
0503         dw_i3c_master_dequeue_xfer_locked(master, xfer);
0504         writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
0505                master->regs + DEVICE_CTRL);
0506     }
0507 
0508     xfer = list_first_entry_or_null(&master->xferqueue.list,
0509                     struct dw_i3c_xfer,
0510                     node);
0511     if (xfer)
0512         list_del_init(&xfer->node);
0513 
0514     master->xferqueue.cur = xfer;
0515     dw_i3c_master_start_xfer_locked(master);
0516 }
0517 
0518 static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
0519 {
0520     unsigned long core_rate, core_period;
0521     u32 scl_timing;
0522     u8 hcnt, lcnt;
0523 
0524     core_rate = clk_get_rate(master->core_clk);
0525     if (!core_rate)
0526         return -EINVAL;
0527 
0528     core_period = DIV_ROUND_UP(1000000000, core_rate);
0529 
0530     hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1;
0531     if (hcnt < SCL_I3C_TIMING_CNT_MIN)
0532         hcnt = SCL_I3C_TIMING_CNT_MIN;
0533 
0534     lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_TYP_I3C_SCL_RATE) - hcnt;
0535     if (lcnt < SCL_I3C_TIMING_CNT_MIN)
0536         lcnt = SCL_I3C_TIMING_CNT_MIN;
0537 
0538     scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
0539     writel(scl_timing, master->regs + SCL_I3C_PP_TIMING);
0540 
0541     if (!(readl(master->regs + DEVICE_CTRL) & DEV_CTRL_I2C_SLAVE_PRESENT))
0542         writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
0543 
0544     lcnt = DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period);
0545     scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
0546     writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
0547 
0548     lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt;
0549     scl_timing = SCL_EXT_LCNT_1(lcnt);
0550     lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt;
0551     scl_timing |= SCL_EXT_LCNT_2(lcnt);
0552     lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt;
0553     scl_timing |= SCL_EXT_LCNT_3(lcnt);
0554     lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt;
0555     scl_timing |= SCL_EXT_LCNT_4(lcnt);
0556     writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING);
0557 
0558     return 0;
0559 }
0560 
0561 static int dw_i2c_clk_cfg(struct dw_i3c_master *master)
0562 {
0563     unsigned long core_rate, core_period;
0564     u16 hcnt, lcnt;
0565     u32 scl_timing;
0566 
0567     core_rate = clk_get_rate(master->core_clk);
0568     if (!core_rate)
0569         return -EINVAL;
0570 
0571     core_period = DIV_ROUND_UP(1000000000, core_rate);
0572 
0573     lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period);
0574     hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_RATE) - lcnt;
0575     scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) |
0576              SCL_I2C_FMP_TIMING_LCNT(lcnt);
0577     writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING);
0578 
0579     lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period);
0580     hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt;
0581     scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) |
0582              SCL_I2C_FM_TIMING_LCNT(lcnt);
0583     writel(scl_timing, master->regs + SCL_I2C_FM_TIMING);
0584 
0585     writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING);
0586     writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
0587            master->regs + DEVICE_CTRL);
0588 
0589     return 0;
0590 }
0591 
0592 static int dw_i3c_master_bus_init(struct i3c_master_controller *m)
0593 {
0594     struct dw_i3c_master *master = to_dw_i3c_master(m);
0595     struct i3c_bus *bus = i3c_master_get_bus(m);
0596     struct i3c_device_info info = { };
0597     u32 thld_ctrl;
0598     int ret;
0599 
0600     switch (bus->mode) {
0601     case I3C_BUS_MODE_MIXED_FAST:
0602     case I3C_BUS_MODE_MIXED_LIMITED:
0603         ret = dw_i2c_clk_cfg(master);
0604         if (ret)
0605             return ret;
0606         fallthrough;
0607     case I3C_BUS_MODE_PURE:
0608         ret = dw_i3c_clk_cfg(master);
0609         if (ret)
0610             return ret;
0611         break;
0612     default:
0613         return -EINVAL;
0614     }
0615 
0616     thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL);
0617     thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
0618     writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL);
0619 
0620     thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL);
0621     thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF;
0622     writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL);
0623 
0624     writel(INTR_ALL, master->regs + INTR_STATUS);
0625     writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN);
0626     writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN);
0627 
0628     ret = i3c_master_get_free_addr(m, 0);
0629     if (ret < 0)
0630         return ret;
0631 
0632     writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret),
0633            master->regs + DEVICE_ADDR);
0634 
0635     memset(&info, 0, sizeof(info));
0636     info.dyn_addr = ret;
0637 
0638     ret = i3c_master_set_info(&master->base, &info);
0639     if (ret)
0640         return ret;
0641 
0642     writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT);
0643     writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT);
0644 
0645     /* For now don't support Hot-Join */
0646     writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK,
0647            master->regs + DEVICE_CTRL);
0648 
0649     dw_i3c_master_enable(master);
0650 
0651     return 0;
0652 }
0653 
0654 static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m)
0655 {
0656     struct dw_i3c_master *master = to_dw_i3c_master(m);
0657 
0658     dw_i3c_master_disable(master);
0659 }
0660 
0661 static int dw_i3c_ccc_set(struct dw_i3c_master *master,
0662               struct i3c_ccc_cmd *ccc)
0663 {
0664     struct dw_i3c_xfer *xfer;
0665     struct dw_i3c_cmd *cmd;
0666     int ret, pos = 0;
0667 
0668     if (ccc->id & I3C_CCC_DIRECT) {
0669         pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
0670         if (pos < 0)
0671             return pos;
0672     }
0673 
0674     xfer = dw_i3c_master_alloc_xfer(master, 1);
0675     if (!xfer)
0676         return -ENOMEM;
0677 
0678     cmd = xfer->cmds;
0679     cmd->tx_buf = ccc->dests[0].payload.data;
0680     cmd->tx_len = ccc->dests[0].payload.len;
0681 
0682     cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
0683               COMMAND_PORT_TRANSFER_ARG;
0684 
0685     cmd->cmd_lo = COMMAND_PORT_CP |
0686               COMMAND_PORT_DEV_INDEX(pos) |
0687               COMMAND_PORT_CMD(ccc->id) |
0688               COMMAND_PORT_TOC |
0689               COMMAND_PORT_ROC;
0690 
0691     dw_i3c_master_enqueue_xfer(master, xfer);
0692     if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
0693         dw_i3c_master_dequeue_xfer(master, xfer);
0694 
0695     ret = xfer->ret;
0696     if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
0697         ccc->err = I3C_ERROR_M2;
0698 
0699     dw_i3c_master_free_xfer(xfer);
0700 
0701     return ret;
0702 }
0703 
0704 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc)
0705 {
0706     struct dw_i3c_xfer *xfer;
0707     struct dw_i3c_cmd *cmd;
0708     int ret, pos;
0709 
0710     pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr);
0711     if (pos < 0)
0712         return pos;
0713 
0714     xfer = dw_i3c_master_alloc_xfer(master, 1);
0715     if (!xfer)
0716         return -ENOMEM;
0717 
0718     cmd = xfer->cmds;
0719     cmd->rx_buf = ccc->dests[0].payload.data;
0720     cmd->rx_len = ccc->dests[0].payload.len;
0721 
0722     cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) |
0723               COMMAND_PORT_TRANSFER_ARG;
0724 
0725     cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
0726               COMMAND_PORT_CP |
0727               COMMAND_PORT_DEV_INDEX(pos) |
0728               COMMAND_PORT_CMD(ccc->id) |
0729               COMMAND_PORT_TOC |
0730               COMMAND_PORT_ROC;
0731 
0732     dw_i3c_master_enqueue_xfer(master, xfer);
0733     if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
0734         dw_i3c_master_dequeue_xfer(master, xfer);
0735 
0736     ret = xfer->ret;
0737     if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK)
0738         ccc->err = I3C_ERROR_M2;
0739     dw_i3c_master_free_xfer(xfer);
0740 
0741     return ret;
0742 }
0743 
0744 static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m,
0745                       struct i3c_ccc_cmd *ccc)
0746 {
0747     struct dw_i3c_master *master = to_dw_i3c_master(m);
0748     int ret = 0;
0749 
0750     if (ccc->id == I3C_CCC_ENTDAA)
0751         return -EINVAL;
0752 
0753     if (ccc->rnw)
0754         ret = dw_i3c_ccc_get(master, ccc);
0755     else
0756         ret = dw_i3c_ccc_set(master, ccc);
0757 
0758     return ret;
0759 }
0760 
0761 static int dw_i3c_master_daa(struct i3c_master_controller *m)
0762 {
0763     struct dw_i3c_master *master = to_dw_i3c_master(m);
0764     struct dw_i3c_xfer *xfer;
0765     struct dw_i3c_cmd *cmd;
0766     u32 olddevs, newdevs;
0767     u8 p, last_addr = 0;
0768     int ret, pos;
0769 
0770     olddevs = ~(master->free_pos);
0771 
0772     /* Prepare DAT before launching DAA. */
0773     for (pos = 0; pos < master->maxdevs; pos++) {
0774         if (olddevs & BIT(pos))
0775             continue;
0776 
0777         ret = i3c_master_get_free_addr(m, last_addr + 1);
0778         if (ret < 0)
0779             return -ENOSPC;
0780 
0781         master->addrs[pos] = ret;
0782         p = even_parity(ret);
0783         last_addr = ret;
0784         ret |= (p << 7);
0785 
0786         writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret),
0787                master->regs +
0788                DEV_ADDR_TABLE_LOC(master->datstartaddr, pos));
0789     }
0790 
0791     xfer = dw_i3c_master_alloc_xfer(master, 1);
0792     if (!xfer)
0793         return -ENOMEM;
0794 
0795     pos = dw_i3c_master_get_free_pos(master);
0796     if (pos < 0) {
0797         dw_i3c_master_free_xfer(xfer);
0798         return pos;
0799     }
0800     cmd = &xfer->cmds[0];
0801     cmd->cmd_hi = 0x1;
0802     cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) |
0803               COMMAND_PORT_DEV_INDEX(pos) |
0804               COMMAND_PORT_CMD(I3C_CCC_ENTDAA) |
0805               COMMAND_PORT_ADDR_ASSGN_CMD |
0806               COMMAND_PORT_TOC |
0807               COMMAND_PORT_ROC;
0808 
0809     dw_i3c_master_enqueue_xfer(master, xfer);
0810     if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
0811         dw_i3c_master_dequeue_xfer(master, xfer);
0812 
0813     newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0);
0814     newdevs &= ~olddevs;
0815 
0816     for (pos = 0; pos < master->maxdevs; pos++) {
0817         if (newdevs & BIT(pos))
0818             i3c_master_add_i3c_dev_locked(m, master->addrs[pos]);
0819     }
0820 
0821     dw_i3c_master_free_xfer(xfer);
0822 
0823     return 0;
0824 }
0825 
0826 static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev,
0827                     struct i3c_priv_xfer *i3c_xfers,
0828                     int i3c_nxfers)
0829 {
0830     struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
0831     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0832     struct dw_i3c_master *master = to_dw_i3c_master(m);
0833     unsigned int nrxwords = 0, ntxwords = 0;
0834     struct dw_i3c_xfer *xfer;
0835     int i, ret = 0;
0836 
0837     if (!i3c_nxfers)
0838         return 0;
0839 
0840     if (i3c_nxfers > master->caps.cmdfifodepth)
0841         return -ENOTSUPP;
0842 
0843     for (i = 0; i < i3c_nxfers; i++) {
0844         if (i3c_xfers[i].rnw)
0845             nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
0846         else
0847             ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4);
0848     }
0849 
0850     if (ntxwords > master->caps.datafifodepth ||
0851         nrxwords > master->caps.datafifodepth)
0852         return -ENOTSUPP;
0853 
0854     xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers);
0855     if (!xfer)
0856         return -ENOMEM;
0857 
0858     for (i = 0; i < i3c_nxfers; i++) {
0859         struct dw_i3c_cmd *cmd = &xfer->cmds[i];
0860 
0861         cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) |
0862             COMMAND_PORT_TRANSFER_ARG;
0863 
0864         if (i3c_xfers[i].rnw) {
0865             cmd->rx_buf = i3c_xfers[i].data.in;
0866             cmd->rx_len = i3c_xfers[i].len;
0867             cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER |
0868                       COMMAND_PORT_SPEED(dev->info.max_read_ds);
0869 
0870         } else {
0871             cmd->tx_buf = i3c_xfers[i].data.out;
0872             cmd->tx_len = i3c_xfers[i].len;
0873             cmd->cmd_lo =
0874                 COMMAND_PORT_SPEED(dev->info.max_write_ds);
0875         }
0876 
0877         cmd->cmd_lo |= COMMAND_PORT_TID(i) |
0878                    COMMAND_PORT_DEV_INDEX(data->index) |
0879                    COMMAND_PORT_ROC;
0880 
0881         if (i == (i3c_nxfers - 1))
0882             cmd->cmd_lo |= COMMAND_PORT_TOC;
0883     }
0884 
0885     dw_i3c_master_enqueue_xfer(master, xfer);
0886     if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
0887         dw_i3c_master_dequeue_xfer(master, xfer);
0888 
0889     ret = xfer->ret;
0890     dw_i3c_master_free_xfer(xfer);
0891 
0892     return ret;
0893 }
0894 
0895 static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev,
0896                       u8 old_dyn_addr)
0897 {
0898     struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
0899     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0900     struct dw_i3c_master *master = to_dw_i3c_master(m);
0901     int pos;
0902 
0903     pos = dw_i3c_master_get_free_pos(master);
0904 
0905     if (data->index > pos && pos > 0) {
0906         writel(0,
0907                master->regs +
0908                DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
0909 
0910         master->addrs[data->index] = 0;
0911         master->free_pos |= BIT(data->index);
0912 
0913         data->index = pos;
0914         master->addrs[pos] = dev->info.dyn_addr;
0915         master->free_pos &= ~BIT(pos);
0916     }
0917 
0918     writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr),
0919            master->regs +
0920            DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
0921 
0922     master->addrs[data->index] = dev->info.dyn_addr;
0923 
0924     return 0;
0925 }
0926 
0927 static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev)
0928 {
0929     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0930     struct dw_i3c_master *master = to_dw_i3c_master(m);
0931     struct dw_i3c_i2c_dev_data *data;
0932     int pos;
0933 
0934     pos = dw_i3c_master_get_free_pos(master);
0935     if (pos < 0)
0936         return pos;
0937 
0938     data = kzalloc(sizeof(*data), GFP_KERNEL);
0939     if (!data)
0940         return -ENOMEM;
0941 
0942     data->index = pos;
0943     master->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr;
0944     master->free_pos &= ~BIT(pos);
0945     i3c_dev_set_master_data(dev, data);
0946 
0947     writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->addrs[pos]),
0948            master->regs +
0949            DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
0950 
0951     return 0;
0952 }
0953 
0954 static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev)
0955 {
0956     struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
0957     struct i3c_master_controller *m = i3c_dev_get_master(dev);
0958     struct dw_i3c_master *master = to_dw_i3c_master(m);
0959 
0960     writel(0,
0961            master->regs +
0962            DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
0963 
0964     i3c_dev_set_master_data(dev, NULL);
0965     master->addrs[data->index] = 0;
0966     master->free_pos |= BIT(data->index);
0967     kfree(data);
0968 }
0969 
0970 static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev,
0971                    const struct i2c_msg *i2c_xfers,
0972                    int i2c_nxfers)
0973 {
0974     struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
0975     struct i3c_master_controller *m = i2c_dev_get_master(dev);
0976     struct dw_i3c_master *master = to_dw_i3c_master(m);
0977     unsigned int nrxwords = 0, ntxwords = 0;
0978     struct dw_i3c_xfer *xfer;
0979     int i, ret = 0;
0980 
0981     if (!i2c_nxfers)
0982         return 0;
0983 
0984     if (i2c_nxfers > master->caps.cmdfifodepth)
0985         return -ENOTSUPP;
0986 
0987     for (i = 0; i < i2c_nxfers; i++) {
0988         if (i2c_xfers[i].flags & I2C_M_RD)
0989             nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
0990         else
0991             ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4);
0992     }
0993 
0994     if (ntxwords > master->caps.datafifodepth ||
0995         nrxwords > master->caps.datafifodepth)
0996         return -ENOTSUPP;
0997 
0998     xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers);
0999     if (!xfer)
1000         return -ENOMEM;
1001 
1002     for (i = 0; i < i2c_nxfers; i++) {
1003         struct dw_i3c_cmd *cmd = &xfer->cmds[i];
1004 
1005         cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) |
1006             COMMAND_PORT_TRANSFER_ARG;
1007 
1008         cmd->cmd_lo = COMMAND_PORT_TID(i) |
1009                   COMMAND_PORT_DEV_INDEX(data->index) |
1010                   COMMAND_PORT_ROC;
1011 
1012         if (i2c_xfers[i].flags & I2C_M_RD) {
1013             cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER;
1014             cmd->rx_buf = i2c_xfers[i].buf;
1015             cmd->rx_len = i2c_xfers[i].len;
1016         } else {
1017             cmd->tx_buf = i2c_xfers[i].buf;
1018             cmd->tx_len = i2c_xfers[i].len;
1019         }
1020 
1021         if (i == (i2c_nxfers - 1))
1022             cmd->cmd_lo |= COMMAND_PORT_TOC;
1023     }
1024 
1025     dw_i3c_master_enqueue_xfer(master, xfer);
1026     if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT))
1027         dw_i3c_master_dequeue_xfer(master, xfer);
1028 
1029     ret = xfer->ret;
1030     dw_i3c_master_free_xfer(xfer);
1031 
1032     return ret;
1033 }
1034 
1035 static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev)
1036 {
1037     struct i3c_master_controller *m = i2c_dev_get_master(dev);
1038     struct dw_i3c_master *master = to_dw_i3c_master(m);
1039     struct dw_i3c_i2c_dev_data *data;
1040     int pos;
1041 
1042     pos = dw_i3c_master_get_free_pos(master);
1043     if (pos < 0)
1044         return pos;
1045 
1046     data = kzalloc(sizeof(*data), GFP_KERNEL);
1047     if (!data)
1048         return -ENOMEM;
1049 
1050     data->index = pos;
1051     master->addrs[pos] = dev->addr;
1052     master->free_pos &= ~BIT(pos);
1053     i2c_dev_set_master_data(dev, data);
1054 
1055     writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV |
1056            DEV_ADDR_TABLE_STATIC_ADDR(dev->addr),
1057            master->regs +
1058            DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1059 
1060     return 0;
1061 }
1062 
1063 static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev)
1064 {
1065     struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
1066     struct i3c_master_controller *m = i2c_dev_get_master(dev);
1067     struct dw_i3c_master *master = to_dw_i3c_master(m);
1068 
1069     writel(0,
1070            master->regs +
1071            DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index));
1072 
1073     i2c_dev_set_master_data(dev, NULL);
1074     master->addrs[data->index] = 0;
1075     master->free_pos |= BIT(data->index);
1076     kfree(data);
1077 }
1078 
1079 static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id)
1080 {
1081     struct dw_i3c_master *master = dev_id;
1082     u32 status;
1083 
1084     status = readl(master->regs + INTR_STATUS);
1085 
1086     if (!(status & readl(master->regs + INTR_STATUS_EN))) {
1087         writel(INTR_ALL, master->regs + INTR_STATUS);
1088         return IRQ_NONE;
1089     }
1090 
1091     spin_lock(&master->xferqueue.lock);
1092     dw_i3c_master_end_xfer_locked(master, status);
1093     if (status & INTR_TRANSFER_ERR_STAT)
1094         writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
1095     spin_unlock(&master->xferqueue.lock);
1096 
1097     return IRQ_HANDLED;
1098 }
1099 
1100 static const struct i3c_master_controller_ops dw_mipi_i3c_ops = {
1101     .bus_init = dw_i3c_master_bus_init,
1102     .bus_cleanup = dw_i3c_master_bus_cleanup,
1103     .attach_i3c_dev = dw_i3c_master_attach_i3c_dev,
1104     .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev,
1105     .detach_i3c_dev = dw_i3c_master_detach_i3c_dev,
1106     .do_daa = dw_i3c_master_daa,
1107     .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd,
1108     .send_ccc_cmd = dw_i3c_master_send_ccc_cmd,
1109     .priv_xfers = dw_i3c_master_priv_xfers,
1110     .attach_i2c_dev = dw_i3c_master_attach_i2c_dev,
1111     .detach_i2c_dev = dw_i3c_master_detach_i2c_dev,
1112     .i2c_xfers = dw_i3c_master_i2c_xfers,
1113 };
1114 
1115 static int dw_i3c_probe(struct platform_device *pdev)
1116 {
1117     struct dw_i3c_master *master;
1118     int ret, irq;
1119 
1120     master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1121     if (!master)
1122         return -ENOMEM;
1123 
1124     master->regs = devm_platform_ioremap_resource(pdev, 0);
1125     if (IS_ERR(master->regs))
1126         return PTR_ERR(master->regs);
1127 
1128     master->core_clk = devm_clk_get(&pdev->dev, NULL);
1129     if (IS_ERR(master->core_clk))
1130         return PTR_ERR(master->core_clk);
1131 
1132     master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
1133                                     "core_rst");
1134     if (IS_ERR(master->core_rst))
1135         return PTR_ERR(master->core_rst);
1136 
1137     ret = clk_prepare_enable(master->core_clk);
1138     if (ret)
1139         goto err_disable_core_clk;
1140 
1141     reset_control_deassert(master->core_rst);
1142 
1143     spin_lock_init(&master->xferqueue.lock);
1144     INIT_LIST_HEAD(&master->xferqueue.list);
1145 
1146     writel(INTR_ALL, master->regs + INTR_STATUS);
1147     irq = platform_get_irq(pdev, 0);
1148     ret = devm_request_irq(&pdev->dev, irq,
1149                    dw_i3c_master_irq_handler, 0,
1150                    dev_name(&pdev->dev), master);
1151     if (ret)
1152         goto err_assert_rst;
1153 
1154     platform_set_drvdata(pdev, master);
1155 
1156     /* Information regarding the FIFOs/QUEUEs depth */
1157     ret = readl(master->regs + QUEUE_STATUS_LEVEL);
1158     master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret);
1159 
1160     ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL);
1161     master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret);
1162 
1163     ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER);
1164     master->datstartaddr = ret;
1165     master->maxdevs = ret >> 16;
1166     master->free_pos = GENMASK(master->maxdevs - 1, 0);
1167 
1168     ret = i3c_master_register(&master->base, &pdev->dev,
1169                   &dw_mipi_i3c_ops, false);
1170     if (ret)
1171         goto err_assert_rst;
1172 
1173     return 0;
1174 
1175 err_assert_rst:
1176     reset_control_assert(master->core_rst);
1177 
1178 err_disable_core_clk:
1179     clk_disable_unprepare(master->core_clk);
1180 
1181     return ret;
1182 }
1183 
1184 static int dw_i3c_remove(struct platform_device *pdev)
1185 {
1186     struct dw_i3c_master *master = platform_get_drvdata(pdev);
1187     int ret;
1188 
1189     ret = i3c_master_unregister(&master->base);
1190     if (ret)
1191         return ret;
1192 
1193     reset_control_assert(master->core_rst);
1194 
1195     clk_disable_unprepare(master->core_clk);
1196 
1197     return 0;
1198 }
1199 
1200 static const struct of_device_id dw_i3c_master_of_match[] = {
1201     { .compatible = "snps,dw-i3c-master-1.00a", },
1202     {},
1203 };
1204 MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match);
1205 
1206 static struct platform_driver dw_i3c_driver = {
1207     .probe = dw_i3c_probe,
1208     .remove = dw_i3c_remove,
1209     .driver = {
1210         .name = "dw-i3c-master",
1211         .of_match_table = of_match_ptr(dw_i3c_master_of_match),
1212     },
1213 };
1214 module_platform_driver(dw_i3c_driver);
1215 
1216 MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>");
1217 MODULE_DESCRIPTION("DesignWare MIPI I3C driver");
1218 MODULE_LICENSE("GPL v2");
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