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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * i2c-xiic.c
0004  * Copyright (c) 2002-2007 Xilinx Inc.
0005  * Copyright (c) 2009-2010 Intel Corporation
0006  *
0007  * This code was implemented by Mocean Laboratories AB when porting linux
0008  * to the automotive development board Russellville. The copyright holder
0009  * as seen in the header is Intel corporation.
0010  * Mocean Laboratories forked off the GNU/Linux platform work into a
0011  * separate company called Pelagicore AB, which committed the code to the
0012  * kernel.
0013  */
0014 
0015 /* Supports:
0016  * Xilinx IIC
0017  */
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/errno.h>
0021 #include <linux/err.h>
0022 #include <linux/delay.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/i2c.h>
0025 #include <linux/interrupt.h>
0026 #include <linux/completion.h>
0027 #include <linux/platform_data/i2c-xiic.h>
0028 #include <linux/io.h>
0029 #include <linux/slab.h>
0030 #include <linux/of.h>
0031 #include <linux/clk.h>
0032 #include <linux/pm_runtime.h>
0033 
0034 #define DRIVER_NAME "xiic-i2c"
0035 
0036 enum xilinx_i2c_state {
0037     STATE_DONE,
0038     STATE_ERROR,
0039     STATE_START
0040 };
0041 
0042 enum xiic_endian {
0043     LITTLE,
0044     BIG
0045 };
0046 
0047 /**
0048  * struct xiic_i2c - Internal representation of the XIIC I2C bus
0049  * @dev: Pointer to device structure
0050  * @base: Memory base of the HW registers
0051  * @completion: Completion for callers
0052  * @adap: Kernel adapter representation
0053  * @tx_msg: Messages from above to be sent
0054  * @lock: Mutual exclusion
0055  * @tx_pos: Current pos in TX message
0056  * @nmsgs: Number of messages in tx_msg
0057  * @rx_msg: Current RX message
0058  * @rx_pos: Position within current RX message
0059  * @endianness: big/little-endian byte order
0060  * @clk: Pointer to AXI4-lite input clock
0061  * @state: See STATE_
0062  * @singlemaster: Indicates bus is single master
0063  */
0064 struct xiic_i2c {
0065     struct device *dev;
0066     void __iomem *base;
0067     struct completion completion;
0068     struct i2c_adapter adap;
0069     struct i2c_msg *tx_msg;
0070     struct mutex lock;
0071     unsigned int tx_pos;
0072     unsigned int nmsgs;
0073     struct i2c_msg *rx_msg;
0074     int rx_pos;
0075     enum xiic_endian endianness;
0076     struct clk *clk;
0077     enum xilinx_i2c_state state;
0078     bool singlemaster;
0079 };
0080 
0081 #define XIIC_MSB_OFFSET 0
0082 #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET)
0083 
0084 /*
0085  * Register offsets in bytes from RegisterBase. Three is added to the
0086  * base offset to access LSB (IBM style) of the word
0087  */
0088 #define XIIC_CR_REG_OFFSET   (0x00 + XIIC_REG_OFFSET)   /* Control Register   */
0089 #define XIIC_SR_REG_OFFSET   (0x04 + XIIC_REG_OFFSET)   /* Status Register    */
0090 #define XIIC_DTR_REG_OFFSET  (0x08 + XIIC_REG_OFFSET)   /* Data Tx Register   */
0091 #define XIIC_DRR_REG_OFFSET  (0x0C + XIIC_REG_OFFSET)   /* Data Rx Register   */
0092 #define XIIC_ADR_REG_OFFSET  (0x10 + XIIC_REG_OFFSET)   /* Address Register   */
0093 #define XIIC_TFO_REG_OFFSET  (0x14 + XIIC_REG_OFFSET)   /* Tx FIFO Occupancy  */
0094 #define XIIC_RFO_REG_OFFSET  (0x18 + XIIC_REG_OFFSET)   /* Rx FIFO Occupancy  */
0095 #define XIIC_TBA_REG_OFFSET  (0x1C + XIIC_REG_OFFSET)   /* 10 Bit Address reg */
0096 #define XIIC_RFD_REG_OFFSET  (0x20 + XIIC_REG_OFFSET)   /* Rx FIFO Depth reg  */
0097 #define XIIC_GPO_REG_OFFSET  (0x24 + XIIC_REG_OFFSET)   /* Output Register    */
0098 
0099 /* Control Register masks */
0100 #define XIIC_CR_ENABLE_DEVICE_MASK        0x01  /* Device enable = 1      */
0101 #define XIIC_CR_TX_FIFO_RESET_MASK        0x02  /* Transmit FIFO reset=1  */
0102 #define XIIC_CR_MSMS_MASK                 0x04  /* Master starts Txing=1  */
0103 #define XIIC_CR_DIR_IS_TX_MASK            0x08  /* Dir of tx. Txing=1     */
0104 #define XIIC_CR_NO_ACK_MASK               0x10  /* Tx Ack. NO ack = 1     */
0105 #define XIIC_CR_REPEATED_START_MASK       0x20  /* Repeated start = 1     */
0106 #define XIIC_CR_GENERAL_CALL_MASK         0x40  /* Gen Call enabled = 1   */
0107 
0108 /* Status Register masks */
0109 #define XIIC_SR_GEN_CALL_MASK             0x01  /* 1=a mstr issued a GC   */
0110 #define XIIC_SR_ADDR_AS_SLAVE_MASK        0x02  /* 1=when addr as slave   */
0111 #define XIIC_SR_BUS_BUSY_MASK             0x04  /* 1 = bus is busy        */
0112 #define XIIC_SR_MSTR_RDING_SLAVE_MASK     0x08  /* 1=Dir: mstr <-- slave  */
0113 #define XIIC_SR_TX_FIFO_FULL_MASK         0x10  /* 1 = Tx FIFO full       */
0114 #define XIIC_SR_RX_FIFO_FULL_MASK         0x20  /* 1 = Rx FIFO full       */
0115 #define XIIC_SR_RX_FIFO_EMPTY_MASK        0x40  /* 1 = Rx FIFO empty      */
0116 #define XIIC_SR_TX_FIFO_EMPTY_MASK        0x80  /* 1 = Tx FIFO empty      */
0117 
0118 /* Interrupt Status Register masks    Interrupt occurs when...       */
0119 #define XIIC_INTR_ARB_LOST_MASK           0x01  /* 1 = arbitration lost   */
0120 #define XIIC_INTR_TX_ERROR_MASK           0x02  /* 1=Tx error/msg complete */
0121 #define XIIC_INTR_TX_EMPTY_MASK           0x04  /* 1 = Tx FIFO/reg empty  */
0122 #define XIIC_INTR_RX_FULL_MASK            0x08  /* 1=Rx FIFO/reg=OCY level */
0123 #define XIIC_INTR_BNB_MASK                0x10  /* 1 = Bus not busy       */
0124 #define XIIC_INTR_AAS_MASK                0x20  /* 1 = when addr as slave */
0125 #define XIIC_INTR_NAAS_MASK               0x40  /* 1 = not addr as slave  */
0126 #define XIIC_INTR_TX_HALF_MASK            0x80  /* 1 = TX FIFO half empty */
0127 
0128 /* The following constants specify the depth of the FIFOs */
0129 #define IIC_RX_FIFO_DEPTH         16    /* Rx fifo capacity               */
0130 #define IIC_TX_FIFO_DEPTH         16    /* Tx fifo capacity               */
0131 
0132 /* The following constants specify groups of interrupts that are typically
0133  * enabled or disables at the same time
0134  */
0135 #define XIIC_TX_INTERRUPTS                           \
0136 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
0137 
0138 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
0139 
0140 /*
0141  * Tx Fifo upper bit masks.
0142  */
0143 #define XIIC_TX_DYN_START_MASK            0x0100 /* 1 = Set dynamic start */
0144 #define XIIC_TX_DYN_STOP_MASK             0x0200 /* 1 = Set dynamic stop */
0145 
0146 /*
0147  * The following constants define the register offsets for the Interrupt
0148  * registers. There are some holes in the memory map for reserved addresses
0149  * to allow other registers to be added and still match the memory map of the
0150  * interrupt controller registers
0151  */
0152 #define XIIC_DGIER_OFFSET    0x1C /* Device Global Interrupt Enable Register */
0153 #define XIIC_IISR_OFFSET     0x20 /* Interrupt Status Register */
0154 #define XIIC_IIER_OFFSET     0x28 /* Interrupt Enable Register */
0155 #define XIIC_RESETR_OFFSET   0x40 /* Reset Register */
0156 
0157 #define XIIC_RESET_MASK             0xAUL
0158 
0159 #define XIIC_PM_TIMEOUT     1000    /* ms */
0160 /* timeout waiting for the controller to respond */
0161 #define XIIC_I2C_TIMEOUT    (msecs_to_jiffies(1000))
0162 /* timeout waiting for the controller finish transfers */
0163 #define XIIC_XFER_TIMEOUT   (msecs_to_jiffies(10000))
0164 
0165 /*
0166  * The following constant is used for the device global interrupt enable
0167  * register, to enable all interrupts for the device, this is the only bit
0168  * in the register
0169  */
0170 #define XIIC_GINTR_ENABLE_MASK      0x80000000UL
0171 
0172 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
0173 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
0174 
0175 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num);
0176 static void __xiic_start_xfer(struct xiic_i2c *i2c);
0177 
0178 /*
0179  * For the register read and write functions, a little-endian and big-endian
0180  * version are necessary. Endianness is detected during the probe function.
0181  * Only the least significant byte [doublet] of the register are ever
0182  * accessed. This requires an offset of 3 [2] from the base address for
0183  * big-endian systems.
0184  */
0185 
0186 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
0187 {
0188     if (i2c->endianness == LITTLE)
0189         iowrite8(value, i2c->base + reg);
0190     else
0191         iowrite8(value, i2c->base + reg + 3);
0192 }
0193 
0194 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
0195 {
0196     u8 ret;
0197 
0198     if (i2c->endianness == LITTLE)
0199         ret = ioread8(i2c->base + reg);
0200     else
0201         ret = ioread8(i2c->base + reg + 3);
0202     return ret;
0203 }
0204 
0205 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
0206 {
0207     if (i2c->endianness == LITTLE)
0208         iowrite16(value, i2c->base + reg);
0209     else
0210         iowrite16be(value, i2c->base + reg + 2);
0211 }
0212 
0213 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
0214 {
0215     if (i2c->endianness == LITTLE)
0216         iowrite32(value, i2c->base + reg);
0217     else
0218         iowrite32be(value, i2c->base + reg);
0219 }
0220 
0221 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
0222 {
0223     u32 ret;
0224 
0225     if (i2c->endianness == LITTLE)
0226         ret = ioread32(i2c->base + reg);
0227     else
0228         ret = ioread32be(i2c->base + reg);
0229     return ret;
0230 }
0231 
0232 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
0233 {
0234     u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
0235 
0236     xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
0237 }
0238 
0239 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
0240 {
0241     u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
0242 
0243     xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
0244 }
0245 
0246 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
0247 {
0248     u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
0249 
0250     xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
0251 }
0252 
0253 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
0254 {
0255     xiic_irq_clr(i2c, mask);
0256     xiic_irq_en(i2c, mask);
0257 }
0258 
0259 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c)
0260 {
0261     u8 sr;
0262     unsigned long timeout;
0263 
0264     timeout = jiffies + XIIC_I2C_TIMEOUT;
0265     for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
0266         !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
0267         sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) {
0268         xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
0269         if (time_after(jiffies, timeout)) {
0270             dev_err(i2c->dev, "Failed to clear rx fifo\n");
0271             return -ETIMEDOUT;
0272         }
0273     }
0274 
0275     return 0;
0276 }
0277 
0278 static int xiic_reinit(struct xiic_i2c *i2c)
0279 {
0280     int ret;
0281 
0282     xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
0283 
0284     /* Set receive Fifo depth to maximum (zero based). */
0285     xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
0286 
0287     /* Reset Tx Fifo. */
0288     xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
0289 
0290     /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
0291     xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
0292 
0293     /* make sure RX fifo is empty */
0294     ret = xiic_clear_rx_fifo(i2c);
0295     if (ret)
0296         return ret;
0297 
0298     /* Enable interrupts */
0299     xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
0300 
0301     xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK);
0302 
0303     return 0;
0304 }
0305 
0306 static void xiic_deinit(struct xiic_i2c *i2c)
0307 {
0308     u8 cr;
0309 
0310     xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
0311 
0312     /* Disable IIC Device. */
0313     cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
0314     xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
0315 }
0316 
0317 static void xiic_read_rx(struct xiic_i2c *i2c)
0318 {
0319     u8 bytes_in_fifo;
0320     int i;
0321 
0322     bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
0323 
0324     dev_dbg(i2c->adap.dev.parent,
0325         "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n",
0326         __func__, bytes_in_fifo, xiic_rx_space(i2c),
0327         xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
0328         xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
0329 
0330     if (bytes_in_fifo > xiic_rx_space(i2c))
0331         bytes_in_fifo = xiic_rx_space(i2c);
0332 
0333     for (i = 0; i < bytes_in_fifo; i++)
0334         i2c->rx_msg->buf[i2c->rx_pos++] =
0335             xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
0336 
0337     xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
0338         (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
0339         IIC_RX_FIFO_DEPTH - 1 :  xiic_rx_space(i2c) - 1);
0340 }
0341 
0342 static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
0343 {
0344     /* return the actual space left in the FIFO */
0345     return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
0346 }
0347 
0348 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
0349 {
0350     u8 fifo_space = xiic_tx_fifo_space(i2c);
0351     int len = xiic_tx_space(i2c);
0352 
0353     len = (len > fifo_space) ? fifo_space : len;
0354 
0355     dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
0356         __func__, len, fifo_space);
0357 
0358     while (len--) {
0359         u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
0360 
0361         if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) {
0362             /* last message in transfer -> STOP */
0363             data |= XIIC_TX_DYN_STOP_MASK;
0364             dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
0365         }
0366         xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
0367     }
0368 }
0369 
0370 static void xiic_wakeup(struct xiic_i2c *i2c, enum xilinx_i2c_state code)
0371 {
0372     i2c->tx_msg = NULL;
0373     i2c->rx_msg = NULL;
0374     i2c->nmsgs = 0;
0375     i2c->state = code;
0376     complete(&i2c->completion);
0377 }
0378 
0379 static irqreturn_t xiic_process(int irq, void *dev_id)
0380 {
0381     struct xiic_i2c *i2c = dev_id;
0382     u32 pend, isr, ier;
0383     u32 clr = 0;
0384     int xfer_more = 0;
0385     int wakeup_req = 0;
0386     enum xilinx_i2c_state wakeup_code = STATE_DONE;
0387     int ret;
0388 
0389     /* Get the interrupt Status from the IPIF. There is no clearing of
0390      * interrupts in the IPIF. Interrupts must be cleared at the source.
0391      * To find which interrupts are pending; AND interrupts pending with
0392      * interrupts masked.
0393      */
0394     mutex_lock(&i2c->lock);
0395     isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
0396     ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
0397     pend = isr & ier;
0398 
0399     dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n",
0400         __func__, ier, isr, pend);
0401     dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n",
0402         __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
0403         i2c->tx_msg, i2c->nmsgs);
0404 
0405 
0406     /* Service requesting interrupt */
0407     if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
0408         ((pend & XIIC_INTR_TX_ERROR_MASK) &&
0409         !(pend & XIIC_INTR_RX_FULL_MASK))) {
0410         /* bus arbritration lost, or...
0411          * Transmit error _OR_ RX completed
0412          * if this happens when RX_FULL is not set
0413          * this is probably a TX error
0414          */
0415 
0416         dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
0417 
0418         /* dynamic mode seem to suffer from problems if we just flushes
0419          * fifos and the next message is a TX with len 0 (only addr)
0420          * reset the IP instead of just flush fifos
0421          */
0422         ret = xiic_reinit(i2c);
0423         if (!ret)
0424             dev_dbg(i2c->adap.dev.parent, "reinit failed\n");
0425 
0426         if (i2c->rx_msg) {
0427             wakeup_req = 1;
0428             wakeup_code = STATE_ERROR;
0429         }
0430         if (i2c->tx_msg) {
0431             wakeup_req = 1;
0432             wakeup_code = STATE_ERROR;
0433         }
0434     }
0435     if (pend & XIIC_INTR_RX_FULL_MASK) {
0436         /* Receive register/FIFO is full */
0437 
0438         clr |= XIIC_INTR_RX_FULL_MASK;
0439         if (!i2c->rx_msg) {
0440             dev_dbg(i2c->adap.dev.parent,
0441                 "%s unexpected RX IRQ\n", __func__);
0442             xiic_clear_rx_fifo(i2c);
0443             goto out;
0444         }
0445 
0446         xiic_read_rx(i2c);
0447         if (xiic_rx_space(i2c) == 0) {
0448             /* this is the last part of the message */
0449             i2c->rx_msg = NULL;
0450 
0451             /* also clear TX error if there (RX complete) */
0452             clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
0453 
0454             dev_dbg(i2c->adap.dev.parent,
0455                 "%s end of message, nmsgs: %d\n",
0456                 __func__, i2c->nmsgs);
0457 
0458             /* send next message if this wasn't the last,
0459              * otherwise the transfer will be finialise when
0460              * receiving the bus not busy interrupt
0461              */
0462             if (i2c->nmsgs > 1) {
0463                 i2c->nmsgs--;
0464                 i2c->tx_msg++;
0465                 dev_dbg(i2c->adap.dev.parent,
0466                     "%s will start next...\n", __func__);
0467                 xfer_more = 1;
0468             }
0469         }
0470     }
0471     if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
0472         /* Transmit register/FIFO is empty or ½ empty */
0473 
0474         clr |= (pend &
0475             (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK));
0476 
0477         if (!i2c->tx_msg) {
0478             dev_dbg(i2c->adap.dev.parent,
0479                 "%s unexpected TX IRQ\n", __func__);
0480             goto out;
0481         }
0482 
0483         xiic_fill_tx_fifo(i2c);
0484 
0485         /* current message sent and there is space in the fifo */
0486         if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
0487             dev_dbg(i2c->adap.dev.parent,
0488                 "%s end of message sent, nmsgs: %d\n",
0489                 __func__, i2c->nmsgs);
0490             if (i2c->nmsgs > 1) {
0491                 i2c->nmsgs--;
0492                 i2c->tx_msg++;
0493                 xfer_more = 1;
0494             } else {
0495                 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
0496 
0497                 dev_dbg(i2c->adap.dev.parent,
0498                     "%s Got TX IRQ but no more to do...\n",
0499                     __func__);
0500             }
0501         } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
0502             /* current frame is sent and is last,
0503              * make sure to disable tx half
0504              */
0505             xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
0506     }
0507 
0508     if (pend & XIIC_INTR_BNB_MASK) {
0509         /* IIC bus has transitioned to not busy */
0510         clr |= XIIC_INTR_BNB_MASK;
0511 
0512         /* The bus is not busy, disable BusNotBusy interrupt */
0513         xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
0514 
0515         if (!i2c->tx_msg)
0516             goto out;
0517 
0518         wakeup_req = 1;
0519 
0520         if (i2c->nmsgs == 1 && !i2c->rx_msg &&
0521             xiic_tx_space(i2c) == 0)
0522             wakeup_code = STATE_DONE;
0523         else
0524             wakeup_code = STATE_ERROR;
0525     }
0526 
0527 out:
0528     dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
0529 
0530     xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
0531     if (xfer_more)
0532         __xiic_start_xfer(i2c);
0533     if (wakeup_req)
0534         xiic_wakeup(i2c, wakeup_code);
0535 
0536     WARN_ON(xfer_more && wakeup_req);
0537 
0538     mutex_unlock(&i2c->lock);
0539     return IRQ_HANDLED;
0540 }
0541 
0542 static int xiic_bus_busy(struct xiic_i2c *i2c)
0543 {
0544     u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
0545 
0546     return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
0547 }
0548 
0549 static int xiic_busy(struct xiic_i2c *i2c)
0550 {
0551     int tries = 3;
0552     int err;
0553 
0554     if (i2c->tx_msg || i2c->rx_msg)
0555         return -EBUSY;
0556 
0557     /* In single master mode bus can only be busy, when in use by this
0558      * driver. If the register indicates bus being busy for some reason we
0559      * should ignore it, since bus will never be released and i2c will be
0560      * stuck forever.
0561      */
0562     if (i2c->singlemaster) {
0563         return 0;
0564     }
0565 
0566     /* for instance if previous transfer was terminated due to TX error
0567      * it might be that the bus is on it's way to become available
0568      * give it at most 3 ms to wake
0569      */
0570     err = xiic_bus_busy(i2c);
0571     while (err && tries--) {
0572         msleep(1);
0573         err = xiic_bus_busy(i2c);
0574     }
0575 
0576     return err;
0577 }
0578 
0579 static void xiic_start_recv(struct xiic_i2c *i2c)
0580 {
0581     u16 rx_watermark;
0582     struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
0583 
0584     /* Clear and enable Rx full interrupt. */
0585     xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
0586 
0587     /* we want to get all but last byte, because the TX_ERROR IRQ is used
0588      * to inidicate error ACK on the address, and negative ack on the last
0589      * received byte, so to not mix them receive all but last.
0590      * In the case where there is only one byte to receive
0591      * we can check if ERROR and RX full is set at the same time
0592      */
0593     rx_watermark = msg->len;
0594     if (rx_watermark > IIC_RX_FIFO_DEPTH)
0595         rx_watermark = IIC_RX_FIFO_DEPTH;
0596     xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, (u8)(rx_watermark - 1));
0597 
0598     if (!(msg->flags & I2C_M_NOSTART))
0599         /* write the address */
0600         xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
0601             i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK);
0602 
0603     xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
0604 
0605     xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
0606         msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
0607 
0608     if (i2c->nmsgs == 1)
0609         /* very last, enable bus not busy as well */
0610         xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
0611 
0612     /* the message is tx:ed */
0613     i2c->tx_pos = msg->len;
0614 }
0615 
0616 static void xiic_start_send(struct xiic_i2c *i2c)
0617 {
0618     struct i2c_msg *msg = i2c->tx_msg;
0619 
0620     dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d",
0621         __func__, msg, msg->len);
0622     dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n",
0623         __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
0624         xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
0625 
0626     if (!(msg->flags & I2C_M_NOSTART)) {
0627         /* write the address */
0628         u16 data = i2c_8bit_addr_from_msg(msg) |
0629             XIIC_TX_DYN_START_MASK;
0630         if ((i2c->nmsgs == 1) && msg->len == 0)
0631             /* no data and last message -> add STOP */
0632             data |= XIIC_TX_DYN_STOP_MASK;
0633 
0634         xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
0635     }
0636 
0637     /* Clear any pending Tx empty, Tx Error and then enable them. */
0638     xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
0639         XIIC_INTR_BNB_MASK |
0640         ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ?
0641             XIIC_INTR_TX_HALF_MASK : 0));
0642 
0643     xiic_fill_tx_fifo(i2c);
0644 }
0645 
0646 static void __xiic_start_xfer(struct xiic_i2c *i2c)
0647 {
0648     int fifo_space = xiic_tx_fifo_space(i2c);
0649 
0650     dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
0651         __func__, i2c->tx_msg, fifo_space);
0652 
0653     if (!i2c->tx_msg)
0654         return;
0655 
0656     i2c->rx_pos = 0;
0657     i2c->tx_pos = 0;
0658     i2c->state = STATE_START;
0659     if (i2c->tx_msg->flags & I2C_M_RD) {
0660         /* we dont date putting several reads in the FIFO */
0661         xiic_start_recv(i2c);
0662     } else {
0663         xiic_start_send(i2c);
0664     }
0665 }
0666 
0667 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num)
0668 {
0669     int ret;
0670 
0671     mutex_lock(&i2c->lock);
0672 
0673     ret = xiic_busy(i2c);
0674     if (ret)
0675         goto out;
0676 
0677     i2c->tx_msg = msgs;
0678     i2c->rx_msg = NULL;
0679     i2c->nmsgs = num;
0680     init_completion(&i2c->completion);
0681 
0682     ret = xiic_reinit(i2c);
0683     if (!ret)
0684         __xiic_start_xfer(i2c);
0685 
0686 out:
0687     mutex_unlock(&i2c->lock);
0688 
0689     return ret;
0690 }
0691 
0692 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
0693 {
0694     struct xiic_i2c *i2c = i2c_get_adapdata(adap);
0695     int err;
0696 
0697     dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
0698         xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
0699 
0700     err = pm_runtime_resume_and_get(i2c->dev);
0701     if (err < 0)
0702         return err;
0703 
0704     err = xiic_start_xfer(i2c, msgs, num);
0705     if (err < 0) {
0706         dev_err(adap->dev.parent, "Error xiic_start_xfer\n");
0707         return err;
0708     }
0709 
0710     err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT);
0711     mutex_lock(&i2c->lock);
0712     if (err == 0) { /* Timeout */
0713         i2c->tx_msg = NULL;
0714         i2c->rx_msg = NULL;
0715         i2c->nmsgs = 0;
0716         err = -ETIMEDOUT;
0717     } else if (err < 0) {   /* Completion error */
0718         i2c->tx_msg = NULL;
0719         i2c->rx_msg = NULL;
0720         i2c->nmsgs = 0;
0721     } else {
0722         err = (i2c->state == STATE_DONE) ? num : -EIO;
0723     }
0724     mutex_unlock(&i2c->lock);
0725     pm_runtime_mark_last_busy(i2c->dev);
0726     pm_runtime_put_autosuspend(i2c->dev);
0727     return err;
0728 }
0729 
0730 static u32 xiic_func(struct i2c_adapter *adap)
0731 {
0732     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0733 }
0734 
0735 static const struct i2c_algorithm xiic_algorithm = {
0736     .master_xfer = xiic_xfer,
0737     .functionality = xiic_func,
0738 };
0739 
0740 static const struct i2c_adapter_quirks xiic_quirks = {
0741     .max_read_len = 255,
0742 };
0743 
0744 static const struct i2c_adapter xiic_adapter = {
0745     .owner = THIS_MODULE,
0746     .class = I2C_CLASS_DEPRECATED,
0747     .algo = &xiic_algorithm,
0748     .quirks = &xiic_quirks,
0749 };
0750 
0751 static int xiic_i2c_probe(struct platform_device *pdev)
0752 {
0753     struct xiic_i2c *i2c;
0754     struct xiic_i2c_platform_data *pdata;
0755     struct resource *res;
0756     int ret, irq;
0757     u8 i;
0758     u32 sr;
0759 
0760     i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
0761     if (!i2c)
0762         return -ENOMEM;
0763 
0764     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0765     i2c->base = devm_ioremap_resource(&pdev->dev, res);
0766     if (IS_ERR(i2c->base))
0767         return PTR_ERR(i2c->base);
0768 
0769     irq = platform_get_irq(pdev, 0);
0770     if (irq < 0)
0771         return irq;
0772 
0773     pdata = dev_get_platdata(&pdev->dev);
0774 
0775     /* hook up driver to tree */
0776     platform_set_drvdata(pdev, i2c);
0777     i2c->adap = xiic_adapter;
0778     i2c_set_adapdata(&i2c->adap, i2c);
0779     i2c->adap.dev.parent = &pdev->dev;
0780     i2c->adap.dev.of_node = pdev->dev.of_node;
0781     snprintf(i2c->adap.name, sizeof(i2c->adap.name),
0782          DRIVER_NAME " %s", pdev->name);
0783 
0784     mutex_init(&i2c->lock);
0785 
0786     i2c->clk = devm_clk_get(&pdev->dev, NULL);
0787     if (IS_ERR(i2c->clk))
0788         return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
0789                      "input clock not found.\n");
0790 
0791     ret = clk_prepare_enable(i2c->clk);
0792     if (ret) {
0793         dev_err(&pdev->dev, "Unable to enable clock.\n");
0794         return ret;
0795     }
0796     i2c->dev = &pdev->dev;
0797     pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT);
0798     pm_runtime_use_autosuspend(i2c->dev);
0799     pm_runtime_set_active(i2c->dev);
0800     pm_runtime_enable(i2c->dev);
0801     ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
0802                     xiic_process, IRQF_ONESHOT,
0803                     pdev->name, i2c);
0804 
0805     if (ret < 0) {
0806         dev_err(&pdev->dev, "Cannot claim IRQ\n");
0807         goto err_clk_dis;
0808     }
0809 
0810     i2c->singlemaster =
0811         of_property_read_bool(pdev->dev.of_node, "single-master");
0812 
0813     /*
0814      * Detect endianness
0815      * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
0816      * set, assume that the endianness was wrong and swap.
0817      */
0818     i2c->endianness = LITTLE;
0819     xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
0820     /* Reset is cleared in xiic_reinit */
0821     sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
0822     if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
0823         i2c->endianness = BIG;
0824 
0825     ret = xiic_reinit(i2c);
0826     if (ret < 0) {
0827         dev_err(&pdev->dev, "Cannot xiic_reinit\n");
0828         goto err_clk_dis;
0829     }
0830 
0831     /* add i2c adapter to i2c tree */
0832     ret = i2c_add_adapter(&i2c->adap);
0833     if (ret) {
0834         xiic_deinit(i2c);
0835         goto err_clk_dis;
0836     }
0837 
0838     if (pdata) {
0839         /* add in known devices to the bus */
0840         for (i = 0; i < pdata->num_devices; i++)
0841             i2c_new_client_device(&i2c->adap, pdata->devices + i);
0842     }
0843 
0844     return 0;
0845 
0846 err_clk_dis:
0847     pm_runtime_set_suspended(&pdev->dev);
0848     pm_runtime_disable(&pdev->dev);
0849     clk_disable_unprepare(i2c->clk);
0850     return ret;
0851 }
0852 
0853 static int xiic_i2c_remove(struct platform_device *pdev)
0854 {
0855     struct xiic_i2c *i2c = platform_get_drvdata(pdev);
0856     int ret;
0857 
0858     /* remove adapter & data */
0859     i2c_del_adapter(&i2c->adap);
0860 
0861     ret = pm_runtime_resume_and_get(i2c->dev);
0862     if (ret < 0)
0863         return ret;
0864 
0865     xiic_deinit(i2c);
0866     pm_runtime_put_sync(i2c->dev);
0867     clk_disable_unprepare(i2c->clk);
0868     pm_runtime_disable(&pdev->dev);
0869     pm_runtime_set_suspended(&pdev->dev);
0870     pm_runtime_dont_use_autosuspend(&pdev->dev);
0871 
0872     return 0;
0873 }
0874 
0875 #if defined(CONFIG_OF)
0876 static const struct of_device_id xiic_of_match[] = {
0877     { .compatible = "xlnx,xps-iic-2.00.a", },
0878     {},
0879 };
0880 MODULE_DEVICE_TABLE(of, xiic_of_match);
0881 #endif
0882 
0883 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev)
0884 {
0885     struct xiic_i2c *i2c = dev_get_drvdata(dev);
0886 
0887     clk_disable(i2c->clk);
0888 
0889     return 0;
0890 }
0891 
0892 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev)
0893 {
0894     struct xiic_i2c *i2c = dev_get_drvdata(dev);
0895     int ret;
0896 
0897     ret = clk_enable(i2c->clk);
0898     if (ret) {
0899         dev_err(dev, "Cannot enable clock.\n");
0900         return ret;
0901     }
0902 
0903     return 0;
0904 }
0905 
0906 static const struct dev_pm_ops xiic_dev_pm_ops = {
0907     SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend,
0908                xiic_i2c_runtime_resume, NULL)
0909 };
0910 
0911 static struct platform_driver xiic_i2c_driver = {
0912     .probe   = xiic_i2c_probe,
0913     .remove  = xiic_i2c_remove,
0914     .driver  = {
0915         .name = DRIVER_NAME,
0916         .of_match_table = of_match_ptr(xiic_of_match),
0917         .pm = &xiic_dev_pm_ops,
0918     },
0919 };
0920 
0921 module_platform_driver(xiic_i2c_driver);
0922 
0923 MODULE_AUTHOR("info@mocean-labs.com");
0924 MODULE_DESCRIPTION("Xilinx I2C bus driver");
0925 MODULE_LICENSE("GPL v2");
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