i2c/busses/i2c-wmt.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Wondermedia I2C Master Mode Driver
0004  *
0005  *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
0006  *
0007  *  Derived from GPLv2+ licensed source:
0008  *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
0009  */
0010
0011 #include <linux/clk.h>
0012 #include <linux/delay.h>
0013 #include <linux/err.h>
0014 #include <linux/i2c.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/module.h>
0018 #include <linux/of.h>
0019 #include <linux/of_address.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/platform_device.h>
0022
0023 #define REG_CR      0x00
0024 #define REG_TCR     0x02
0025 #define REG_CSR     0x04
0026 #define REG_ISR     0x06
0027 #define REG_IMR     0x08
0028 #define REG_CDR     0x0A
0029 #define REG_TR      0x0C
0030 #define REG_MCR     0x0E
0031 #define REG_SLAVE_CR    0x10
0032 #define REG_SLAVE_SR    0x12
0033 #define REG_SLAVE_ISR   0x14
0034 #define REG_SLAVE_IMR   0x16
0035 #define REG_SLAVE_DR    0x18
0036 #define REG_SLAVE_TR    0x1A
0037
0038 /* REG_CR Bit fields */
0039 #define CR_TX_NEXT_ACK      0x0000
0040 #define CR_ENABLE       0x0001
0041 #define CR_TX_NEXT_NO_ACK   0x0002
0042 #define CR_TX_END       0x0004
0043 #define CR_CPU_RDY      0x0008
0044 #define SLAV_MODE_SEL       0x8000
0045
0046 /* REG_TCR Bit fields */
0047 #define TCR_STANDARD_MODE   0x0000
0048 #define TCR_MASTER_WRITE    0x0000
0049 #define TCR_HS_MODE     0x2000
0050 #define TCR_MASTER_READ     0x4000
0051 #define TCR_FAST_MODE       0x8000
0052 #define TCR_SLAVE_ADDR_MASK 0x007F
0053
0054 /* REG_ISR Bit fields */
0055 #define ISR_NACK_ADDR       0x0001
0056 #define ISR_BYTE_END        0x0002
0057 #define ISR_SCL_TIMEOUT     0x0004
0058 #define ISR_WRITE_ALL       0x0007
0059
0060 /* REG_IMR Bit fields */
0061 #define IMR_ENABLE_ALL      0x0007
0062
0063 /* REG_CSR Bit fields */
0064 #define CSR_RCV_NOT_ACK     0x0001
0065 #define CSR_RCV_ACK_MASK    0x0001
0066 #define CSR_READY_MASK      0x0002
0067
0068 /* REG_TR */
0069 #define SCL_TIMEOUT(x)      (((x) & 0xFF) << 8)
0070 #define TR_STD          0x0064
0071 #define TR_HS           0x0019
0072
0073 /* REG_MCR */
0074 #define MCR_APB_96M     7
0075 #define MCR_APB_166M        12
0076
0077 #define I2C_MODE_STANDARD   0
0078 #define I2C_MODE_FAST       1
0079
0080 #define WMT_I2C_TIMEOUT     (msecs_to_jiffies(1000))
0081
0082 struct wmt_i2c_dev {
0083     struct i2c_adapter  adapter;
0084     struct completion   complete;
0085     struct device       *dev;
0086     void __iomem        *base;
0087     struct clk      *clk;
0088     int         mode;
0089     int         irq;
0090     u16         cmd_status;
0091 };
0092
0093 static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
0094 {
0095     unsigned long timeout;
0096
0097     timeout = jiffies + WMT_I2C_TIMEOUT;
0098     while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
0099         if (time_after(jiffies, timeout)) {
0100             dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
0101             return -EBUSY;
0102         }
0103         msleep(20);
0104     }
0105
0106     return 0;
0107 }
0108
0109 static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
0110 {
0111     int ret = 0;
0112
0113     if (i2c_dev->cmd_status & ISR_NACK_ADDR)
0114         ret = -EIO;
0115
0116     if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
0117         ret = -ETIMEDOUT;
0118
0119     return ret;
0120 }
0121
0122 static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
0123              int last)
0124 {
0125     struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
0126     u16 val, tcr_val;
0127     int ret;
0128     unsigned long wait_result;
0129     int xfer_len = 0;
0130
0131     if (!(pmsg->flags & I2C_M_NOSTART)) {
0132         ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
0133         if (ret < 0)
0134             return ret;
0135     }
0136
0137     if (pmsg->len == 0) {
0138         /*
0139          * We still need to run through the while (..) once, so
0140          * start at -1 and break out early from the loop
0141          */
0142         xfer_len = -1;
0143         writew(0, i2c_dev->base + REG_CDR);
0144     } else {
0145         writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
0146     }
0147
0148     if (!(pmsg->flags & I2C_M_NOSTART)) {
0149         val = readw(i2c_dev->base + REG_CR);
0150         val &= ~CR_TX_END;
0151         writew(val, i2c_dev->base + REG_CR);
0152
0153         val = readw(i2c_dev->base + REG_CR);
0154         val |= CR_CPU_RDY;
0155         writew(val, i2c_dev->base + REG_CR);
0156     }
0157
0158     reinit_completion(&i2c_dev->complete);
0159
0160     if (i2c_dev->mode == I2C_MODE_STANDARD)
0161         tcr_val = TCR_STANDARD_MODE;
0162     else
0163         tcr_val = TCR_FAST_MODE;
0164
0165     tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
0166
0167     writew(tcr_val, i2c_dev->base + REG_TCR);
0168
0169     if (pmsg->flags & I2C_M_NOSTART) {
0170         val = readw(i2c_dev->base + REG_CR);
0171         val |= CR_CPU_RDY;
0172         writew(val, i2c_dev->base + REG_CR);
0173     }
0174
0175     while (xfer_len < pmsg->len) {
0176         wait_result = wait_for_completion_timeout(&i2c_dev->complete,
0177                             msecs_to_jiffies(500));
0178
0179         if (wait_result == 0)
0180             return -ETIMEDOUT;
0181
0182         ret = wmt_check_status(i2c_dev);
0183         if (ret)
0184             return ret;
0185
0186         xfer_len++;
0187
0188         val = readw(i2c_dev->base + REG_CSR);
0189         if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
0190             dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
0191             return -EIO;
0192         }
0193
0194         if (pmsg->len == 0) {
0195             val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
0196             writew(val, i2c_dev->base + REG_CR);
0197             break;
0198         }
0199
0200         if (xfer_len == pmsg->len) {
0201             if (last != 1)
0202                 writew(CR_ENABLE, i2c_dev->base + REG_CR);
0203         } else {
0204             writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
0205                                 REG_CDR);
0206             writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
0207         }
0208     }
0209
0210     return 0;
0211 }
0212
0213 static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
0214             int last)
0215 {
0216     struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
0217     u16 val, tcr_val;
0218     int ret;
0219     unsigned long wait_result;
0220     u32 xfer_len = 0;
0221
0222     if (!(pmsg->flags & I2C_M_NOSTART)) {
0223         ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
0224         if (ret < 0)
0225             return ret;
0226     }
0227
0228     val = readw(i2c_dev->base + REG_CR);
0229     val &= ~CR_TX_END;
0230     writew(val, i2c_dev->base + REG_CR);
0231
0232     val = readw(i2c_dev->base + REG_CR);
0233     val &= ~CR_TX_NEXT_NO_ACK;
0234     writew(val, i2c_dev->base + REG_CR);
0235
0236     if (!(pmsg->flags & I2C_M_NOSTART)) {
0237         val = readw(i2c_dev->base + REG_CR);
0238         val |= CR_CPU_RDY;
0239         writew(val, i2c_dev->base + REG_CR);
0240     }
0241
0242     if (pmsg->len == 1) {
0243         val = readw(i2c_dev->base + REG_CR);
0244         val |= CR_TX_NEXT_NO_ACK;
0245         writew(val, i2c_dev->base + REG_CR);
0246     }
0247
0248     reinit_completion(&i2c_dev->complete);
0249
0250     if (i2c_dev->mode == I2C_MODE_STANDARD)
0251         tcr_val = TCR_STANDARD_MODE;
0252     else
0253         tcr_val = TCR_FAST_MODE;
0254
0255     tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
0256
0257     writew(tcr_val, i2c_dev->base + REG_TCR);
0258
0259     if (pmsg->flags & I2C_M_NOSTART) {
0260         val = readw(i2c_dev->base + REG_CR);
0261         val |= CR_CPU_RDY;
0262         writew(val, i2c_dev->base + REG_CR);
0263     }
0264
0265     while (xfer_len < pmsg->len) {
0266         wait_result = wait_for_completion_timeout(&i2c_dev->complete,
0267                             msecs_to_jiffies(500));
0268
0269         if (!wait_result)
0270             return -ETIMEDOUT;
0271
0272         ret = wmt_check_status(i2c_dev);
0273         if (ret)
0274             return ret;
0275
0276         pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
0277         xfer_len++;
0278
0279         if (xfer_len == pmsg->len - 1) {
0280             val = readw(i2c_dev->base + REG_CR);
0281             val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
0282             writew(val, i2c_dev->base + REG_CR);
0283         } else {
0284             val = readw(i2c_dev->base + REG_CR);
0285             val |= CR_CPU_RDY;
0286             writew(val, i2c_dev->base + REG_CR);
0287         }
0288     }
0289
0290     return 0;
0291 }
0292
0293 static int wmt_i2c_xfer(struct i2c_adapter *adap,
0294             struct i2c_msg msgs[],
0295             int num)
0296 {
0297     struct i2c_msg *pmsg;
0298     int i, is_last;
0299     int ret = 0;
0300
0301     for (i = 0; ret >= 0 && i < num; i++) {
0302         is_last = ((i + 1) == num);
0303
0304         pmsg = &msgs[i];
0305         if (pmsg->flags & I2C_M_RD)
0306             ret = wmt_i2c_read(adap, pmsg, is_last);
0307         else
0308             ret = wmt_i2c_write(adap, pmsg, is_last);
0309     }
0310
0311     return (ret < 0) ? ret : i;
0312 }
0313
0314 static u32 wmt_i2c_func(struct i2c_adapter *adap)
0315 {
0316     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
0317 }
0318
0319 static const struct i2c_algorithm wmt_i2c_algo = {
0320     .master_xfer    = wmt_i2c_xfer,
0321     .functionality  = wmt_i2c_func,
0322 };
0323
0324 static irqreturn_t wmt_i2c_isr(int irq, void *data)
0325 {
0326     struct wmt_i2c_dev *i2c_dev = data;
0327
0328     /* save the status and write-clear it */
0329     i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
0330     writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
0331
0332     complete(&i2c_dev->complete);
0333
0334     return IRQ_HANDLED;
0335 }
0336
0337 static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
0338 {
0339     int err;
0340
0341     err = clk_prepare_enable(i2c_dev->clk);
0342     if (err) {
0343         dev_err(i2c_dev->dev, "failed to enable clock\n");
0344         return err;
0345     }
0346
0347     err = clk_set_rate(i2c_dev->clk, 20000000);
0348     if (err) {
0349         dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
0350         clk_disable_unprepare(i2c_dev->clk);
0351         return err;
0352     }
0353
0354     writew(0, i2c_dev->base + REG_CR);
0355     writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
0356     writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
0357     writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
0358     writew(CR_ENABLE, i2c_dev->base + REG_CR);
0359     readw(i2c_dev->base + REG_CSR);     /* read clear */
0360     writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
0361
0362     if (i2c_dev->mode == I2C_MODE_STANDARD)
0363         writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
0364     else
0365         writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
0366
0367     return 0;
0368 }
0369
0370 static int wmt_i2c_probe(struct platform_device *pdev)
0371 {
0372     struct device_node *np = pdev->dev.of_node;
0373     struct wmt_i2c_dev *i2c_dev;
0374     struct i2c_adapter *adap;
0375     struct resource *res;
0376     int err;
0377     u32 clk_rate;
0378
0379     i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
0380     if (!i2c_dev)
0381         return -ENOMEM;
0382
0383     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0384     i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
0385     if (IS_ERR(i2c_dev->base))
0386         return PTR_ERR(i2c_dev->base);
0387
0388     i2c_dev->irq = irq_of_parse_and_map(np, 0);
0389     if (!i2c_dev->irq) {
0390         dev_err(&pdev->dev, "irq missing or invalid\n");
0391         return -EINVAL;
0392     }
0393
0394     i2c_dev->clk = of_clk_get(np, 0);
0395     if (IS_ERR(i2c_dev->clk)) {
0396         dev_err(&pdev->dev, "unable to request clock\n");
0397         return PTR_ERR(i2c_dev->clk);
0398     }
0399
0400     i2c_dev->mode = I2C_MODE_STANDARD;
0401     err = of_property_read_u32(np, "clock-frequency", &clk_rate);
0402     if (!err && (clk_rate == I2C_MAX_FAST_MODE_FREQ))
0403         i2c_dev->mode = I2C_MODE_FAST;
0404
0405     i2c_dev->dev = &pdev->dev;
0406
0407     err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
0408                             "i2c", i2c_dev);
0409     if (err) {
0410         dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
0411         return err;
0412     }
0413
0414     adap = &i2c_dev->adapter;
0415     i2c_set_adapdata(adap, i2c_dev);
0416     strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
0417     adap->owner = THIS_MODULE;
0418     adap->algo = &wmt_i2c_algo;
0419     adap->dev.parent = &pdev->dev;
0420     adap->dev.of_node = pdev->dev.of_node;
0421
0422     init_completion(&i2c_dev->complete);
0423
0424     err = wmt_i2c_reset_hardware(i2c_dev);
0425     if (err) {
0426         dev_err(&pdev->dev, "error initializing hardware\n");
0427         return err;
0428     }
0429
0430     err = i2c_add_adapter(adap);
0431     if (err)
0432         return err;
0433
0434     platform_set_drvdata(pdev, i2c_dev);
0435
0436     return 0;
0437 }
0438
0439 static int wmt_i2c_remove(struct platform_device *pdev)
0440 {
0441     struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
0442
0443     /* Disable interrupts, clock and delete adapter */
0444     writew(0, i2c_dev->base + REG_IMR);
0445     clk_disable_unprepare(i2c_dev->clk);
0446     i2c_del_adapter(&i2c_dev->adapter);
0447
0448     return 0;
0449 }
0450
0451 static const struct of_device_id wmt_i2c_dt_ids[] = {
0452     { .compatible = "wm,wm8505-i2c" },
0453     { /* Sentinel */ },
0454 };
0455
0456 static struct platform_driver wmt_i2c_driver = {
0457     .probe      = wmt_i2c_probe,
0458     .remove     = wmt_i2c_remove,
0459     .driver     = {
0460         .name   = "wmt-i2c",
0461         .of_match_table = wmt_i2c_dt_ids,
0462     },
0463 };
0464
0465 module_platform_driver(wmt_i2c_driver);
0466
0467 MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
0468 MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
0469 MODULE_LICENSE("GPL");
0470 MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);