i2c/busses/i2c-uniphier-f.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/i2c.h>
0008 #include <linux/iopoll.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013
0014 #define UNIPHIER_FI2C_CR    0x00    /* control register */
0015 #define     UNIPHIER_FI2C_CR_MST    BIT(3)  /* master mode */
0016 #define     UNIPHIER_FI2C_CR_STA    BIT(2)  /* start condition */
0017 #define     UNIPHIER_FI2C_CR_STO    BIT(1)  /* stop condition */
0018 #define     UNIPHIER_FI2C_CR_NACK   BIT(0)  /* do not return ACK */
0019 #define UNIPHIER_FI2C_DTTX  0x04    /* TX FIFO */
0020 #define     UNIPHIER_FI2C_DTTX_CMD  BIT(8)  /* send command (slave addr) */
0021 #define     UNIPHIER_FI2C_DTTX_RD   BIT(0)  /* read transaction */
0022 #define UNIPHIER_FI2C_DTRX  0x04    /* RX FIFO */
0023 #define UNIPHIER_FI2C_SLAD  0x0c    /* slave address */
0024 #define UNIPHIER_FI2C_CYC   0x10    /* clock cycle control */
0025 #define UNIPHIER_FI2C_LCTL  0x14    /* clock low period control */
0026 #define UNIPHIER_FI2C_SSUT  0x18    /* restart/stop setup time control */
0027 #define UNIPHIER_FI2C_DSUT  0x1c    /* data setup time control */
0028 #define UNIPHIER_FI2C_INT   0x20    /* interrupt status */
0029 #define UNIPHIER_FI2C_IE    0x24    /* interrupt enable */
0030 #define UNIPHIER_FI2C_IC    0x28    /* interrupt clear */
0031 #define     UNIPHIER_FI2C_INT_TE    BIT(9)  /* TX FIFO empty */
0032 #define     UNIPHIER_FI2C_INT_RF    BIT(8)  /* RX FIFO full */
0033 #define     UNIPHIER_FI2C_INT_TC    BIT(7)  /* send complete (STOP) */
0034 #define     UNIPHIER_FI2C_INT_RC    BIT(6)  /* receive complete (STOP) */
0035 #define     UNIPHIER_FI2C_INT_TB    BIT(5)  /* sent specified bytes */
0036 #define     UNIPHIER_FI2C_INT_RB    BIT(4)  /* received specified bytes */
0037 #define     UNIPHIER_FI2C_INT_NA    BIT(2)  /* no ACK */
0038 #define     UNIPHIER_FI2C_INT_AL    BIT(1)  /* arbitration lost */
0039 #define UNIPHIER_FI2C_SR    0x2c    /* status register */
0040 #define     UNIPHIER_FI2C_SR_DB     BIT(12) /* device busy */
0041 #define     UNIPHIER_FI2C_SR_STS    BIT(11) /* stop condition detected */
0042 #define     UNIPHIER_FI2C_SR_BB     BIT(8)  /* bus busy */
0043 #define     UNIPHIER_FI2C_SR_RFF    BIT(3)  /* RX FIFO full */
0044 #define     UNIPHIER_FI2C_SR_RNE    BIT(2)  /* RX FIFO not empty */
0045 #define     UNIPHIER_FI2C_SR_TNF    BIT(1)  /* TX FIFO not full */
0046 #define     UNIPHIER_FI2C_SR_TFE    BIT(0)  /* TX FIFO empty */
0047 #define UNIPHIER_FI2C_RST   0x34    /* reset control */
0048 #define     UNIPHIER_FI2C_RST_TBRST BIT(2)  /* clear TX FIFO */
0049 #define     UNIPHIER_FI2C_RST_RBRST BIT(1)  /* clear RX FIFO */
0050 #define     UNIPHIER_FI2C_RST_RST   BIT(0)  /* forcible bus reset */
0051 #define UNIPHIER_FI2C_BM    0x38    /* bus monitor */
0052 #define     UNIPHIER_FI2C_BM_SDAO   BIT(3)  /* output for SDA line */
0053 #define     UNIPHIER_FI2C_BM_SDAS   BIT(2)  /* readback of SDA line */
0054 #define     UNIPHIER_FI2C_BM_SCLO   BIT(1)  /* output for SCL line */
0055 #define     UNIPHIER_FI2C_BM_SCLS   BIT(0)  /* readback of SCL line */
0056 #define UNIPHIER_FI2C_NOISE 0x3c    /* noise filter control */
0057 #define UNIPHIER_FI2C_TBC   0x40    /* TX byte count setting */
0058 #define UNIPHIER_FI2C_RBC   0x44    /* RX byte count setting */
0059 #define UNIPHIER_FI2C_TBCM  0x48    /* TX byte count monitor */
0060 #define UNIPHIER_FI2C_RBCM  0x4c    /* RX byte count monitor */
0061 #define UNIPHIER_FI2C_BRST  0x50    /* bus reset */
0062 #define     UNIPHIER_FI2C_BRST_FOEN BIT(1)  /* normal operation */
0063 #define     UNIPHIER_FI2C_BRST_RSCL BIT(0)  /* release SCL */
0064
0065 #define UNIPHIER_FI2C_INT_FAULTS    \
0066                 (UNIPHIER_FI2C_INT_NA | UNIPHIER_FI2C_INT_AL)
0067 #define UNIPHIER_FI2C_INT_STOP      \
0068                 (UNIPHIER_FI2C_INT_TC | UNIPHIER_FI2C_INT_RC)
0069
0070 #define UNIPHIER_FI2C_RD        BIT(0)
0071 #define UNIPHIER_FI2C_STOP      BIT(1)
0072 #define UNIPHIER_FI2C_MANUAL_NACK   BIT(2)
0073 #define UNIPHIER_FI2C_BYTE_WISE     BIT(3)
0074 #define UNIPHIER_FI2C_DEFER_STOP_COMP   BIT(4)
0075
0076 #define UNIPHIER_FI2C_FIFO_SIZE     8
0077
0078 struct uniphier_fi2c_priv {
0079     struct completion comp;
0080     struct i2c_adapter adap;
0081     void __iomem *membase;
0082     struct clk *clk;
0083     unsigned int len;
0084     u8 *buf;
0085     u32 enabled_irqs;
0086     int error;
0087     unsigned int flags;
0088     unsigned int busy_cnt;
0089     unsigned int clk_cycle;
0090     spinlock_t lock;    /* IRQ synchronization */
0091 };
0092
0093 static void uniphier_fi2c_fill_txfifo(struct uniphier_fi2c_priv *priv,
0094                       bool first)
0095 {
0096     int fifo_space = UNIPHIER_FI2C_FIFO_SIZE;
0097
0098     /*
0099      * TX-FIFO stores slave address in it for the first access.
0100      * Decrement the counter.
0101      */
0102     if (first)
0103         fifo_space--;
0104
0105     while (priv->len) {
0106         if (fifo_space-- <= 0)
0107             break;
0108
0109         writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX);
0110         priv->len--;
0111     }
0112 }
0113
0114 static void uniphier_fi2c_drain_rxfifo(struct uniphier_fi2c_priv *priv)
0115 {
0116     int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ?
0117                         1 : UNIPHIER_FI2C_FIFO_SIZE;
0118
0119     while (priv->len) {
0120         if (fifo_left-- <= 0)
0121             break;
0122
0123         *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX);
0124         priv->len--;
0125     }
0126 }
0127
0128 static void uniphier_fi2c_set_irqs(struct uniphier_fi2c_priv *priv)
0129 {
0130     writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE);
0131 }
0132
0133 static void uniphier_fi2c_clear_irqs(struct uniphier_fi2c_priv *priv,
0134                      u32 mask)
0135 {
0136     writel(mask, priv->membase + UNIPHIER_FI2C_IC);
0137 }
0138
0139 static void uniphier_fi2c_stop(struct uniphier_fi2c_priv *priv)
0140 {
0141     priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP;
0142     uniphier_fi2c_set_irqs(priv);
0143     writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO,
0144            priv->membase + UNIPHIER_FI2C_CR);
0145 }
0146
0147 static irqreturn_t uniphier_fi2c_interrupt(int irq, void *dev_id)
0148 {
0149     struct uniphier_fi2c_priv *priv = dev_id;
0150     u32 irq_status;
0151
0152     spin_lock(&priv->lock);
0153
0154     irq_status = readl(priv->membase + UNIPHIER_FI2C_INT);
0155     irq_status &= priv->enabled_irqs;
0156
0157     if (irq_status & UNIPHIER_FI2C_INT_STOP)
0158         goto complete;
0159
0160     if (unlikely(irq_status & UNIPHIER_FI2C_INT_AL)) {
0161         priv->error = -EAGAIN;
0162         goto complete;
0163     }
0164
0165     if (unlikely(irq_status & UNIPHIER_FI2C_INT_NA)) {
0166         priv->error = -ENXIO;
0167         if (priv->flags & UNIPHIER_FI2C_RD) {
0168             /*
0169              * work around a hardware bug:
0170              * The receive-completed interrupt is never set even if
0171              * STOP condition is detected after the address phase
0172              * of read transaction fails to get ACK.
0173              * To avoid time-out error, we issue STOP here,
0174              * but do not wait for its completion.
0175              * It should be checked after exiting this handler.
0176              */
0177             uniphier_fi2c_stop(priv);
0178             priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP;
0179             goto complete;
0180         }
0181         goto stop;
0182     }
0183
0184     if (irq_status & UNIPHIER_FI2C_INT_TE) {
0185         if (!priv->len)
0186             goto data_done;
0187
0188         uniphier_fi2c_fill_txfifo(priv, false);
0189         goto handled;
0190     }
0191
0192     if (irq_status & (UNIPHIER_FI2C_INT_RF | UNIPHIER_FI2C_INT_RB)) {
0193         uniphier_fi2c_drain_rxfifo(priv);
0194         /*
0195          * If the number of bytes to read is multiple of the FIFO size
0196          * (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little
0197          * earlier than INT_RB. We wait for INT_RB to confirm the
0198          * completion of the current message.
0199          */
0200         if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB))
0201             goto data_done;
0202
0203         if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) {
0204             if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE &&
0205                 !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) {
0206                 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB;
0207                 uniphier_fi2c_set_irqs(priv);
0208                 priv->flags |= UNIPHIER_FI2C_BYTE_WISE;
0209             }
0210             if (priv->len <= 1)
0211                 writel(UNIPHIER_FI2C_CR_MST |
0212                        UNIPHIER_FI2C_CR_NACK,
0213                        priv->membase + UNIPHIER_FI2C_CR);
0214         }
0215
0216         goto handled;
0217     }
0218
0219     spin_unlock(&priv->lock);
0220
0221     return IRQ_NONE;
0222
0223 data_done:
0224     if (priv->flags & UNIPHIER_FI2C_STOP) {
0225 stop:
0226         uniphier_fi2c_stop(priv);
0227     } else {
0228 complete:
0229         priv->enabled_irqs = 0;
0230         uniphier_fi2c_set_irqs(priv);
0231         complete(&priv->comp);
0232     }
0233
0234 handled:
0235     /*
0236      * This controller makes a pause while any bit of the IRQ status is
0237      * asserted. Clear the asserted bit to kick the controller just before
0238      * exiting the handler.
0239      */
0240     uniphier_fi2c_clear_irqs(priv, irq_status);
0241
0242     spin_unlock(&priv->lock);
0243
0244     return IRQ_HANDLED;
0245 }
0246
0247 static void uniphier_fi2c_tx_init(struct uniphier_fi2c_priv *priv, u16 addr,
0248                   bool repeat)
0249 {
0250     priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE;
0251     uniphier_fi2c_set_irqs(priv);
0252
0253     /* do not use TX byte counter */
0254     writel(0, priv->membase + UNIPHIER_FI2C_TBC);
0255     /* set slave address */
0256     writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1,
0257            priv->membase + UNIPHIER_FI2C_DTTX);
0258     /*
0259      * First chunk of data. For a repeated START condition, do not write
0260      * data to the TX fifo here to avoid the timing issue.
0261      */
0262     if (!repeat)
0263         uniphier_fi2c_fill_txfifo(priv, true);
0264 }
0265
0266 static void uniphier_fi2c_rx_init(struct uniphier_fi2c_priv *priv, u16 addr)
0267 {
0268     priv->flags |= UNIPHIER_FI2C_RD;
0269
0270     if (likely(priv->len < 256)) {
0271         /*
0272          * If possible, use RX byte counter.
0273          * It can automatically handle NACK for the last byte.
0274          */
0275         writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC);
0276         priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF |
0277                       UNIPHIER_FI2C_INT_RB;
0278     } else {
0279         /*
0280          * The byte counter can not count over 256.  In this case,
0281          * do not use it at all.  Drain data when FIFO gets full,
0282          * but treat the last portion as a special case.
0283          */
0284         writel(0, priv->membase + UNIPHIER_FI2C_RBC);
0285         priv->flags |= UNIPHIER_FI2C_MANUAL_NACK;
0286         priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF;
0287     }
0288
0289     uniphier_fi2c_set_irqs(priv);
0290
0291     /* set slave address with RD bit */
0292     writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1,
0293            priv->membase + UNIPHIER_FI2C_DTTX);
0294 }
0295
0296 static void uniphier_fi2c_reset(struct uniphier_fi2c_priv *priv)
0297 {
0298     writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST);
0299 }
0300
0301 static void uniphier_fi2c_prepare_operation(struct uniphier_fi2c_priv *priv)
0302 {
0303     writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL,
0304            priv->membase + UNIPHIER_FI2C_BRST);
0305 }
0306
0307 static void uniphier_fi2c_recover(struct uniphier_fi2c_priv *priv)
0308 {
0309     uniphier_fi2c_reset(priv);
0310     i2c_recover_bus(&priv->adap);
0311 }
0312
0313 static int uniphier_fi2c_master_xfer_one(struct i2c_adapter *adap,
0314                      struct i2c_msg *msg, bool repeat,
0315                      bool stop)
0316 {
0317     struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
0318     bool is_read = msg->flags & I2C_M_RD;
0319     unsigned long time_left, flags;
0320
0321     priv->len = msg->len;
0322     priv->buf = msg->buf;
0323     priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS;
0324     priv->error = 0;
0325     priv->flags = 0;
0326
0327     if (stop)
0328         priv->flags |= UNIPHIER_FI2C_STOP;
0329
0330     reinit_completion(&priv->comp);
0331     uniphier_fi2c_clear_irqs(priv, U32_MAX);
0332     writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST,
0333            priv->membase + UNIPHIER_FI2C_RST);  /* reset TX/RX FIFO */
0334
0335     spin_lock_irqsave(&priv->lock, flags);
0336
0337     if (is_read)
0338         uniphier_fi2c_rx_init(priv, msg->addr);
0339     else
0340         uniphier_fi2c_tx_init(priv, msg->addr, repeat);
0341
0342     /*
0343      * For a repeated START condition, writing a slave address to the FIFO
0344      * kicks the controller. So, the UNIPHIER_FI2C_CR register should be
0345      * written only for a non-repeated START condition.
0346      */
0347     if (!repeat)
0348         writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA,
0349                priv->membase + UNIPHIER_FI2C_CR);
0350
0351     spin_unlock_irqrestore(&priv->lock, flags);
0352
0353     time_left = wait_for_completion_timeout(&priv->comp, adap->timeout);
0354
0355     spin_lock_irqsave(&priv->lock, flags);
0356     priv->enabled_irqs = 0;
0357     uniphier_fi2c_set_irqs(priv);
0358     spin_unlock_irqrestore(&priv->lock, flags);
0359
0360     if (!time_left) {
0361         dev_err(&adap->dev, "transaction timeout.\n");
0362         uniphier_fi2c_recover(priv);
0363         return -ETIMEDOUT;
0364     }
0365
0366     if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) {
0367         u32 status;
0368         int ret;
0369
0370         ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR,
0371                      status,
0372                      (status & UNIPHIER_FI2C_SR_STS) &&
0373                      !(status & UNIPHIER_FI2C_SR_BB),
0374                      1, 20);
0375         if (ret) {
0376             dev_err(&adap->dev,
0377                 "stop condition was not completed.\n");
0378             uniphier_fi2c_recover(priv);
0379             return ret;
0380         }
0381     }
0382
0383     return priv->error;
0384 }
0385
0386 static int uniphier_fi2c_check_bus_busy(struct i2c_adapter *adap)
0387 {
0388     struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
0389
0390     if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) {
0391         if (priv->busy_cnt++ > 3) {
0392             /*
0393              * If bus busy continues too long, it is probably
0394              * in a wrong state.  Try bus recovery.
0395              */
0396             uniphier_fi2c_recover(priv);
0397             priv->busy_cnt = 0;
0398         }
0399
0400         return -EAGAIN;
0401     }
0402
0403     priv->busy_cnt = 0;
0404     return 0;
0405 }
0406
0407 static int uniphier_fi2c_master_xfer(struct i2c_adapter *adap,
0408                      struct i2c_msg *msgs, int num)
0409 {
0410     struct i2c_msg *msg, *emsg = msgs + num;
0411     bool repeat = false;
0412     int ret;
0413
0414     ret = uniphier_fi2c_check_bus_busy(adap);
0415     if (ret)
0416         return ret;
0417
0418     for (msg = msgs; msg < emsg; msg++) {
0419         /* Emit STOP if it is the last message or I2C_M_STOP is set. */
0420         bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP);
0421
0422         ret = uniphier_fi2c_master_xfer_one(adap, msg, repeat, stop);
0423         if (ret)
0424             return ret;
0425
0426         repeat = !stop;
0427     }
0428
0429     return num;
0430 }
0431
0432 static u32 uniphier_fi2c_functionality(struct i2c_adapter *adap)
0433 {
0434     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0435 }
0436
0437 static const struct i2c_algorithm uniphier_fi2c_algo = {
0438     .master_xfer = uniphier_fi2c_master_xfer,
0439     .functionality = uniphier_fi2c_functionality,
0440 };
0441
0442 static int uniphier_fi2c_get_scl(struct i2c_adapter *adap)
0443 {
0444     struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
0445
0446     return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
0447                             UNIPHIER_FI2C_BM_SCLS);
0448 }
0449
0450 static void uniphier_fi2c_set_scl(struct i2c_adapter *adap, int val)
0451 {
0452     struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
0453
0454     writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0,
0455            priv->membase + UNIPHIER_FI2C_BRST);
0456 }
0457
0458 static int uniphier_fi2c_get_sda(struct i2c_adapter *adap)
0459 {
0460     struct uniphier_fi2c_priv *priv = i2c_get_adapdata(adap);
0461
0462     return !!(readl(priv->membase + UNIPHIER_FI2C_BM) &
0463                             UNIPHIER_FI2C_BM_SDAS);
0464 }
0465
0466 static void uniphier_fi2c_unprepare_recovery(struct i2c_adapter *adap)
0467 {
0468     uniphier_fi2c_prepare_operation(i2c_get_adapdata(adap));
0469 }
0470
0471 static struct i2c_bus_recovery_info uniphier_fi2c_bus_recovery_info = {
0472     .recover_bus = i2c_generic_scl_recovery,
0473     .get_scl = uniphier_fi2c_get_scl,
0474     .set_scl = uniphier_fi2c_set_scl,
0475     .get_sda = uniphier_fi2c_get_sda,
0476     .unprepare_recovery = uniphier_fi2c_unprepare_recovery,
0477 };
0478
0479 static void uniphier_fi2c_hw_init(struct uniphier_fi2c_priv *priv)
0480 {
0481     unsigned int cyc = priv->clk_cycle;
0482     u32 tmp;
0483
0484     tmp = readl(priv->membase + UNIPHIER_FI2C_CR);
0485     tmp |= UNIPHIER_FI2C_CR_MST;
0486     writel(tmp, priv->membase + UNIPHIER_FI2C_CR);
0487
0488     uniphier_fi2c_reset(priv);
0489
0490     /*
0491      *  Standard-mode: tLOW + tHIGH = 10 us
0492      *  Fast-mode:     tLOW + tHIGH = 2.5 us
0493      */
0494     writel(cyc, priv->membase + UNIPHIER_FI2C_CYC);
0495     /*
0496      *  Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us
0497      *  Fast-mode:     tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us
0498      * "tLow/tHIGH = 5/4" meets both.
0499      */
0500     writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL);
0501     /*
0502      *  Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us
0503      *  Fast-mode:     tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us
0504      */
0505     writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT);
0506     /*
0507      *  Standard-mode: tSU;DAT = 250 ns
0508      *  Fast-mode:     tSU;DAT = 100 ns
0509      */
0510     writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT);
0511
0512     uniphier_fi2c_prepare_operation(priv);
0513 }
0514
0515 static int uniphier_fi2c_probe(struct platform_device *pdev)
0516 {
0517     struct device *dev = &pdev->dev;
0518     struct uniphier_fi2c_priv *priv;
0519     u32 bus_speed;
0520     unsigned long clk_rate;
0521     int irq, ret;
0522
0523     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0524     if (!priv)
0525         return -ENOMEM;
0526
0527     priv->membase = devm_platform_ioremap_resource(pdev, 0);
0528     if (IS_ERR(priv->membase))
0529         return PTR_ERR(priv->membase);
0530
0531     irq = platform_get_irq(pdev, 0);
0532     if (irq < 0)
0533         return irq;
0534
0535     if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed))
0536         bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
0537
0538     if (!bus_speed || bus_speed > I2C_MAX_FAST_MODE_FREQ) {
0539         dev_err(dev, "invalid clock-frequency %d\n", bus_speed);
0540         return -EINVAL;
0541     }
0542
0543     priv->clk = devm_clk_get(dev, NULL);
0544     if (IS_ERR(priv->clk)) {
0545         dev_err(dev, "failed to get clock\n");
0546         return PTR_ERR(priv->clk);
0547     }
0548
0549     ret = clk_prepare_enable(priv->clk);
0550     if (ret)
0551         return ret;
0552
0553     clk_rate = clk_get_rate(priv->clk);
0554     if (!clk_rate) {
0555         dev_err(dev, "input clock rate should not be zero\n");
0556         ret = -EINVAL;
0557         goto disable_clk;
0558     }
0559
0560     priv->clk_cycle = clk_rate / bus_speed;
0561     init_completion(&priv->comp);
0562     spin_lock_init(&priv->lock);
0563     priv->adap.owner = THIS_MODULE;
0564     priv->adap.algo = &uniphier_fi2c_algo;
0565     priv->adap.dev.parent = dev;
0566     priv->adap.dev.of_node = dev->of_node;
0567     strscpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name));
0568     priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info;
0569     i2c_set_adapdata(&priv->adap, priv);
0570     platform_set_drvdata(pdev, priv);
0571
0572     uniphier_fi2c_hw_init(priv);
0573
0574     ret = devm_request_irq(dev, irq, uniphier_fi2c_interrupt, 0,
0575                    pdev->name, priv);
0576     if (ret) {
0577         dev_err(dev, "failed to request irq %d\n", irq);
0578         goto disable_clk;
0579     }
0580
0581     ret = i2c_add_adapter(&priv->adap);
0582 disable_clk:
0583     if (ret)
0584         clk_disable_unprepare(priv->clk);
0585
0586     return ret;
0587 }
0588
0589 static int uniphier_fi2c_remove(struct platform_device *pdev)
0590 {
0591     struct uniphier_fi2c_priv *priv = platform_get_drvdata(pdev);
0592
0593     i2c_del_adapter(&priv->adap);
0594     clk_disable_unprepare(priv->clk);
0595
0596     return 0;
0597 }
0598
0599 static int __maybe_unused uniphier_fi2c_suspend(struct device *dev)
0600 {
0601     struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
0602
0603     clk_disable_unprepare(priv->clk);
0604
0605     return 0;
0606 }
0607
0608 static int __maybe_unused uniphier_fi2c_resume(struct device *dev)
0609 {
0610     struct uniphier_fi2c_priv *priv = dev_get_drvdata(dev);
0611     int ret;
0612
0613     ret = clk_prepare_enable(priv->clk);
0614     if (ret)
0615         return ret;
0616
0617     uniphier_fi2c_hw_init(priv);
0618
0619     return 0;
0620 }
0621
0622 static const struct dev_pm_ops uniphier_fi2c_pm_ops = {
0623     SET_SYSTEM_SLEEP_PM_OPS(uniphier_fi2c_suspend, uniphier_fi2c_resume)
0624 };
0625
0626 static const struct of_device_id uniphier_fi2c_match[] = {
0627     { .compatible = "socionext,uniphier-fi2c" },
0628     { /* sentinel */ }
0629 };
0630 MODULE_DEVICE_TABLE(of, uniphier_fi2c_match);
0631
0632 static struct platform_driver uniphier_fi2c_drv = {
0633     .probe  = uniphier_fi2c_probe,
0634     .remove = uniphier_fi2c_remove,
0635     .driver = {
0636         .name  = "uniphier-fi2c",
0637         .of_match_table = uniphier_fi2c_match,
0638         .pm = &uniphier_fi2c_pm_ops,
0639     },
0640 };
0641 module_platform_driver(uniphier_fi2c_drv);
0642
0643 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
0644 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");
0645 MODULE_LICENSE("GPL");