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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2012 FUJITSU SEMICONDUCTOR LIMITED
0004  */
0005 
0006 #include <linux/acpi.h>
0007 #include <linux/clk.h>
0008 #include <linux/delay.h>
0009 #include <linux/device.h>
0010 #include <linux/err.h>
0011 #include <linux/errno.h>
0012 #include <linux/i2c.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/sched.h>
0019 #include <linux/slab.h>
0020 #include <linux/spinlock.h>
0021 
0022 #define WAIT_PCLK(n, rate)  \
0023     ndelay(DIV_ROUND_UP(DIV_ROUND_UP(1000000000, rate), n) + 10)
0024 
0025 /* I2C register address definitions */
0026 #define SYNQUACER_I2C_REG_BSR       (0x00 << 2) // Bus Status
0027 #define SYNQUACER_I2C_REG_BCR       (0x01 << 2) // Bus Control
0028 #define SYNQUACER_I2C_REG_CCR       (0x02 << 2) // Clock Control
0029 #define SYNQUACER_I2C_REG_ADR       (0x03 << 2) // Address
0030 #define SYNQUACER_I2C_REG_DAR       (0x04 << 2) // Data
0031 #define SYNQUACER_I2C_REG_CSR       (0x05 << 2) // Expansion CS
0032 #define SYNQUACER_I2C_REG_FSR       (0x06 << 2) // Bus Clock Freq
0033 #define SYNQUACER_I2C_REG_BC2R      (0x07 << 2) // Bus Control 2
0034 
0035 /* I2C register bit definitions */
0036 #define SYNQUACER_I2C_BSR_FBT       BIT(0)  // First Byte Transfer
0037 #define SYNQUACER_I2C_BSR_GCA       BIT(1)  // General Call Address
0038 #define SYNQUACER_I2C_BSR_AAS       BIT(2)  // Address as Slave
0039 #define SYNQUACER_I2C_BSR_TRX       BIT(3)  // Transfer/Receive
0040 #define SYNQUACER_I2C_BSR_LRB       BIT(4)  // Last Received Bit
0041 #define SYNQUACER_I2C_BSR_AL        BIT(5)  // Arbitration Lost
0042 #define SYNQUACER_I2C_BSR_RSC       BIT(6)  // Repeated Start Cond.
0043 #define SYNQUACER_I2C_BSR_BB        BIT(7)  // Bus Busy
0044 
0045 #define SYNQUACER_I2C_BCR_INT       BIT(0)  // Interrupt
0046 #define SYNQUACER_I2C_BCR_INTE      BIT(1)  // Interrupt Enable
0047 #define SYNQUACER_I2C_BCR_GCAA      BIT(2)  // Gen. Call Access Ack.
0048 #define SYNQUACER_I2C_BCR_ACK       BIT(3)  // Acknowledge
0049 #define SYNQUACER_I2C_BCR_MSS       BIT(4)  // Master Slave Select
0050 #define SYNQUACER_I2C_BCR_SCC       BIT(5)  // Start Condition Cont.
0051 #define SYNQUACER_I2C_BCR_BEIE      BIT(6)  // Bus Error Int Enable
0052 #define SYNQUACER_I2C_BCR_BER       BIT(7)  // Bus Error
0053 
0054 #define SYNQUACER_I2C_CCR_CS_MASK   (0x1f)  // CCR Clock Period Sel.
0055 #define SYNQUACER_I2C_CCR_EN        BIT(5)  // Enable
0056 #define SYNQUACER_I2C_CCR_FM        BIT(6)  // Speed Mode Select
0057 
0058 #define SYNQUACER_I2C_CSR_CS_MASK   (0x3f)  // CSR Clock Period Sel.
0059 
0060 #define SYNQUACER_I2C_BC2R_SCLL     BIT(0)  // SCL Low Drive
0061 #define SYNQUACER_I2C_BC2R_SDAL     BIT(1)  // SDA Low Drive
0062 #define SYNQUACER_I2C_BC2R_SCLS     BIT(4)  // SCL Status
0063 #define SYNQUACER_I2C_BC2R_SDAS     BIT(5)  // SDA Status
0064 
0065 /* PCLK frequency */
0066 #define SYNQUACER_I2C_BUS_CLK_FR(rate)  (((rate) / 20000000) + 1)
0067 
0068 /* STANDARD MODE frequency */
0069 #define SYNQUACER_I2C_CLK_MASTER_STD(rate)          \
0070     DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
0071 /* FAST MODE frequency */
0072 #define SYNQUACER_I2C_CLK_MASTER_FAST(rate)         \
0073     DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
0074 
0075 /* (clkrate <= 18000000) */
0076 /* calculate the value of CS bits in CCR register on standard mode */
0077 #define SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rate)          \
0078        ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65)       \
0079                     & SYNQUACER_I2C_CCR_CS_MASK)
0080 
0081 /* calculate the value of CS bits in CSR register on standard mode */
0082 #define SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rate)      0x00
0083 
0084 /* calculate the value of CS bits in CCR register on fast mode */
0085 #define SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rate)         \
0086        ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1)       \
0087                     & SYNQUACER_I2C_CCR_CS_MASK)
0088 
0089 /* calculate the value of CS bits in CSR register on fast mode */
0090 #define SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rate)     0x00
0091 
0092 /* (clkrate > 18000000) */
0093 /* calculate the value of CS bits in CCR register on standard mode */
0094 #define SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rate)          \
0095        ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1)        \
0096                     & SYNQUACER_I2C_CCR_CS_MASK)
0097 
0098 /* calculate the value of CS bits in CSR register on standard mode */
0099 #define SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rate)          \
0100        (((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 1) >> 5) \
0101                     & SYNQUACER_I2C_CSR_CS_MASK)
0102 
0103 /* calculate the value of CS bits in CCR register on fast mode */
0104 #define SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rate)         \
0105        ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1)       \
0106                     & SYNQUACER_I2C_CCR_CS_MASK)
0107 
0108 /* calculate the value of CS bits in CSR register on fast mode */
0109 #define SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rate)         \
0110        (((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) >> 5)    \
0111                     & SYNQUACER_I2C_CSR_CS_MASK)
0112 
0113 /* min I2C clock frequency 14M */
0114 #define SYNQUACER_I2C_MIN_CLK_RATE  (14 * 1000000)
0115 /* max I2C clock frequency 200M */
0116 #define SYNQUACER_I2C_MAX_CLK_RATE  (200 * 1000000)
0117 /* I2C clock frequency 18M */
0118 #define SYNQUACER_I2C_CLK_RATE_18M  (18 * 1000000)
0119 
0120 #define SYNQUACER_I2C_SPEED_FM      400 // Fast Mode
0121 #define SYNQUACER_I2C_SPEED_SM      100 // Standard Mode
0122 
0123 enum i2c_state {
0124     STATE_IDLE,
0125     STATE_START,
0126     STATE_READ,
0127     STATE_WRITE
0128 };
0129 
0130 struct synquacer_i2c {
0131     struct completion   completion;
0132 
0133     struct i2c_msg      *msg;
0134     u32         msg_num;
0135     u32         msg_idx;
0136     u32         msg_ptr;
0137 
0138     int         irq;
0139     struct device       *dev;
0140     void __iomem        *base;
0141     struct clk      *pclk;
0142     u32         pclkrate;
0143     u32         speed_khz;
0144     u32         timeout_ms;
0145     enum i2c_state      state;
0146     struct i2c_adapter  adapter;
0147 };
0148 
0149 static inline int is_lastmsg(struct synquacer_i2c *i2c)
0150 {
0151     return i2c->msg_idx >= (i2c->msg_num - 1);
0152 }
0153 
0154 static inline int is_msglast(struct synquacer_i2c *i2c)
0155 {
0156     return i2c->msg_ptr == (i2c->msg->len - 1);
0157 }
0158 
0159 static inline int is_msgend(struct synquacer_i2c *i2c)
0160 {
0161     return i2c->msg_ptr >= i2c->msg->len;
0162 }
0163 
0164 static inline unsigned long calc_timeout_ms(struct synquacer_i2c *i2c,
0165                         struct i2c_msg *msgs,
0166                         int num)
0167 {
0168     unsigned long bit_count = 0;
0169     int i;
0170 
0171     for (i = 0; i < num; i++, msgs++)
0172         bit_count += msgs->len;
0173 
0174     return DIV_ROUND_UP((bit_count * 9 + num * 10) * 3, 200) + 10;
0175 }
0176 
0177 static void synquacer_i2c_stop(struct synquacer_i2c *i2c, int ret)
0178 {
0179     /*
0180      * clear IRQ (INT=0, BER=0)
0181      * set Stop Condition (MSS=0)
0182      * Interrupt Disable
0183      */
0184     writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
0185 
0186     i2c->state = STATE_IDLE;
0187 
0188     i2c->msg_ptr = 0;
0189     i2c->msg = NULL;
0190     i2c->msg_idx++;
0191     i2c->msg_num = 0;
0192     if (ret)
0193         i2c->msg_idx = ret;
0194 
0195     complete(&i2c->completion);
0196 }
0197 
0198 static void synquacer_i2c_hw_init(struct synquacer_i2c *i2c)
0199 {
0200     unsigned char ccr_cs, csr_cs;
0201     u32 rt = i2c->pclkrate;
0202 
0203     /* Set own Address */
0204     writeb(0, i2c->base + SYNQUACER_I2C_REG_ADR);
0205 
0206     /* Set PCLK frequency */
0207     writeb(SYNQUACER_I2C_BUS_CLK_FR(i2c->pclkrate),
0208            i2c->base + SYNQUACER_I2C_REG_FSR);
0209 
0210     switch (i2c->speed_khz) {
0211     case SYNQUACER_I2C_SPEED_FM:
0212         if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
0213             ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MAX_18M(rt);
0214             csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MAX_18M(rt);
0215         } else {
0216             ccr_cs = SYNQUACER_I2C_CCR_CS_FAST_MIN_18M(rt);
0217             csr_cs = SYNQUACER_I2C_CSR_CS_FAST_MIN_18M(rt);
0218         }
0219 
0220         /* Set Clock and enable, Set fast mode */
0221         writeb(ccr_cs | SYNQUACER_I2C_CCR_FM |
0222                SYNQUACER_I2C_CCR_EN,
0223                i2c->base + SYNQUACER_I2C_REG_CCR);
0224         writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
0225         break;
0226     case SYNQUACER_I2C_SPEED_SM:
0227         if (i2c->pclkrate <= SYNQUACER_I2C_CLK_RATE_18M) {
0228             ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MAX_18M(rt);
0229             csr_cs = SYNQUACER_I2C_CSR_CS_STD_MAX_18M(rt);
0230         } else {
0231             ccr_cs = SYNQUACER_I2C_CCR_CS_STD_MIN_18M(rt);
0232             csr_cs = SYNQUACER_I2C_CSR_CS_STD_MIN_18M(rt);
0233         }
0234 
0235         /* Set Clock and enable, Set standard mode */
0236         writeb(ccr_cs | SYNQUACER_I2C_CCR_EN,
0237               i2c->base + SYNQUACER_I2C_REG_CCR);
0238         writeb(csr_cs, i2c->base + SYNQUACER_I2C_REG_CSR);
0239         break;
0240     default:
0241         WARN_ON(1);
0242     }
0243 
0244     /* clear IRQ (INT=0, BER=0), Interrupt Disable */
0245     writeb(0, i2c->base + SYNQUACER_I2C_REG_BCR);
0246     writeb(0, i2c->base + SYNQUACER_I2C_REG_BC2R);
0247 }
0248 
0249 static void synquacer_i2c_hw_reset(struct synquacer_i2c *i2c)
0250 {
0251     /* Disable clock */
0252     writeb(0, i2c->base + SYNQUACER_I2C_REG_CCR);
0253     writeb(0, i2c->base + SYNQUACER_I2C_REG_CSR);
0254 
0255     WAIT_PCLK(100, i2c->pclkrate);
0256 }
0257 
0258 static int synquacer_i2c_master_start(struct synquacer_i2c *i2c,
0259                       struct i2c_msg *pmsg)
0260 {
0261     unsigned char bsr, bcr;
0262 
0263     writeb(i2c_8bit_addr_from_msg(pmsg), i2c->base + SYNQUACER_I2C_REG_DAR);
0264 
0265     dev_dbg(i2c->dev, "slave:0x%02x\n", pmsg->addr);
0266 
0267     /* Generate Start Condition */
0268     bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
0269     bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
0270     dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
0271 
0272     if ((bsr & SYNQUACER_I2C_BSR_BB) &&
0273         !(bcr & SYNQUACER_I2C_BCR_MSS)) {
0274         dev_dbg(i2c->dev, "bus is busy");
0275         return -EBUSY;
0276     }
0277 
0278     if (bsr & SYNQUACER_I2C_BSR_BB) { /* Bus is busy */
0279         dev_dbg(i2c->dev, "Continuous Start");
0280         writeb(bcr | SYNQUACER_I2C_BCR_SCC,
0281                i2c->base + SYNQUACER_I2C_REG_BCR);
0282     } else {
0283         if (bcr & SYNQUACER_I2C_BCR_MSS) {
0284             dev_dbg(i2c->dev, "not in master mode");
0285             return -EAGAIN;
0286         }
0287         dev_dbg(i2c->dev, "Start Condition");
0288         /* Start Condition + Enable Interrupts */
0289         writeb(bcr | SYNQUACER_I2C_BCR_MSS |
0290                SYNQUACER_I2C_BCR_INTE | SYNQUACER_I2C_BCR_BEIE,
0291                i2c->base + SYNQUACER_I2C_REG_BCR);
0292     }
0293 
0294     WAIT_PCLK(10, i2c->pclkrate);
0295 
0296     /* get BSR & BCR registers */
0297     bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
0298     bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
0299     dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
0300 
0301     if ((bsr & SYNQUACER_I2C_BSR_AL) ||
0302         !(bcr & SYNQUACER_I2C_BCR_MSS)) {
0303         dev_dbg(i2c->dev, "arbitration lost\n");
0304         return -EAGAIN;
0305     }
0306 
0307     return 0;
0308 }
0309 
0310 static int synquacer_i2c_doxfer(struct synquacer_i2c *i2c,
0311                 struct i2c_msg *msgs, int num)
0312 {
0313     unsigned char bsr;
0314     unsigned long timeout;
0315     int ret;
0316 
0317     synquacer_i2c_hw_init(i2c);
0318     bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
0319     if (bsr & SYNQUACER_I2C_BSR_BB) {
0320         dev_err(i2c->dev, "cannot get bus (bus busy)\n");
0321         return -EBUSY;
0322     }
0323 
0324     reinit_completion(&i2c->completion);
0325 
0326     i2c->msg = msgs;
0327     i2c->msg_num = num;
0328     i2c->msg_ptr = 0;
0329     i2c->msg_idx = 0;
0330     i2c->state = STATE_START;
0331 
0332     ret = synquacer_i2c_master_start(i2c, i2c->msg);
0333     if (ret < 0) {
0334         dev_dbg(i2c->dev, "Address failed: (%d)\n", ret);
0335         return ret;
0336     }
0337 
0338     timeout = wait_for_completion_timeout(&i2c->completion,
0339                     msecs_to_jiffies(i2c->timeout_ms));
0340     if (timeout == 0) {
0341         dev_dbg(i2c->dev, "timeout\n");
0342         return -EAGAIN;
0343     }
0344 
0345     ret = i2c->msg_idx;
0346     if (ret != num) {
0347         dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
0348         return -EAGAIN;
0349     }
0350 
0351     /* wait 2 clock periods to ensure the stop has been through the bus */
0352     udelay(DIV_ROUND_UP(2 * 1000, i2c->speed_khz));
0353 
0354     return ret;
0355 }
0356 
0357 static irqreturn_t synquacer_i2c_isr(int irq, void *dev_id)
0358 {
0359     struct synquacer_i2c *i2c = dev_id;
0360 
0361     unsigned char byte;
0362     unsigned char bsr, bcr;
0363     int ret;
0364 
0365     bcr = readb(i2c->base + SYNQUACER_I2C_REG_BCR);
0366     bsr = readb(i2c->base + SYNQUACER_I2C_REG_BSR);
0367     dev_dbg(i2c->dev, "bsr:0x%02x, bcr:0x%02x\n", bsr, bcr);
0368 
0369     if (bcr & SYNQUACER_I2C_BCR_BER) {
0370         dev_err(i2c->dev, "bus error\n");
0371         synquacer_i2c_stop(i2c, -EAGAIN);
0372         goto out;
0373     }
0374     if ((bsr & SYNQUACER_I2C_BSR_AL) ||
0375         !(bcr & SYNQUACER_I2C_BCR_MSS)) {
0376         dev_dbg(i2c->dev, "arbitration lost\n");
0377         synquacer_i2c_stop(i2c, -EAGAIN);
0378         goto out;
0379     }
0380 
0381     switch (i2c->state) {
0382     case STATE_START:
0383         if (bsr & SYNQUACER_I2C_BSR_LRB) {
0384             dev_dbg(i2c->dev, "ack was not received\n");
0385             synquacer_i2c_stop(i2c, -EAGAIN);
0386             goto out;
0387         }
0388 
0389         if (i2c->msg->flags & I2C_M_RD)
0390             i2c->state = STATE_READ;
0391         else
0392             i2c->state = STATE_WRITE;
0393 
0394         if (is_lastmsg(i2c) && i2c->msg->len == 0) {
0395             synquacer_i2c_stop(i2c, 0);
0396             goto out;
0397         }
0398 
0399         if (i2c->state == STATE_READ)
0400             goto prepare_read;
0401         fallthrough;
0402 
0403     case STATE_WRITE:
0404         if (bsr & SYNQUACER_I2C_BSR_LRB) {
0405             dev_dbg(i2c->dev, "WRITE: No Ack\n");
0406             synquacer_i2c_stop(i2c, -EAGAIN);
0407             goto out;
0408         }
0409 
0410         if (!is_msgend(i2c)) {
0411             writeb(i2c->msg->buf[i2c->msg_ptr++],
0412                    i2c->base + SYNQUACER_I2C_REG_DAR);
0413 
0414             /* clear IRQ, and continue */
0415             writeb(SYNQUACER_I2C_BCR_BEIE |
0416                    SYNQUACER_I2C_BCR_MSS |
0417                    SYNQUACER_I2C_BCR_INTE,
0418                    i2c->base + SYNQUACER_I2C_REG_BCR);
0419             break;
0420         }
0421         if (is_lastmsg(i2c)) {
0422             synquacer_i2c_stop(i2c, 0);
0423             break;
0424         }
0425         dev_dbg(i2c->dev, "WRITE: Next Message\n");
0426 
0427         i2c->msg_ptr = 0;
0428         i2c->msg_idx++;
0429         i2c->msg++;
0430 
0431         /* send the new start */
0432         ret = synquacer_i2c_master_start(i2c, i2c->msg);
0433         if (ret < 0) {
0434             dev_dbg(i2c->dev, "restart error (%d)\n", ret);
0435             synquacer_i2c_stop(i2c, -EAGAIN);
0436             break;
0437         }
0438         i2c->state = STATE_START;
0439         break;
0440 
0441     case STATE_READ:
0442         byte = readb(i2c->base + SYNQUACER_I2C_REG_DAR);
0443         if (!(bsr & SYNQUACER_I2C_BSR_FBT)) /* data */
0444             i2c->msg->buf[i2c->msg_ptr++] = byte;
0445         else /* address */
0446             dev_dbg(i2c->dev, "address:0x%02x. ignore it.\n", byte);
0447 
0448 prepare_read:
0449         if (is_msglast(i2c)) {
0450             writeb(SYNQUACER_I2C_BCR_MSS |
0451                    SYNQUACER_I2C_BCR_BEIE |
0452                    SYNQUACER_I2C_BCR_INTE,
0453                    i2c->base + SYNQUACER_I2C_REG_BCR);
0454             break;
0455         }
0456         if (!is_msgend(i2c)) {
0457             writeb(SYNQUACER_I2C_BCR_MSS |
0458                    SYNQUACER_I2C_BCR_BEIE |
0459                    SYNQUACER_I2C_BCR_INTE |
0460                    SYNQUACER_I2C_BCR_ACK,
0461                    i2c->base + SYNQUACER_I2C_REG_BCR);
0462             break;
0463         }
0464         if (is_lastmsg(i2c)) {
0465             /* last message, send stop and complete */
0466             dev_dbg(i2c->dev, "READ: Send Stop\n");
0467             synquacer_i2c_stop(i2c, 0);
0468             break;
0469         }
0470         dev_dbg(i2c->dev, "READ: Next Transfer\n");
0471 
0472         i2c->msg_ptr = 0;
0473         i2c->msg_idx++;
0474         i2c->msg++;
0475 
0476         ret = synquacer_i2c_master_start(i2c, i2c->msg);
0477         if (ret < 0) {
0478             dev_dbg(i2c->dev, "restart error (%d)\n", ret);
0479             synquacer_i2c_stop(i2c, -EAGAIN);
0480         } else {
0481             i2c->state = STATE_START;
0482         }
0483         break;
0484     default:
0485         dev_err(i2c->dev, "called in err STATE (%d)\n", i2c->state);
0486         break;
0487     }
0488 
0489 out:
0490     WAIT_PCLK(10, i2c->pclkrate);
0491     return IRQ_HANDLED;
0492 }
0493 
0494 static int synquacer_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
0495                   int num)
0496 {
0497     struct synquacer_i2c *i2c;
0498     int retry;
0499     int ret;
0500 
0501     i2c = i2c_get_adapdata(adap);
0502     i2c->timeout_ms = calc_timeout_ms(i2c, msgs, num);
0503 
0504     dev_dbg(i2c->dev, "calculated timeout %d ms\n", i2c->timeout_ms);
0505 
0506     for (retry = 0; retry <= adap->retries; retry++) {
0507         ret = synquacer_i2c_doxfer(i2c, msgs, num);
0508         if (ret != -EAGAIN)
0509             return ret;
0510 
0511         dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
0512 
0513         synquacer_i2c_hw_reset(i2c);
0514     }
0515     return -EIO;
0516 }
0517 
0518 static u32 synquacer_i2c_functionality(struct i2c_adapter *adap)
0519 {
0520     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0521 }
0522 
0523 static const struct i2c_algorithm synquacer_i2c_algo = {
0524     .master_xfer    = synquacer_i2c_xfer,
0525     .functionality  = synquacer_i2c_functionality,
0526 };
0527 
0528 static const struct i2c_adapter synquacer_i2c_ops = {
0529     .owner      = THIS_MODULE,
0530     .name       = "synquacer_i2c-adapter",
0531     .algo       = &synquacer_i2c_algo,
0532     .retries    = 5,
0533 };
0534 
0535 static int synquacer_i2c_probe(struct platform_device *pdev)
0536 {
0537     struct synquacer_i2c *i2c;
0538     u32 bus_speed;
0539     int ret;
0540 
0541     i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
0542     if (!i2c)
0543         return -ENOMEM;
0544 
0545     bus_speed = i2c_acpi_find_bus_speed(&pdev->dev);
0546     if (!bus_speed)
0547         device_property_read_u32(&pdev->dev, "clock-frequency",
0548                      &bus_speed);
0549 
0550     device_property_read_u32(&pdev->dev, "socionext,pclk-rate",
0551                  &i2c->pclkrate);
0552 
0553     i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
0554     if (PTR_ERR(i2c->pclk) == -EPROBE_DEFER)
0555         return -EPROBE_DEFER;
0556     if (!IS_ERR_OR_NULL(i2c->pclk)) {
0557         dev_dbg(&pdev->dev, "clock source %p\n", i2c->pclk);
0558 
0559         ret = clk_prepare_enable(i2c->pclk);
0560         if (ret) {
0561             dev_err(&pdev->dev, "failed to enable clock (%d)\n",
0562                 ret);
0563             return ret;
0564         }
0565         i2c->pclkrate = clk_get_rate(i2c->pclk);
0566     }
0567 
0568     if (i2c->pclkrate < SYNQUACER_I2C_MIN_CLK_RATE ||
0569         i2c->pclkrate > SYNQUACER_I2C_MAX_CLK_RATE) {
0570         dev_err(&pdev->dev, "PCLK missing or out of range (%d)\n",
0571             i2c->pclkrate);
0572         return -EINVAL;
0573     }
0574 
0575     i2c->base = devm_platform_ioremap_resource(pdev, 0);
0576     if (IS_ERR(i2c->base))
0577         return PTR_ERR(i2c->base);
0578 
0579     i2c->irq = platform_get_irq(pdev, 0);
0580     if (i2c->irq < 0)
0581         return i2c->irq;
0582 
0583     ret = devm_request_irq(&pdev->dev, i2c->irq, synquacer_i2c_isr,
0584                    0, dev_name(&pdev->dev), i2c);
0585     if (ret < 0) {
0586         dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
0587         return ret;
0588     }
0589 
0590     i2c->state = STATE_IDLE;
0591     i2c->dev = &pdev->dev;
0592     i2c->adapter = synquacer_i2c_ops;
0593     i2c_set_adapdata(&i2c->adapter, i2c);
0594     i2c->adapter.dev.parent = &pdev->dev;
0595     i2c->adapter.dev.of_node = pdev->dev.of_node;
0596     ACPI_COMPANION_SET(&i2c->adapter.dev, ACPI_COMPANION(&pdev->dev));
0597     i2c->adapter.nr = pdev->id;
0598     init_completion(&i2c->completion);
0599 
0600     if (bus_speed < I2C_MAX_FAST_MODE_FREQ)
0601         i2c->speed_khz = SYNQUACER_I2C_SPEED_SM;
0602     else
0603         i2c->speed_khz = SYNQUACER_I2C_SPEED_FM;
0604 
0605     synquacer_i2c_hw_init(i2c);
0606 
0607     ret = i2c_add_numbered_adapter(&i2c->adapter);
0608     if (ret) {
0609         dev_err(&pdev->dev, "failed to add bus to i2c core\n");
0610         return ret;
0611     }
0612 
0613     platform_set_drvdata(pdev, i2c);
0614 
0615     dev_info(&pdev->dev, "%s: synquacer_i2c adapter\n",
0616          dev_name(&i2c->adapter.dev));
0617 
0618     return 0;
0619 }
0620 
0621 static int synquacer_i2c_remove(struct platform_device *pdev)
0622 {
0623     struct synquacer_i2c *i2c = platform_get_drvdata(pdev);
0624 
0625     i2c_del_adapter(&i2c->adapter);
0626     if (!IS_ERR(i2c->pclk))
0627         clk_disable_unprepare(i2c->pclk);
0628 
0629     return 0;
0630 };
0631 
0632 static const struct of_device_id synquacer_i2c_dt_ids[] = {
0633     { .compatible = "socionext,synquacer-i2c" },
0634     { /* sentinel */ }
0635 };
0636 MODULE_DEVICE_TABLE(of, synquacer_i2c_dt_ids);
0637 
0638 #ifdef CONFIG_ACPI
0639 static const struct acpi_device_id synquacer_i2c_acpi_ids[] = {
0640     { "SCX0003" },
0641     { /* sentinel */ }
0642 };
0643 MODULE_DEVICE_TABLE(acpi, synquacer_i2c_acpi_ids);
0644 #endif
0645 
0646 static struct platform_driver synquacer_i2c_driver = {
0647     .probe  = synquacer_i2c_probe,
0648     .remove = synquacer_i2c_remove,
0649     .driver = {
0650         .name = "synquacer_i2c",
0651         .of_match_table = of_match_ptr(synquacer_i2c_dt_ids),
0652         .acpi_match_table = ACPI_PTR(synquacer_i2c_acpi_ids),
0653     },
0654 };
0655 module_platform_driver(synquacer_i2c_driver);
0656 
0657 MODULE_AUTHOR("Fujitsu Semiconductor Ltd");
0658 MODULE_DESCRIPTION("Socionext SynQuacer I2C Driver");
0659 MODULE_LICENSE("GPL v2");
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