i2c/busses/i2c-sun6i-p2wi.c

0001 /*
0002  * P2WI (Push-Pull Two Wire Interface) bus driver.
0003  *
0004  * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
0005  *
0006  * This file is licensed under the terms of the GNU General Public License
0007  * version 2.  This program is licensed "as is" without any warranty of any
0008  * kind, whether express or implied.
0009  *
0010  * The P2WI controller looks like an SMBus controller which only supports byte
0011  * data transfers. But, it differs from standard SMBus protocol on several
0012  * aspects:
0013  * - it supports only one slave device, and thus drop the address field
0014  * - it adds a parity bit every 8bits of data
0015  * - only one read access is required to read a byte (instead of a write
0016  *   followed by a read access in standard SMBus protocol)
0017  * - there's no Ack bit after each byte transfer
0018  *
0019  * This means this bus cannot be used to interface with standard SMBus
0020  * devices (the only known device to support this interface is the AXP221
0021  * PMIC).
0022  *
0023  */
0024 #include <linux/clk.h>
0025 #include <linux/i2c.h>
0026 #include <linux/io.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/module.h>
0029 #include <linux/of.h>
0030 #include <linux/platform_device.h>
0031 #include <linux/reset.h>
0032
0033
0034 /* P2WI registers */
0035 #define P2WI_CTRL       0x0
0036 #define P2WI_CCR        0x4
0037 #define P2WI_INTE       0x8
0038 #define P2WI_INTS       0xc
0039 #define P2WI_DADDR0     0x10
0040 #define P2WI_DADDR1     0x14
0041 #define P2WI_DLEN       0x18
0042 #define P2WI_DATA0      0x1c
0043 #define P2WI_DATA1      0x20
0044 #define P2WI_LCR        0x24
0045 #define P2WI_PMCR       0x28
0046
0047 /* CTRL fields */
0048 #define P2WI_CTRL_START_TRANS       BIT(7)
0049 #define P2WI_CTRL_ABORT_TRANS       BIT(6)
0050 #define P2WI_CTRL_GLOBAL_INT_ENB    BIT(1)
0051 #define P2WI_CTRL_SOFT_RST      BIT(0)
0052
0053 /* CLK CTRL fields */
0054 #define P2WI_CCR_SDA_OUT_DELAY(v)   (((v) & 0x7) << 8)
0055 #define P2WI_CCR_MAX_CLK_DIV        0xff
0056 #define P2WI_CCR_CLK_DIV(v)     ((v) & P2WI_CCR_MAX_CLK_DIV)
0057
0058 /* STATUS fields */
0059 #define P2WI_INTS_TRANS_ERR_ID(v)   (((v) >> 8) & 0xff)
0060 #define P2WI_INTS_LOAD_BSY      BIT(2)
0061 #define P2WI_INTS_TRANS_ERR     BIT(1)
0062 #define P2WI_INTS_TRANS_OVER        BIT(0)
0063
0064 /* DATA LENGTH fields*/
0065 #define P2WI_DLEN_READ          BIT(4)
0066 #define P2WI_DLEN_DATA_LENGTH(v)    ((v - 1) & 0x7)
0067
0068 /* LINE CTRL fields*/
0069 #define P2WI_LCR_SCL_STATE      BIT(5)
0070 #define P2WI_LCR_SDA_STATE      BIT(4)
0071 #define P2WI_LCR_SCL_CTL        BIT(3)
0072 #define P2WI_LCR_SCL_CTL_EN     BIT(2)
0073 #define P2WI_LCR_SDA_CTL        BIT(1)
0074 #define P2WI_LCR_SDA_CTL_EN     BIT(0)
0075
0076 /* PMU MODE CTRL fields */
0077 #define P2WI_PMCR_PMU_INIT_SEND     BIT(31)
0078 #define P2WI_PMCR_PMU_INIT_DATA(v)  (((v) & 0xff) << 16)
0079 #define P2WI_PMCR_PMU_MODE_REG(v)   (((v) & 0xff) << 8)
0080 #define P2WI_PMCR_PMU_DEV_ADDR(v)   ((v) & 0xff)
0081
0082 #define P2WI_MAX_FREQ           6000000
0083
0084 struct p2wi {
0085     struct i2c_adapter adapter;
0086     struct completion complete;
0087     unsigned int status;
0088     void __iomem *regs;
0089     struct clk *clk;
0090     struct reset_control *rstc;
0091     int slave_addr;
0092 };
0093
0094 static irqreturn_t p2wi_interrupt(int irq, void *dev_id)
0095 {
0096     struct p2wi *p2wi = dev_id;
0097     unsigned long status;
0098
0099     status = readl(p2wi->regs + P2WI_INTS);
0100     p2wi->status = status;
0101
0102     /* Clear interrupts */
0103     status &= (P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR |
0104            P2WI_INTS_TRANS_OVER);
0105     writel(status, p2wi->regs + P2WI_INTS);
0106
0107     complete(&p2wi->complete);
0108
0109     return IRQ_HANDLED;
0110 }
0111
0112 static u32 p2wi_functionality(struct i2c_adapter *adap)
0113 {
0114     return I2C_FUNC_SMBUS_BYTE_DATA;
0115 }
0116
0117 static int p2wi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
0118                unsigned short flags, char read_write,
0119                u8 command, int size, union i2c_smbus_data *data)
0120 {
0121     struct p2wi *p2wi = i2c_get_adapdata(adap);
0122     unsigned long dlen = P2WI_DLEN_DATA_LENGTH(1);
0123
0124     if (p2wi->slave_addr >= 0 && addr != p2wi->slave_addr) {
0125         dev_err(&adap->dev, "invalid P2WI address\n");
0126         return -EINVAL;
0127     }
0128
0129     if (!data)
0130         return -EINVAL;
0131
0132     writel(command, p2wi->regs + P2WI_DADDR0);
0133
0134     if (read_write == I2C_SMBUS_READ)
0135         dlen |= P2WI_DLEN_READ;
0136     else
0137         writel(data->byte, p2wi->regs + P2WI_DATA0);
0138
0139     writel(dlen, p2wi->regs + P2WI_DLEN);
0140
0141     if (readl(p2wi->regs + P2WI_CTRL) & P2WI_CTRL_START_TRANS) {
0142         dev_err(&adap->dev, "P2WI bus busy\n");
0143         return -EBUSY;
0144     }
0145
0146     reinit_completion(&p2wi->complete);
0147
0148     writel(P2WI_INTS_LOAD_BSY | P2WI_INTS_TRANS_ERR | P2WI_INTS_TRANS_OVER,
0149            p2wi->regs + P2WI_INTE);
0150
0151     writel(P2WI_CTRL_START_TRANS | P2WI_CTRL_GLOBAL_INT_ENB,
0152            p2wi->regs + P2WI_CTRL);
0153
0154     wait_for_completion(&p2wi->complete);
0155
0156     if (p2wi->status & P2WI_INTS_LOAD_BSY) {
0157         dev_err(&adap->dev, "P2WI bus busy\n");
0158         return -EBUSY;
0159     }
0160
0161     if (p2wi->status & P2WI_INTS_TRANS_ERR) {
0162         dev_err(&adap->dev, "P2WI bus xfer error\n");
0163         return -ENXIO;
0164     }
0165
0166     if (read_write == I2C_SMBUS_READ)
0167         data->byte = readl(p2wi->regs + P2WI_DATA0);
0168
0169     return 0;
0170 }
0171
0172 static const struct i2c_algorithm p2wi_algo = {
0173     .smbus_xfer = p2wi_smbus_xfer,
0174     .functionality = p2wi_functionality,
0175 };
0176
0177 static const struct of_device_id p2wi_of_match_table[] = {
0178     { .compatible = "allwinner,sun6i-a31-p2wi" },
0179     {}
0180 };
0181 MODULE_DEVICE_TABLE(of, p2wi_of_match_table);
0182
0183 static int p2wi_probe(struct platform_device *pdev)
0184 {
0185     struct device *dev = &pdev->dev;
0186     struct device_node *np = dev->of_node;
0187     struct device_node *childnp;
0188     unsigned long parent_clk_freq;
0189     u32 clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
0190     struct p2wi *p2wi;
0191     u32 slave_addr;
0192     int clk_div;
0193     int irq;
0194     int ret;
0195
0196     of_property_read_u32(np, "clock-frequency", &clk_freq);
0197     if (clk_freq > P2WI_MAX_FREQ) {
0198         dev_err(dev,
0199             "required clock-frequency (%u Hz) is too high (max = 6MHz)",
0200             clk_freq);
0201         return -EINVAL;
0202     }
0203
0204     if (of_get_child_count(np) > 1) {
0205         dev_err(dev, "P2WI only supports one slave device\n");
0206         return -EINVAL;
0207     }
0208
0209     p2wi = devm_kzalloc(dev, sizeof(struct p2wi), GFP_KERNEL);
0210     if (!p2wi)
0211         return -ENOMEM;
0212
0213     p2wi->slave_addr = -1;
0214
0215     /*
0216      * Authorize a p2wi node without any children to be able to use an
0217      * i2c-dev from userpace.
0218      * In this case the slave_addr is set to -1 and won't be checked when
0219      * launching a P2WI transfer.
0220      */
0221     childnp = of_get_next_available_child(np, NULL);
0222     if (childnp) {
0223         ret = of_property_read_u32(childnp, "reg", &slave_addr);
0224         if (ret) {
0225             dev_err(dev, "invalid slave address on node %pOF\n",
0226                 childnp);
0227             return -EINVAL;
0228         }
0229
0230         p2wi->slave_addr = slave_addr;
0231     }
0232
0233     p2wi->regs = devm_platform_ioremap_resource(pdev, 0);
0234     if (IS_ERR(p2wi->regs))
0235         return PTR_ERR(p2wi->regs);
0236
0237     strscpy(p2wi->adapter.name, pdev->name, sizeof(p2wi->adapter.name));
0238     irq = platform_get_irq(pdev, 0);
0239     if (irq < 0)
0240         return irq;
0241
0242     p2wi->clk = devm_clk_get(dev, NULL);
0243     if (IS_ERR(p2wi->clk)) {
0244         ret = PTR_ERR(p2wi->clk);
0245         dev_err(dev, "failed to retrieve clk: %d\n", ret);
0246         return ret;
0247     }
0248
0249     ret = clk_prepare_enable(p2wi->clk);
0250     if (ret) {
0251         dev_err(dev, "failed to enable clk: %d\n", ret);
0252         return ret;
0253     }
0254
0255     parent_clk_freq = clk_get_rate(p2wi->clk);
0256
0257     p2wi->rstc = devm_reset_control_get_exclusive(dev, NULL);
0258     if (IS_ERR(p2wi->rstc)) {
0259         ret = PTR_ERR(p2wi->rstc);
0260         dev_err(dev, "failed to retrieve reset controller: %d\n", ret);
0261         goto err_clk_disable;
0262     }
0263
0264     ret = reset_control_deassert(p2wi->rstc);
0265     if (ret) {
0266         dev_err(dev, "failed to deassert reset line: %d\n", ret);
0267         goto err_clk_disable;
0268     }
0269
0270     init_completion(&p2wi->complete);
0271     p2wi->adapter.dev.parent = dev;
0272     p2wi->adapter.algo = &p2wi_algo;
0273     p2wi->adapter.owner = THIS_MODULE;
0274     p2wi->adapter.dev.of_node = pdev->dev.of_node;
0275     platform_set_drvdata(pdev, p2wi);
0276     i2c_set_adapdata(&p2wi->adapter, p2wi);
0277
0278     ret = devm_request_irq(dev, irq, p2wi_interrupt, 0, pdev->name, p2wi);
0279     if (ret) {
0280         dev_err(dev, "can't register interrupt handler irq%d: %d\n",
0281             irq, ret);
0282         goto err_reset_assert;
0283     }
0284
0285     writel(P2WI_CTRL_SOFT_RST, p2wi->regs + P2WI_CTRL);
0286
0287     clk_div = parent_clk_freq / clk_freq;
0288     if (!clk_div) {
0289         dev_warn(dev,
0290              "clock-frequency is too high, setting it to %lu Hz\n",
0291              parent_clk_freq);
0292         clk_div = 1;
0293     } else if (clk_div > P2WI_CCR_MAX_CLK_DIV) {
0294         dev_warn(dev,
0295              "clock-frequency is too low, setting it to %lu Hz\n",
0296              parent_clk_freq / P2WI_CCR_MAX_CLK_DIV);
0297         clk_div = P2WI_CCR_MAX_CLK_DIV;
0298     }
0299
0300     writel(P2WI_CCR_SDA_OUT_DELAY(1) | P2WI_CCR_CLK_DIV(clk_div),
0301            p2wi->regs + P2WI_CCR);
0302
0303     ret = i2c_add_adapter(&p2wi->adapter);
0304     if (!ret)
0305         return 0;
0306
0307 err_reset_assert:
0308     reset_control_assert(p2wi->rstc);
0309
0310 err_clk_disable:
0311     clk_disable_unprepare(p2wi->clk);
0312
0313     return ret;
0314 }
0315
0316 static int p2wi_remove(struct platform_device *dev)
0317 {
0318     struct p2wi *p2wi = platform_get_drvdata(dev);
0319
0320     reset_control_assert(p2wi->rstc);
0321     clk_disable_unprepare(p2wi->clk);
0322     i2c_del_adapter(&p2wi->adapter);
0323
0324     return 0;
0325 }
0326
0327 static struct platform_driver p2wi_driver = {
0328     .probe  = p2wi_probe,
0329     .remove = p2wi_remove,
0330     .driver = {
0331         .name = "i2c-sunxi-p2wi",
0332         .of_match_table = p2wi_of_match_table,
0333     },
0334 };
0335 module_platform_driver(p2wi_driver);
0336
0337 MODULE_AUTHOR("Boris BREZILLON <boris.brezillon@free-electrons.com>");
0338 MODULE_DESCRIPTION("Allwinner P2WI driver");
0339 MODULE_LICENSE("GPL v2");