Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for STMicroelectronics STM32F7 I2C controller
0004  *
0005  * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
0006  * reference manual.
0007  * Please see below a link to the documentation:
0008  * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
0009  *
0010  * Copyright (C) M'boumba Cedric Madianga 2017
0011  * Copyright (C) STMicroelectronics 2017
0012  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
0013  *
0014  * This driver is based on i2c-stm32f4.c
0015  *
0016  */
0017 #include <linux/clk.h>
0018 #include <linux/delay.h>
0019 #include <linux/err.h>
0020 #include <linux/i2c.h>
0021 #include <linux/i2c-smbus.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/io.h>
0024 #include <linux/iopoll.h>
0025 #include <linux/mfd/syscon.h>
0026 #include <linux/module.h>
0027 #include <linux/of.h>
0028 #include <linux/of_address.h>
0029 #include <linux/of_platform.h>
0030 #include <linux/platform_device.h>
0031 #include <linux/pinctrl/consumer.h>
0032 #include <linux/pm_runtime.h>
0033 #include <linux/pm_wakeirq.h>
0034 #include <linux/regmap.h>
0035 #include <linux/reset.h>
0036 #include <linux/slab.h>
0037 
0038 #include "i2c-stm32.h"
0039 
0040 /* STM32F7 I2C registers */
0041 #define STM32F7_I2C_CR1             0x00
0042 #define STM32F7_I2C_CR2             0x04
0043 #define STM32F7_I2C_OAR1            0x08
0044 #define STM32F7_I2C_OAR2            0x0C
0045 #define STM32F7_I2C_PECR            0x20
0046 #define STM32F7_I2C_TIMINGR         0x10
0047 #define STM32F7_I2C_ISR             0x18
0048 #define STM32F7_I2C_ICR             0x1C
0049 #define STM32F7_I2C_RXDR            0x24
0050 #define STM32F7_I2C_TXDR            0x28
0051 
0052 /* STM32F7 I2C control 1 */
0053 #define STM32F7_I2C_CR1_PECEN           BIT(23)
0054 #define STM32F7_I2C_CR1_ALERTEN         BIT(22)
0055 #define STM32F7_I2C_CR1_SMBHEN          BIT(20)
0056 #define STM32F7_I2C_CR1_WUPEN           BIT(18)
0057 #define STM32F7_I2C_CR1_SBC         BIT(16)
0058 #define STM32F7_I2C_CR1_RXDMAEN         BIT(15)
0059 #define STM32F7_I2C_CR1_TXDMAEN         BIT(14)
0060 #define STM32F7_I2C_CR1_ANFOFF          BIT(12)
0061 #define STM32F7_I2C_CR1_DNF_MASK        GENMASK(11, 8)
0062 #define STM32F7_I2C_CR1_DNF(n)          (((n) & 0xf) << 8)
0063 #define STM32F7_I2C_CR1_ERRIE           BIT(7)
0064 #define STM32F7_I2C_CR1_TCIE            BIT(6)
0065 #define STM32F7_I2C_CR1_STOPIE          BIT(5)
0066 #define STM32F7_I2C_CR1_NACKIE          BIT(4)
0067 #define STM32F7_I2C_CR1_ADDRIE          BIT(3)
0068 #define STM32F7_I2C_CR1_RXIE            BIT(2)
0069 #define STM32F7_I2C_CR1_TXIE            BIT(1)
0070 #define STM32F7_I2C_CR1_PE          BIT(0)
0071 #define STM32F7_I2C_ALL_IRQ_MASK        (STM32F7_I2C_CR1_ERRIE \
0072                         | STM32F7_I2C_CR1_TCIE \
0073                         | STM32F7_I2C_CR1_STOPIE \
0074                         | STM32F7_I2C_CR1_NACKIE \
0075                         | STM32F7_I2C_CR1_RXIE \
0076                         | STM32F7_I2C_CR1_TXIE)
0077 #define STM32F7_I2C_XFER_IRQ_MASK       (STM32F7_I2C_CR1_TCIE \
0078                         | STM32F7_I2C_CR1_STOPIE \
0079                         | STM32F7_I2C_CR1_NACKIE \
0080                         | STM32F7_I2C_CR1_RXIE \
0081                         | STM32F7_I2C_CR1_TXIE)
0082 
0083 /* STM32F7 I2C control 2 */
0084 #define STM32F7_I2C_CR2_PECBYTE         BIT(26)
0085 #define STM32F7_I2C_CR2_RELOAD          BIT(24)
0086 #define STM32F7_I2C_CR2_NBYTES_MASK     GENMASK(23, 16)
0087 #define STM32F7_I2C_CR2_NBYTES(n)       (((n) & 0xff) << 16)
0088 #define STM32F7_I2C_CR2_NACK            BIT(15)
0089 #define STM32F7_I2C_CR2_STOP            BIT(14)
0090 #define STM32F7_I2C_CR2_START           BIT(13)
0091 #define STM32F7_I2C_CR2_HEAD10R         BIT(12)
0092 #define STM32F7_I2C_CR2_ADD10           BIT(11)
0093 #define STM32F7_I2C_CR2_RD_WRN          BIT(10)
0094 #define STM32F7_I2C_CR2_SADD10_MASK     GENMASK(9, 0)
0095 #define STM32F7_I2C_CR2_SADD10(n)       (((n) & \
0096                         STM32F7_I2C_CR2_SADD10_MASK))
0097 #define STM32F7_I2C_CR2_SADD7_MASK      GENMASK(7, 1)
0098 #define STM32F7_I2C_CR2_SADD7(n)        (((n) & 0x7f) << 1)
0099 
0100 /* STM32F7 I2C Own Address 1 */
0101 #define STM32F7_I2C_OAR1_OA1EN          BIT(15)
0102 #define STM32F7_I2C_OAR1_OA1MODE        BIT(10)
0103 #define STM32F7_I2C_OAR1_OA1_10_MASK        GENMASK(9, 0)
0104 #define STM32F7_I2C_OAR1_OA1_10(n)      (((n) & \
0105                         STM32F7_I2C_OAR1_OA1_10_MASK))
0106 #define STM32F7_I2C_OAR1_OA1_7_MASK     GENMASK(7, 1)
0107 #define STM32F7_I2C_OAR1_OA1_7(n)       (((n) & 0x7f) << 1)
0108 #define STM32F7_I2C_OAR1_MASK           (STM32F7_I2C_OAR1_OA1_7_MASK \
0109                         | STM32F7_I2C_OAR1_OA1_10_MASK \
0110                         | STM32F7_I2C_OAR1_OA1EN \
0111                         | STM32F7_I2C_OAR1_OA1MODE)
0112 
0113 /* STM32F7 I2C Own Address 2 */
0114 #define STM32F7_I2C_OAR2_OA2EN          BIT(15)
0115 #define STM32F7_I2C_OAR2_OA2MSK_MASK        GENMASK(10, 8)
0116 #define STM32F7_I2C_OAR2_OA2MSK(n)      (((n) & 0x7) << 8)
0117 #define STM32F7_I2C_OAR2_OA2_7_MASK     GENMASK(7, 1)
0118 #define STM32F7_I2C_OAR2_OA2_7(n)       (((n) & 0x7f) << 1)
0119 #define STM32F7_I2C_OAR2_MASK           (STM32F7_I2C_OAR2_OA2MSK_MASK \
0120                         | STM32F7_I2C_OAR2_OA2_7_MASK \
0121                         | STM32F7_I2C_OAR2_OA2EN)
0122 
0123 /* STM32F7 I2C Interrupt Status */
0124 #define STM32F7_I2C_ISR_ADDCODE_MASK        GENMASK(23, 17)
0125 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
0126                 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
0127 #define STM32F7_I2C_ISR_DIR         BIT(16)
0128 #define STM32F7_I2C_ISR_BUSY            BIT(15)
0129 #define STM32F7_I2C_ISR_ALERT           BIT(13)
0130 #define STM32F7_I2C_ISR_PECERR          BIT(11)
0131 #define STM32F7_I2C_ISR_ARLO            BIT(9)
0132 #define STM32F7_I2C_ISR_BERR            BIT(8)
0133 #define STM32F7_I2C_ISR_TCR         BIT(7)
0134 #define STM32F7_I2C_ISR_TC          BIT(6)
0135 #define STM32F7_I2C_ISR_STOPF           BIT(5)
0136 #define STM32F7_I2C_ISR_NACKF           BIT(4)
0137 #define STM32F7_I2C_ISR_ADDR            BIT(3)
0138 #define STM32F7_I2C_ISR_RXNE            BIT(2)
0139 #define STM32F7_I2C_ISR_TXIS            BIT(1)
0140 #define STM32F7_I2C_ISR_TXE         BIT(0)
0141 
0142 /* STM32F7 I2C Interrupt Clear */
0143 #define STM32F7_I2C_ICR_ALERTCF         BIT(13)
0144 #define STM32F7_I2C_ICR_PECCF           BIT(11)
0145 #define STM32F7_I2C_ICR_ARLOCF          BIT(9)
0146 #define STM32F7_I2C_ICR_BERRCF          BIT(8)
0147 #define STM32F7_I2C_ICR_STOPCF          BIT(5)
0148 #define STM32F7_I2C_ICR_NACKCF          BIT(4)
0149 #define STM32F7_I2C_ICR_ADDRCF          BIT(3)
0150 
0151 /* STM32F7 I2C Timing */
0152 #define STM32F7_I2C_TIMINGR_PRESC(n)        (((n) & 0xf) << 28)
0153 #define STM32F7_I2C_TIMINGR_SCLDEL(n)       (((n) & 0xf) << 20)
0154 #define STM32F7_I2C_TIMINGR_SDADEL(n)       (((n) & 0xf) << 16)
0155 #define STM32F7_I2C_TIMINGR_SCLH(n)     (((n) & 0xff) << 8)
0156 #define STM32F7_I2C_TIMINGR_SCLL(n)     ((n) & 0xff)
0157 
0158 #define STM32F7_I2C_MAX_LEN         0xff
0159 #define STM32F7_I2C_DMA_LEN_MIN         0x16
0160 enum {
0161     STM32F7_SLAVE_HOSTNOTIFY,
0162     STM32F7_SLAVE_7_10_BITS_ADDR,
0163     STM32F7_SLAVE_7_BITS_ADDR,
0164     STM32F7_I2C_MAX_SLAVE
0165 };
0166 
0167 #define STM32F7_I2C_DNF_DEFAULT         0
0168 #define STM32F7_I2C_DNF_MAX         15
0169 
0170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50  /* ns */
0171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
0172 
0173 #define STM32F7_I2C_RISE_TIME_DEFAULT       25  /* ns */
0174 #define STM32F7_I2C_FALL_TIME_DEFAULT       10  /* ns */
0175 
0176 #define STM32F7_PRESC_MAX           BIT(4)
0177 #define STM32F7_SCLDEL_MAX          BIT(4)
0178 #define STM32F7_SDADEL_MAX          BIT(4)
0179 #define STM32F7_SCLH_MAX            BIT(8)
0180 #define STM32F7_SCLL_MAX            BIT(8)
0181 
0182 #define STM32F7_AUTOSUSPEND_DELAY       (HZ / 100)
0183 
0184 /**
0185  * struct stm32f7_i2c_regs - i2c f7 registers backup
0186  * @cr1: Control register 1
0187  * @cr2: Control register 2
0188  * @oar1: Own address 1 register
0189  * @oar2: Own address 2 register
0190  * @tmgr: Timing register
0191  */
0192 struct stm32f7_i2c_regs {
0193     u32 cr1;
0194     u32 cr2;
0195     u32 oar1;
0196     u32 oar2;
0197     u32 tmgr;
0198 };
0199 
0200 /**
0201  * struct stm32f7_i2c_spec - private i2c specification timing
0202  * @rate: I2C bus speed (Hz)
0203  * @fall_max: Max fall time of both SDA and SCL signals (ns)
0204  * @rise_max: Max rise time of both SDA and SCL signals (ns)
0205  * @hddat_min: Min data hold time (ns)
0206  * @vddat_max: Max data valid time (ns)
0207  * @sudat_min: Min data setup time (ns)
0208  * @l_min: Min low period of the SCL clock (ns)
0209  * @h_min: Min high period of the SCL clock (ns)
0210  */
0211 struct stm32f7_i2c_spec {
0212     u32 rate;
0213     u32 fall_max;
0214     u32 rise_max;
0215     u32 hddat_min;
0216     u32 vddat_max;
0217     u32 sudat_min;
0218     u32 l_min;
0219     u32 h_min;
0220 };
0221 
0222 /**
0223  * struct stm32f7_i2c_setup - private I2C timing setup parameters
0224  * @speed_freq: I2C speed frequency  (Hz)
0225  * @clock_src: I2C clock source frequency (Hz)
0226  * @rise_time: Rise time (ns)
0227  * @fall_time: Fall time (ns)
0228  * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
0229  */
0230 struct stm32f7_i2c_setup {
0231     u32 speed_freq;
0232     u32 clock_src;
0233     u32 rise_time;
0234     u32 fall_time;
0235     u32 fmp_clr_offset;
0236 };
0237 
0238 /**
0239  * struct stm32f7_i2c_timings - private I2C output parameters
0240  * @node: List entry
0241  * @presc: Prescaler value
0242  * @scldel: Data setup time
0243  * @sdadel: Data hold time
0244  * @sclh: SCL high period (master mode)
0245  * @scll: SCL low period (master mode)
0246  */
0247 struct stm32f7_i2c_timings {
0248     struct list_head node;
0249     u8 presc;
0250     u8 scldel;
0251     u8 sdadel;
0252     u8 sclh;
0253     u8 scll;
0254 };
0255 
0256 /**
0257  * struct stm32f7_i2c_msg - client specific data
0258  * @addr: 8-bit or 10-bit slave addr, including r/w bit
0259  * @count: number of bytes to be transferred
0260  * @buf: data buffer
0261  * @result: result of the transfer
0262  * @stop: last I2C msg to be sent, i.e. STOP to be generated
0263  * @smbus: boolean to know if the I2C IP is used in SMBus mode
0264  * @size: type of SMBus protocol
0265  * @read_write: direction of SMBus protocol
0266  * SMBus block read and SMBus block write - block read process call protocols
0267  * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
0268  * contain a maximum of 32 bytes of data + byte command + byte count + PEC
0269  * This buffer has to be 32-bit aligned to be compliant with memory address
0270  * register in DMA mode.
0271  */
0272 struct stm32f7_i2c_msg {
0273     u16 addr;
0274     u32 count;
0275     u8 *buf;
0276     int result;
0277     bool stop;
0278     bool smbus;
0279     int size;
0280     char read_write;
0281     u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
0282 };
0283 
0284 /**
0285  * struct stm32f7_i2c_alert - SMBus alert specific data
0286  * @setup: platform data for the smbus_alert i2c client
0287  * @ara: I2C slave device used to respond to the SMBus Alert with Alert
0288  * Response Address
0289  */
0290 struct stm32f7_i2c_alert {
0291     struct i2c_smbus_alert_setup setup;
0292     struct i2c_client *ara;
0293 };
0294 
0295 /**
0296  * struct stm32f7_i2c_dev - private data of the controller
0297  * @adap: I2C adapter for this controller
0298  * @dev: device for this controller
0299  * @base: virtual memory area
0300  * @complete: completion of I2C message
0301  * @clk: hw i2c clock
0302  * @bus_rate: I2C clock frequency of the controller
0303  * @msg: Pointer to data to be written
0304  * @msg_num: number of I2C messages to be executed
0305  * @msg_id: message identifiant
0306  * @f7_msg: customized i2c msg for driver usage
0307  * @setup: I2C timing input setup
0308  * @timing: I2C computed timings
0309  * @slave: list of slave devices registered on the I2C bus
0310  * @slave_running: slave device currently used
0311  * @backup_regs: backup of i2c controller registers (for suspend/resume)
0312  * @slave_dir: transfer direction for the current slave device
0313  * @master_mode: boolean to know in which mode the I2C is running (master or
0314  * slave)
0315  * @dma: dma data
0316  * @use_dma: boolean to know if dma is used in the current transfer
0317  * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
0318  * @fmp_sreg: register address for setting Fast Mode Plus bits
0319  * @fmp_creg: register address for clearing Fast Mode Plus bits
0320  * @fmp_mask: mask for Fast Mode Plus bits in set register
0321  * @wakeup_src: boolean to know if the device is a wakeup source
0322  * @smbus_mode: states that the controller is configured in SMBus mode
0323  * @host_notify_client: SMBus host-notify client
0324  * @analog_filter: boolean to indicate enabling of the analog filter
0325  * @dnf_dt: value of digital filter requested via dt
0326  * @dnf: value of digital filter to apply
0327  * @alert: SMBus alert specific data
0328  */
0329 struct stm32f7_i2c_dev {
0330     struct i2c_adapter adap;
0331     struct device *dev;
0332     void __iomem *base;
0333     struct completion complete;
0334     struct clk *clk;
0335     unsigned int bus_rate;
0336     struct i2c_msg *msg;
0337     unsigned int msg_num;
0338     unsigned int msg_id;
0339     struct stm32f7_i2c_msg f7_msg;
0340     struct stm32f7_i2c_setup setup;
0341     struct stm32f7_i2c_timings timing;
0342     struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
0343     struct i2c_client *slave_running;
0344     struct stm32f7_i2c_regs backup_regs;
0345     u32 slave_dir;
0346     bool master_mode;
0347     struct stm32_i2c_dma *dma;
0348     bool use_dma;
0349     struct regmap *regmap;
0350     u32 fmp_sreg;
0351     u32 fmp_creg;
0352     u32 fmp_mask;
0353     bool wakeup_src;
0354     bool smbus_mode;
0355     struct i2c_client *host_notify_client;
0356     bool analog_filter;
0357     u32 dnf_dt;
0358     u32 dnf;
0359     struct stm32f7_i2c_alert *alert;
0360 };
0361 
0362 /*
0363  * All these values are coming from I2C Specification, Version 6.0, 4th of
0364  * April 2014.
0365  *
0366  * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
0367  * and Fast-mode Plus I2C-bus devices
0368  */
0369 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
0370     {
0371         .rate = I2C_MAX_STANDARD_MODE_FREQ,
0372         .fall_max = 300,
0373         .rise_max = 1000,
0374         .hddat_min = 0,
0375         .vddat_max = 3450,
0376         .sudat_min = 250,
0377         .l_min = 4700,
0378         .h_min = 4000,
0379     },
0380     {
0381         .rate = I2C_MAX_FAST_MODE_FREQ,
0382         .fall_max = 300,
0383         .rise_max = 300,
0384         .hddat_min = 0,
0385         .vddat_max = 900,
0386         .sudat_min = 100,
0387         .l_min = 1300,
0388         .h_min = 600,
0389     },
0390     {
0391         .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
0392         .fall_max = 100,
0393         .rise_max = 120,
0394         .hddat_min = 0,
0395         .vddat_max = 450,
0396         .sudat_min = 50,
0397         .l_min = 500,
0398         .h_min = 260,
0399     },
0400 };
0401 
0402 static const struct stm32f7_i2c_setup stm32f7_setup = {
0403     .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
0404     .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
0405 };
0406 
0407 static const struct stm32f7_i2c_setup stm32mp15_setup = {
0408     .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
0409     .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
0410     .fmp_clr_offset = 0x40,
0411 };
0412 
0413 static const struct stm32f7_i2c_setup stm32mp13_setup = {
0414     .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
0415     .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
0416     .fmp_clr_offset = 0x4,
0417 };
0418 
0419 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
0420 {
0421     writel_relaxed(readl_relaxed(reg) | mask, reg);
0422 }
0423 
0424 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
0425 {
0426     writel_relaxed(readl_relaxed(reg) & ~mask, reg);
0427 }
0428 
0429 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
0430 {
0431     stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
0432 }
0433 
0434 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
0435 {
0436     int i;
0437 
0438     for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
0439         if (rate <= stm32f7_i2c_specs[i].rate)
0440             return &stm32f7_i2c_specs[i];
0441 
0442     return ERR_PTR(-EINVAL);
0443 }
0444 
0445 #define RATE_MIN(rate)  ((rate) * 8 / 10)
0446 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
0447                       struct stm32f7_i2c_setup *setup,
0448                       struct stm32f7_i2c_timings *output)
0449 {
0450     struct stm32f7_i2c_spec *specs;
0451     u32 p_prev = STM32F7_PRESC_MAX;
0452     u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
0453                        setup->clock_src);
0454     u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
0455                        setup->speed_freq);
0456     u32 clk_error_prev = i2cbus;
0457     u32 tsync;
0458     u32 af_delay_min, af_delay_max;
0459     u32 dnf_delay;
0460     u32 clk_min, clk_max;
0461     int sdadel_min, sdadel_max;
0462     int scldel_min;
0463     struct stm32f7_i2c_timings *v, *_v, *s;
0464     struct list_head solutions;
0465     u16 p, l, a, h;
0466     int ret = 0;
0467 
0468     specs = stm32f7_get_specs(setup->speed_freq);
0469     if (specs == ERR_PTR(-EINVAL)) {
0470         dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
0471             setup->speed_freq);
0472         return -EINVAL;
0473     }
0474 
0475     if ((setup->rise_time > specs->rise_max) ||
0476         (setup->fall_time > specs->fall_max)) {
0477         dev_err(i2c_dev->dev,
0478             "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
0479             setup->rise_time, specs->rise_max,
0480             setup->fall_time, specs->fall_max);
0481         return -EINVAL;
0482     }
0483 
0484     i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
0485     if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
0486         dev_err(i2c_dev->dev,
0487             "DNF out of bound %d/%d\n",
0488             i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
0489         return -EINVAL;
0490     }
0491 
0492     /*  Analog and Digital Filters */
0493     af_delay_min =
0494         (i2c_dev->analog_filter ?
0495          STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
0496     af_delay_max =
0497         (i2c_dev->analog_filter ?
0498          STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
0499     dnf_delay = i2c_dev->dnf * i2cclk;
0500 
0501     sdadel_min = specs->hddat_min + setup->fall_time -
0502         af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
0503 
0504     sdadel_max = specs->vddat_max - setup->rise_time -
0505         af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
0506 
0507     scldel_min = setup->rise_time + specs->sudat_min;
0508 
0509     if (sdadel_min < 0)
0510         sdadel_min = 0;
0511     if (sdadel_max < 0)
0512         sdadel_max = 0;
0513 
0514     dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
0515         sdadel_min, sdadel_max, scldel_min);
0516 
0517     INIT_LIST_HEAD(&solutions);
0518     /* Compute possible values for PRESC, SCLDEL and SDADEL */
0519     for (p = 0; p < STM32F7_PRESC_MAX; p++) {
0520         for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
0521             u32 scldel = (l + 1) * (p + 1) * i2cclk;
0522 
0523             if (scldel < scldel_min)
0524                 continue;
0525 
0526             for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
0527                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
0528 
0529                 if (((sdadel >= sdadel_min) &&
0530                      (sdadel <= sdadel_max)) &&
0531                     (p != p_prev)) {
0532                     v = kmalloc(sizeof(*v), GFP_KERNEL);
0533                     if (!v) {
0534                         ret = -ENOMEM;
0535                         goto exit;
0536                     }
0537 
0538                     v->presc = p;
0539                     v->scldel = l;
0540                     v->sdadel = a;
0541                     p_prev = p;
0542 
0543                     list_add_tail(&v->node,
0544                               &solutions);
0545                     break;
0546                 }
0547             }
0548 
0549             if (p_prev == p)
0550                 break;
0551         }
0552     }
0553 
0554     if (list_empty(&solutions)) {
0555         dev_err(i2c_dev->dev, "no Prescaler solution\n");
0556         ret = -EPERM;
0557         goto exit;
0558     }
0559 
0560     tsync = af_delay_min + dnf_delay + (2 * i2cclk);
0561     s = NULL;
0562     clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
0563     clk_min = NSEC_PER_SEC / setup->speed_freq;
0564 
0565     /*
0566      * Among Prescaler possibilities discovered above figures out SCL Low
0567      * and High Period. Provided:
0568      * - SCL Low Period has to be higher than SCL Clock Low Period
0569      *   defined by I2C Specification. I2C Clock has to be lower than
0570      *   (SCL Low Period - Analog/Digital filters) / 4.
0571      * - SCL High Period has to be lower than SCL Clock High Period
0572      *   defined by I2C Specification
0573      * - I2C Clock has to be lower than SCL High Period
0574      */
0575     list_for_each_entry(v, &solutions, node) {
0576         u32 prescaler = (v->presc + 1) * i2cclk;
0577 
0578         for (l = 0; l < STM32F7_SCLL_MAX; l++) {
0579             u32 tscl_l = (l + 1) * prescaler + tsync;
0580 
0581             if ((tscl_l < specs->l_min) ||
0582                 (i2cclk >=
0583                  ((tscl_l - af_delay_min - dnf_delay) / 4))) {
0584                 continue;
0585             }
0586 
0587             for (h = 0; h < STM32F7_SCLH_MAX; h++) {
0588                 u32 tscl_h = (h + 1) * prescaler + tsync;
0589                 u32 tscl = tscl_l + tscl_h +
0590                     setup->rise_time + setup->fall_time;
0591 
0592                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
0593                     (tscl_h >= specs->h_min) &&
0594                     (i2cclk < tscl_h)) {
0595                     int clk_error = tscl - i2cbus;
0596 
0597                     if (clk_error < 0)
0598                         clk_error = -clk_error;
0599 
0600                     if (clk_error < clk_error_prev) {
0601                         clk_error_prev = clk_error;
0602                         v->scll = l;
0603                         v->sclh = h;
0604                         s = v;
0605                     }
0606                 }
0607             }
0608         }
0609     }
0610 
0611     if (!s) {
0612         dev_err(i2c_dev->dev, "no solution at all\n");
0613         ret = -EPERM;
0614         goto exit;
0615     }
0616 
0617     output->presc = s->presc;
0618     output->scldel = s->scldel;
0619     output->sdadel = s->sdadel;
0620     output->scll = s->scll;
0621     output->sclh = s->sclh;
0622 
0623     dev_dbg(i2c_dev->dev,
0624         "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
0625         output->presc,
0626         output->scldel, output->sdadel,
0627         output->scll, output->sclh);
0628 
0629 exit:
0630     /* Release list and memory */
0631     list_for_each_entry_safe(v, _v, &solutions, node) {
0632         list_del(&v->node);
0633         kfree(v);
0634     }
0635 
0636     return ret;
0637 }
0638 
0639 static u32 stm32f7_get_lower_rate(u32 rate)
0640 {
0641     int i = ARRAY_SIZE(stm32f7_i2c_specs);
0642 
0643     while (--i)
0644         if (stm32f7_i2c_specs[i].rate < rate)
0645             break;
0646 
0647     return stm32f7_i2c_specs[i].rate;
0648 }
0649 
0650 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
0651                     struct stm32f7_i2c_setup *setup)
0652 {
0653     struct i2c_timings timings, *t = &timings;
0654     int ret = 0;
0655 
0656     t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
0657     t->scl_rise_ns = i2c_dev->setup.rise_time;
0658     t->scl_fall_ns = i2c_dev->setup.fall_time;
0659 
0660     i2c_parse_fw_timings(i2c_dev->dev, t, false);
0661 
0662     if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
0663         dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
0664             t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
0665         return -EINVAL;
0666     }
0667 
0668     setup->speed_freq = t->bus_freq_hz;
0669     i2c_dev->setup.rise_time = t->scl_rise_ns;
0670     i2c_dev->setup.fall_time = t->scl_fall_ns;
0671     i2c_dev->dnf_dt = t->digital_filter_width_ns;
0672     setup->clock_src = clk_get_rate(i2c_dev->clk);
0673 
0674     if (!setup->clock_src) {
0675         dev_err(i2c_dev->dev, "clock rate is 0\n");
0676         return -EINVAL;
0677     }
0678 
0679     if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
0680         i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
0681 
0682     do {
0683         ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
0684                          &i2c_dev->timing);
0685         if (ret) {
0686             dev_err(i2c_dev->dev,
0687                 "failed to compute I2C timings.\n");
0688             if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
0689                 break;
0690             setup->speed_freq =
0691                 stm32f7_get_lower_rate(setup->speed_freq);
0692             dev_warn(i2c_dev->dev,
0693                  "downgrade I2C Speed Freq to (%i)\n",
0694                  setup->speed_freq);
0695         }
0696     } while (ret);
0697 
0698     if (ret) {
0699         dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
0700         return ret;
0701     }
0702 
0703     i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
0704                                "i2c-analog-filter");
0705 
0706     dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
0707         setup->speed_freq, setup->clock_src);
0708     dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
0709         setup->rise_time, setup->fall_time);
0710     dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
0711         (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf);
0712 
0713     i2c_dev->bus_rate = setup->speed_freq;
0714 
0715     return 0;
0716 }
0717 
0718 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
0719 {
0720     void __iomem *base = i2c_dev->base;
0721     u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
0722 
0723     stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
0724 }
0725 
0726 static void stm32f7_i2c_dma_callback(void *arg)
0727 {
0728     struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
0729     struct stm32_i2c_dma *dma = i2c_dev->dma;
0730     struct device *dev = dma->chan_using->device->dev;
0731 
0732     stm32f7_i2c_disable_dma_req(i2c_dev);
0733     dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
0734     complete(&dma->dma_complete);
0735 }
0736 
0737 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
0738 {
0739     struct stm32f7_i2c_timings *t = &i2c_dev->timing;
0740     u32 timing = 0;
0741 
0742     /* Timing settings */
0743     timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
0744     timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
0745     timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
0746     timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
0747     timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
0748     writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
0749 
0750     /* Configure the Analog Filter */
0751     if (i2c_dev->analog_filter)
0752         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
0753                      STM32F7_I2C_CR1_ANFOFF);
0754     else
0755         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
0756                      STM32F7_I2C_CR1_ANFOFF);
0757 
0758     /* Program the Digital Filter */
0759     stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
0760                  STM32F7_I2C_CR1_DNF_MASK);
0761     stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
0762                  STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
0763 
0764     stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
0765                  STM32F7_I2C_CR1_PE);
0766 }
0767 
0768 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
0769 {
0770     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
0771     void __iomem *base = i2c_dev->base;
0772 
0773     if (f7_msg->count) {
0774         writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
0775         f7_msg->count--;
0776     }
0777 }
0778 
0779 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
0780 {
0781     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
0782     void __iomem *base = i2c_dev->base;
0783 
0784     if (f7_msg->count) {
0785         *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
0786         f7_msg->count--;
0787     } else {
0788         /* Flush RX buffer has no data is expected */
0789         readb_relaxed(base + STM32F7_I2C_RXDR);
0790     }
0791 }
0792 
0793 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
0794 {
0795     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
0796     u32 cr2;
0797 
0798     if (i2c_dev->use_dma)
0799         f7_msg->count -= STM32F7_I2C_MAX_LEN;
0800 
0801     cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
0802 
0803     cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
0804     if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
0805         cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
0806     } else {
0807         cr2 &= ~STM32F7_I2C_CR2_RELOAD;
0808         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
0809     }
0810 
0811     writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
0812 }
0813 
0814 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
0815 {
0816     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
0817     u32 cr2;
0818     u8 *val;
0819 
0820     /*
0821      * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
0822      * data received inform us how many data will follow.
0823      */
0824     stm32f7_i2c_read_rx_data(i2c_dev);
0825 
0826     /*
0827      * Update NBYTES with the value read to continue the transfer
0828      */
0829     val = f7_msg->buf - sizeof(u8);
0830     f7_msg->count = *val;
0831     cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
0832     cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
0833     cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
0834     writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
0835 }
0836 
0837 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
0838 {
0839     struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
0840 
0841     stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
0842                  STM32F7_I2C_CR1_PE);
0843 
0844     stm32f7_i2c_hw_config(i2c_dev);
0845 }
0846 
0847 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
0848 {
0849     u32 status;
0850     int ret;
0851 
0852     ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
0853                      status,
0854                      !(status & STM32F7_I2C_ISR_BUSY),
0855                      10, 1000);
0856     if (!ret)
0857         return 0;
0858 
0859     stm32f7_i2c_release_bus(&i2c_dev->adap);
0860 
0861     return -EBUSY;
0862 }
0863 
0864 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
0865                  struct i2c_msg *msg)
0866 {
0867     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
0868     void __iomem *base = i2c_dev->base;
0869     u32 cr1, cr2;
0870     int ret;
0871 
0872     f7_msg->addr = msg->addr;
0873     f7_msg->buf = msg->buf;
0874     f7_msg->count = msg->len;
0875     f7_msg->result = 0;
0876     f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
0877 
0878     reinit_completion(&i2c_dev->complete);
0879 
0880     cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
0881     cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
0882 
0883     /* Set transfer direction */
0884     cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
0885     if (msg->flags & I2C_M_RD)
0886         cr2 |= STM32F7_I2C_CR2_RD_WRN;
0887 
0888     /* Set slave address */
0889     cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
0890     if (msg->flags & I2C_M_TEN) {
0891         cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
0892         cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
0893         cr2 |= STM32F7_I2C_CR2_ADD10;
0894     } else {
0895         cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
0896         cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
0897     }
0898 
0899     /* Set nb bytes to transfer and reload if needed */
0900     cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
0901     if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
0902         cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
0903         cr2 |= STM32F7_I2C_CR2_RELOAD;
0904     } else {
0905         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
0906     }
0907 
0908     /* Enable NACK, STOP, error and transfer complete interrupts */
0909     cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
0910         STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
0911 
0912     /* Clear DMA req and TX/RX interrupt */
0913     cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
0914             STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
0915 
0916     /* Configure DMA or enable RX/TX interrupt */
0917     i2c_dev->use_dma = false;
0918     if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
0919         ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
0920                           msg->flags & I2C_M_RD,
0921                           f7_msg->count, f7_msg->buf,
0922                           stm32f7_i2c_dma_callback,
0923                           i2c_dev);
0924         if (!ret)
0925             i2c_dev->use_dma = true;
0926         else
0927             dev_warn(i2c_dev->dev, "can't use DMA\n");
0928     }
0929 
0930     if (!i2c_dev->use_dma) {
0931         if (msg->flags & I2C_M_RD)
0932             cr1 |= STM32F7_I2C_CR1_RXIE;
0933         else
0934             cr1 |= STM32F7_I2C_CR1_TXIE;
0935     } else {
0936         if (msg->flags & I2C_M_RD)
0937             cr1 |= STM32F7_I2C_CR1_RXDMAEN;
0938         else
0939             cr1 |= STM32F7_I2C_CR1_TXDMAEN;
0940     }
0941 
0942     /* Configure Start/Repeated Start */
0943     cr2 |= STM32F7_I2C_CR2_START;
0944 
0945     i2c_dev->master_mode = true;
0946 
0947     /* Write configurations registers */
0948     writel_relaxed(cr1, base + STM32F7_I2C_CR1);
0949     writel_relaxed(cr2, base + STM32F7_I2C_CR2);
0950 }
0951 
0952 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
0953                       unsigned short flags, u8 command,
0954                       union i2c_smbus_data *data)
0955 {
0956     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
0957     struct device *dev = i2c_dev->dev;
0958     void __iomem *base = i2c_dev->base;
0959     u32 cr1, cr2;
0960     int i, ret;
0961 
0962     f7_msg->result = 0;
0963     reinit_completion(&i2c_dev->complete);
0964 
0965     cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
0966     cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
0967 
0968     /* Set transfer direction */
0969     cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
0970     if (f7_msg->read_write)
0971         cr2 |= STM32F7_I2C_CR2_RD_WRN;
0972 
0973     /* Set slave address */
0974     cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
0975     cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
0976 
0977     f7_msg->smbus_buf[0] = command;
0978     switch (f7_msg->size) {
0979     case I2C_SMBUS_QUICK:
0980         f7_msg->stop = true;
0981         f7_msg->count = 0;
0982         break;
0983     case I2C_SMBUS_BYTE:
0984         f7_msg->stop = true;
0985         f7_msg->count = 1;
0986         break;
0987     case I2C_SMBUS_BYTE_DATA:
0988         if (f7_msg->read_write) {
0989             f7_msg->stop = false;
0990             f7_msg->count = 1;
0991             cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
0992         } else {
0993             f7_msg->stop = true;
0994             f7_msg->count = 2;
0995             f7_msg->smbus_buf[1] = data->byte;
0996         }
0997         break;
0998     case I2C_SMBUS_WORD_DATA:
0999         if (f7_msg->read_write) {
1000             f7_msg->stop = false;
1001             f7_msg->count = 1;
1002             cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1003         } else {
1004             f7_msg->stop = true;
1005             f7_msg->count = 3;
1006             f7_msg->smbus_buf[1] = data->word & 0xff;
1007             f7_msg->smbus_buf[2] = data->word >> 8;
1008         }
1009         break;
1010     case I2C_SMBUS_BLOCK_DATA:
1011         if (f7_msg->read_write) {
1012             f7_msg->stop = false;
1013             f7_msg->count = 1;
1014             cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1015         } else {
1016             f7_msg->stop = true;
1017             if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1018                 !data->block[0]) {
1019                 dev_err(dev, "Invalid block write size %d\n",
1020                     data->block[0]);
1021                 return -EINVAL;
1022             }
1023             f7_msg->count = data->block[0] + 2;
1024             for (i = 1; i < f7_msg->count; i++)
1025                 f7_msg->smbus_buf[i] = data->block[i - 1];
1026         }
1027         break;
1028     case I2C_SMBUS_PROC_CALL:
1029         f7_msg->stop = false;
1030         f7_msg->count = 3;
1031         f7_msg->smbus_buf[1] = data->word & 0xff;
1032         f7_msg->smbus_buf[2] = data->word >> 8;
1033         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1034         f7_msg->read_write = I2C_SMBUS_READ;
1035         break;
1036     case I2C_SMBUS_BLOCK_PROC_CALL:
1037         f7_msg->stop = false;
1038         if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1039             dev_err(dev, "Invalid block write size %d\n",
1040                 data->block[0]);
1041             return -EINVAL;
1042         }
1043         f7_msg->count = data->block[0] + 2;
1044         for (i = 1; i < f7_msg->count; i++)
1045             f7_msg->smbus_buf[i] = data->block[i - 1];
1046         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1047         f7_msg->read_write = I2C_SMBUS_READ;
1048         break;
1049     case I2C_SMBUS_I2C_BLOCK_DATA:
1050         /* Rely on emulated i2c transfer (through master_xfer) */
1051         return -EOPNOTSUPP;
1052     default:
1053         dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1054         return -EOPNOTSUPP;
1055     }
1056 
1057     f7_msg->buf = f7_msg->smbus_buf;
1058 
1059     /* Configure PEC */
1060     if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1061         cr1 |= STM32F7_I2C_CR1_PECEN;
1062         cr2 |= STM32F7_I2C_CR2_PECBYTE;
1063         if (!f7_msg->read_write)
1064             f7_msg->count++;
1065     } else {
1066         cr1 &= ~STM32F7_I2C_CR1_PECEN;
1067         cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1068     }
1069 
1070     /* Set number of bytes to be transferred */
1071     cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1072     cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1073 
1074     /* Enable NACK, STOP, error and transfer complete interrupts */
1075     cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1076         STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1077 
1078     /* Clear DMA req and TX/RX interrupt */
1079     cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1080             STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1081 
1082     /* Configure DMA or enable RX/TX interrupt */
1083     i2c_dev->use_dma = false;
1084     if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1085         ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1086                           cr2 & STM32F7_I2C_CR2_RD_WRN,
1087                           f7_msg->count, f7_msg->buf,
1088                           stm32f7_i2c_dma_callback,
1089                           i2c_dev);
1090         if (!ret)
1091             i2c_dev->use_dma = true;
1092         else
1093             dev_warn(i2c_dev->dev, "can't use DMA\n");
1094     }
1095 
1096     if (!i2c_dev->use_dma) {
1097         if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1098             cr1 |= STM32F7_I2C_CR1_RXIE;
1099         else
1100             cr1 |= STM32F7_I2C_CR1_TXIE;
1101     } else {
1102         if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1103             cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1104         else
1105             cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1106     }
1107 
1108     /* Set Start bit */
1109     cr2 |= STM32F7_I2C_CR2_START;
1110 
1111     i2c_dev->master_mode = true;
1112 
1113     /* Write configurations registers */
1114     writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1115     writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1116 
1117     return 0;
1118 }
1119 
1120 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1121 {
1122     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1123     void __iomem *base = i2c_dev->base;
1124     u32 cr1, cr2;
1125     int ret;
1126 
1127     cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1128     cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1129 
1130     /* Set transfer direction */
1131     cr2 |= STM32F7_I2C_CR2_RD_WRN;
1132 
1133     switch (f7_msg->size) {
1134     case I2C_SMBUS_BYTE_DATA:
1135         f7_msg->count = 1;
1136         break;
1137     case I2C_SMBUS_WORD_DATA:
1138     case I2C_SMBUS_PROC_CALL:
1139         f7_msg->count = 2;
1140         break;
1141     case I2C_SMBUS_BLOCK_DATA:
1142     case I2C_SMBUS_BLOCK_PROC_CALL:
1143         f7_msg->count = 1;
1144         cr2 |= STM32F7_I2C_CR2_RELOAD;
1145         break;
1146     }
1147 
1148     f7_msg->buf = f7_msg->smbus_buf;
1149     f7_msg->stop = true;
1150 
1151     /* Add one byte for PEC if needed */
1152     if (cr1 & STM32F7_I2C_CR1_PECEN)
1153         f7_msg->count++;
1154 
1155     /* Set number of bytes to be transferred */
1156     cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1157     cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1158 
1159     /*
1160      * Configure RX/TX interrupt:
1161      */
1162     cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1163     cr1 |= STM32F7_I2C_CR1_RXIE;
1164 
1165     /*
1166      * Configure DMA or enable RX/TX interrupt:
1167      * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1168      * dma as we don't know in advance how many data will be received
1169      */
1170     cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1171          STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1172 
1173     i2c_dev->use_dma = false;
1174     if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1175         f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1176         f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1177         ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1178                           cr2 & STM32F7_I2C_CR2_RD_WRN,
1179                           f7_msg->count, f7_msg->buf,
1180                           stm32f7_i2c_dma_callback,
1181                           i2c_dev);
1182 
1183         if (!ret)
1184             i2c_dev->use_dma = true;
1185         else
1186             dev_warn(i2c_dev->dev, "can't use DMA\n");
1187     }
1188 
1189     if (!i2c_dev->use_dma)
1190         cr1 |= STM32F7_I2C_CR1_RXIE;
1191     else
1192         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1193 
1194     /* Configure Repeated Start */
1195     cr2 |= STM32F7_I2C_CR2_START;
1196 
1197     /* Write configurations registers */
1198     writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1199     writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1200 }
1201 
1202 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1203 {
1204     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1205     u8 count, internal_pec, received_pec;
1206 
1207     internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1208 
1209     switch (f7_msg->size) {
1210     case I2C_SMBUS_BYTE:
1211     case I2C_SMBUS_BYTE_DATA:
1212         received_pec = f7_msg->smbus_buf[1];
1213         break;
1214     case I2C_SMBUS_WORD_DATA:
1215     case I2C_SMBUS_PROC_CALL:
1216         received_pec = f7_msg->smbus_buf[2];
1217         break;
1218     case I2C_SMBUS_BLOCK_DATA:
1219     case I2C_SMBUS_BLOCK_PROC_CALL:
1220         count = f7_msg->smbus_buf[0];
1221         received_pec = f7_msg->smbus_buf[count];
1222         break;
1223     default:
1224         dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1225         return -EINVAL;
1226     }
1227 
1228     if (internal_pec != received_pec) {
1229         dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1230             internal_pec, received_pec);
1231         return -EBADMSG;
1232     }
1233 
1234     return 0;
1235 }
1236 
1237 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1238 {
1239     u32 addr;
1240 
1241     if (!slave)
1242         return false;
1243 
1244     if (slave->flags & I2C_CLIENT_TEN) {
1245         /*
1246          * For 10-bit addr, addcode = 11110XY with
1247          * X = Bit 9 of slave address
1248          * Y = Bit 8 of slave address
1249          */
1250         addr = slave->addr >> 8;
1251         addr |= 0x78;
1252         if (addr == addcode)
1253             return true;
1254     } else {
1255         addr = slave->addr & 0x7f;
1256         if (addr == addcode)
1257             return true;
1258     }
1259 
1260     return false;
1261 }
1262 
1263 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1264 {
1265     struct i2c_client *slave = i2c_dev->slave_running;
1266     void __iomem *base = i2c_dev->base;
1267     u32 mask;
1268     u8 value = 0;
1269 
1270     if (i2c_dev->slave_dir) {
1271         /* Notify i2c slave that new read transfer is starting */
1272         i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1273 
1274         /*
1275          * Disable slave TX config in case of I2C combined message
1276          * (I2C Write followed by I2C Read)
1277          */
1278         mask = STM32F7_I2C_CR2_RELOAD;
1279         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1280         mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1281                STM32F7_I2C_CR1_TCIE;
1282         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1283 
1284         /* Enable TX empty, STOP, NACK interrupts */
1285         mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1286             STM32F7_I2C_CR1_TXIE;
1287         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1288 
1289         /* Write 1st data byte */
1290         writel_relaxed(value, base + STM32F7_I2C_TXDR);
1291     } else {
1292         /* Notify i2c slave that new write transfer is starting */
1293         i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1294 
1295         /* Set reload mode to be able to ACK/NACK each received byte */
1296         mask = STM32F7_I2C_CR2_RELOAD;
1297         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1298 
1299         /*
1300          * Set STOP, NACK, RX empty and transfer complete interrupts.*
1301          * Set Slave Byte Control to be able to ACK/NACK each data
1302          * byte received
1303          */
1304         mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1305             STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1306             STM32F7_I2C_CR1_TCIE;
1307         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1308     }
1309 }
1310 
1311 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1312 {
1313     void __iomem *base = i2c_dev->base;
1314     u32 isr, addcode, dir, mask;
1315     int i;
1316 
1317     isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1318     addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1319     dir = isr & STM32F7_I2C_ISR_DIR;
1320 
1321     for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1322         if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1323             i2c_dev->slave_running = i2c_dev->slave[i];
1324             i2c_dev->slave_dir = dir;
1325 
1326             /* Start I2C slave processing */
1327             stm32f7_i2c_slave_start(i2c_dev);
1328 
1329             /* Clear ADDR flag */
1330             mask = STM32F7_I2C_ICR_ADDRCF;
1331             writel_relaxed(mask, base + STM32F7_I2C_ICR);
1332             break;
1333         }
1334     }
1335 }
1336 
1337 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1338                     struct i2c_client *slave, int *id)
1339 {
1340     int i;
1341 
1342     for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1343         if (i2c_dev->slave[i] == slave) {
1344             *id = i;
1345             return 0;
1346         }
1347     }
1348 
1349     dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1350 
1351     return -ENODEV;
1352 }
1353 
1354 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1355                      struct i2c_client *slave, int *id)
1356 {
1357     struct device *dev = i2c_dev->dev;
1358     int i;
1359 
1360     /*
1361      * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1362      * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1363      * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1364      */
1365     if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1366         if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1367             goto fail;
1368         *id = STM32F7_SLAVE_HOSTNOTIFY;
1369         return 0;
1370     }
1371 
1372     for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1373         if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1374             (slave->flags & I2C_CLIENT_TEN))
1375             continue;
1376         if (!i2c_dev->slave[i]) {
1377             *id = i;
1378             return 0;
1379         }
1380     }
1381 
1382 fail:
1383     dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1384 
1385     return -EINVAL;
1386 }
1387 
1388 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1389 {
1390     int i;
1391 
1392     for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1393         if (i2c_dev->slave[i])
1394             return true;
1395     }
1396 
1397     return false;
1398 }
1399 
1400 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1401 {
1402     int i, busy;
1403 
1404     busy = 0;
1405     for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1406         if (i2c_dev->slave[i])
1407             busy++;
1408     }
1409 
1410     return i == busy;
1411 }
1412 
1413 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1414 {
1415     void __iomem *base = i2c_dev->base;
1416     u32 cr2, status, mask;
1417     u8 val;
1418     int ret;
1419 
1420     status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1421 
1422     /* Slave transmitter mode */
1423     if (status & STM32F7_I2C_ISR_TXIS) {
1424         i2c_slave_event(i2c_dev->slave_running,
1425                 I2C_SLAVE_READ_PROCESSED,
1426                 &val);
1427 
1428         /* Write data byte */
1429         writel_relaxed(val, base + STM32F7_I2C_TXDR);
1430     }
1431 
1432     /* Transfer Complete Reload for Slave receiver mode */
1433     if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1434         /*
1435          * Read data byte then set NBYTES to receive next byte or NACK
1436          * the current received byte
1437          */
1438         val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1439         ret = i2c_slave_event(i2c_dev->slave_running,
1440                       I2C_SLAVE_WRITE_RECEIVED,
1441                       &val);
1442         if (!ret) {
1443             cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1444             cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1445             writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1446         } else {
1447             mask = STM32F7_I2C_CR2_NACK;
1448             stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1449         }
1450     }
1451 
1452     /* NACK received */
1453     if (status & STM32F7_I2C_ISR_NACKF) {
1454         dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1455         writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1456     }
1457 
1458     /* STOP received */
1459     if (status & STM32F7_I2C_ISR_STOPF) {
1460         /* Disable interrupts */
1461         stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1462 
1463         if (i2c_dev->slave_dir) {
1464             /*
1465              * Flush TX buffer in order to not used the byte in
1466              * TXDR for the next transfer
1467              */
1468             mask = STM32F7_I2C_ISR_TXE;
1469             stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1470         }
1471 
1472         /* Clear STOP flag */
1473         writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1474 
1475         /* Notify i2c slave that a STOP flag has been detected */
1476         i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1477 
1478         i2c_dev->slave_running = NULL;
1479     }
1480 
1481     /* Address match received */
1482     if (status & STM32F7_I2C_ISR_ADDR)
1483         stm32f7_i2c_slave_addr(i2c_dev);
1484 
1485     return IRQ_HANDLED;
1486 }
1487 
1488 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1489 {
1490     struct stm32f7_i2c_dev *i2c_dev = data;
1491     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1492     struct stm32_i2c_dma *dma = i2c_dev->dma;
1493     void __iomem *base = i2c_dev->base;
1494     u32 status, mask;
1495     int ret = IRQ_HANDLED;
1496 
1497     /* Check if the interrupt if for a slave device */
1498     if (!i2c_dev->master_mode) {
1499         ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1500         return ret;
1501     }
1502 
1503     status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1504 
1505     /* Tx empty */
1506     if (status & STM32F7_I2C_ISR_TXIS)
1507         stm32f7_i2c_write_tx_data(i2c_dev);
1508 
1509     /* RX not empty */
1510     if (status & STM32F7_I2C_ISR_RXNE)
1511         stm32f7_i2c_read_rx_data(i2c_dev);
1512 
1513     /* NACK received */
1514     if (status & STM32F7_I2C_ISR_NACKF) {
1515         dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1516             __func__, f7_msg->addr);
1517         writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1518         if (i2c_dev->use_dma) {
1519             stm32f7_i2c_disable_dma_req(i2c_dev);
1520             dmaengine_terminate_async(dma->chan_using);
1521         }
1522         f7_msg->result = -ENXIO;
1523     }
1524 
1525     /* STOP detection flag */
1526     if (status & STM32F7_I2C_ISR_STOPF) {
1527         /* Disable interrupts */
1528         if (stm32f7_i2c_is_slave_registered(i2c_dev))
1529             mask = STM32F7_I2C_XFER_IRQ_MASK;
1530         else
1531             mask = STM32F7_I2C_ALL_IRQ_MASK;
1532         stm32f7_i2c_disable_irq(i2c_dev, mask);
1533 
1534         /* Clear STOP flag */
1535         writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1536 
1537         if (i2c_dev->use_dma && !f7_msg->result) {
1538             ret = IRQ_WAKE_THREAD;
1539         } else {
1540             i2c_dev->master_mode = false;
1541             complete(&i2c_dev->complete);
1542         }
1543     }
1544 
1545     /* Transfer complete */
1546     if (status & STM32F7_I2C_ISR_TC) {
1547         if (f7_msg->stop) {
1548             mask = STM32F7_I2C_CR2_STOP;
1549             stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1550         } else if (i2c_dev->use_dma && !f7_msg->result) {
1551             ret = IRQ_WAKE_THREAD;
1552         } else if (f7_msg->smbus) {
1553             stm32f7_i2c_smbus_rep_start(i2c_dev);
1554         } else {
1555             i2c_dev->msg_id++;
1556             i2c_dev->msg++;
1557             stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1558         }
1559     }
1560 
1561     if (status & STM32F7_I2C_ISR_TCR) {
1562         if (f7_msg->smbus)
1563             stm32f7_i2c_smbus_reload(i2c_dev);
1564         else
1565             stm32f7_i2c_reload(i2c_dev);
1566     }
1567 
1568     return ret;
1569 }
1570 
1571 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1572 {
1573     struct stm32f7_i2c_dev *i2c_dev = data;
1574     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1575     struct stm32_i2c_dma *dma = i2c_dev->dma;
1576     u32 status;
1577     int ret;
1578 
1579     /*
1580      * Wait for dma transfer completion before sending next message or
1581      * notity the end of xfer to the client
1582      */
1583     ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1584     if (!ret) {
1585         dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1586         stm32f7_i2c_disable_dma_req(i2c_dev);
1587         dmaengine_terminate_async(dma->chan_using);
1588         f7_msg->result = -ETIMEDOUT;
1589     }
1590 
1591     status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1592 
1593     if (status & STM32F7_I2C_ISR_TC) {
1594         if (f7_msg->smbus) {
1595             stm32f7_i2c_smbus_rep_start(i2c_dev);
1596         } else {
1597             i2c_dev->msg_id++;
1598             i2c_dev->msg++;
1599             stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1600         }
1601     } else {
1602         i2c_dev->master_mode = false;
1603         complete(&i2c_dev->complete);
1604     }
1605 
1606     return IRQ_HANDLED;
1607 }
1608 
1609 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1610 {
1611     struct stm32f7_i2c_dev *i2c_dev = data;
1612     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1613     void __iomem *base = i2c_dev->base;
1614     struct device *dev = i2c_dev->dev;
1615     struct stm32_i2c_dma *dma = i2c_dev->dma;
1616     u32 status;
1617 
1618     status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1619 
1620     /* Bus error */
1621     if (status & STM32F7_I2C_ISR_BERR) {
1622         dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n",
1623             __func__, f7_msg->addr);
1624         writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1625         stm32f7_i2c_release_bus(&i2c_dev->adap);
1626         f7_msg->result = -EIO;
1627     }
1628 
1629     /* Arbitration loss */
1630     if (status & STM32F7_I2C_ISR_ARLO) {
1631         dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n",
1632             __func__, f7_msg->addr);
1633         writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1634         f7_msg->result = -EAGAIN;
1635     }
1636 
1637     if (status & STM32F7_I2C_ISR_PECERR) {
1638         dev_err(dev, "<%s>: PEC error in reception accessing addr 0x%x\n",
1639             __func__, f7_msg->addr);
1640         writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1641         f7_msg->result = -EINVAL;
1642     }
1643 
1644     if (status & STM32F7_I2C_ISR_ALERT) {
1645         dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
1646         writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1647         i2c_handle_smbus_alert(i2c_dev->alert->ara);
1648         return IRQ_HANDLED;
1649     }
1650 
1651     if (!i2c_dev->slave_running) {
1652         u32 mask;
1653         /* Disable interrupts */
1654         if (stm32f7_i2c_is_slave_registered(i2c_dev))
1655             mask = STM32F7_I2C_XFER_IRQ_MASK;
1656         else
1657             mask = STM32F7_I2C_ALL_IRQ_MASK;
1658         stm32f7_i2c_disable_irq(i2c_dev, mask);
1659     }
1660 
1661     /* Disable dma */
1662     if (i2c_dev->use_dma) {
1663         stm32f7_i2c_disable_dma_req(i2c_dev);
1664         dmaengine_terminate_async(dma->chan_using);
1665     }
1666 
1667     i2c_dev->master_mode = false;
1668     complete(&i2c_dev->complete);
1669 
1670     return IRQ_HANDLED;
1671 }
1672 
1673 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1674                 struct i2c_msg msgs[], int num)
1675 {
1676     struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1677     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1678     struct stm32_i2c_dma *dma = i2c_dev->dma;
1679     unsigned long time_left;
1680     int ret;
1681 
1682     i2c_dev->msg = msgs;
1683     i2c_dev->msg_num = num;
1684     i2c_dev->msg_id = 0;
1685     f7_msg->smbus = false;
1686 
1687     ret = pm_runtime_resume_and_get(i2c_dev->dev);
1688     if (ret < 0)
1689         return ret;
1690 
1691     ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1692     if (ret)
1693         goto pm_free;
1694 
1695     stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1696 
1697     time_left = wait_for_completion_timeout(&i2c_dev->complete,
1698                         i2c_dev->adap.timeout);
1699     ret = f7_msg->result;
1700     if (ret) {
1701         if (i2c_dev->use_dma)
1702             dmaengine_synchronize(dma->chan_using);
1703 
1704         /*
1705          * It is possible that some unsent data have already been
1706          * written into TXDR. To avoid sending old data in a
1707          * further transfer, flush TXDR in case of any error
1708          */
1709         writel_relaxed(STM32F7_I2C_ISR_TXE,
1710                    i2c_dev->base + STM32F7_I2C_ISR);
1711         goto pm_free;
1712     }
1713 
1714     if (!time_left) {
1715         dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1716             i2c_dev->msg->addr);
1717         if (i2c_dev->use_dma)
1718             dmaengine_terminate_sync(dma->chan_using);
1719         stm32f7_i2c_wait_free_bus(i2c_dev);
1720         ret = -ETIMEDOUT;
1721     }
1722 
1723 pm_free:
1724     pm_runtime_mark_last_busy(i2c_dev->dev);
1725     pm_runtime_put_autosuspend(i2c_dev->dev);
1726 
1727     return (ret < 0) ? ret : num;
1728 }
1729 
1730 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1731                   unsigned short flags, char read_write,
1732                   u8 command, int size,
1733                   union i2c_smbus_data *data)
1734 {
1735     struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1736     struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1737     struct stm32_i2c_dma *dma = i2c_dev->dma;
1738     struct device *dev = i2c_dev->dev;
1739     unsigned long timeout;
1740     int i, ret;
1741 
1742     f7_msg->addr = addr;
1743     f7_msg->size = size;
1744     f7_msg->read_write = read_write;
1745     f7_msg->smbus = true;
1746 
1747     ret = pm_runtime_resume_and_get(dev);
1748     if (ret < 0)
1749         return ret;
1750 
1751     ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1752     if (ret)
1753         goto pm_free;
1754 
1755     ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1756     if (ret)
1757         goto pm_free;
1758 
1759     timeout = wait_for_completion_timeout(&i2c_dev->complete,
1760                           i2c_dev->adap.timeout);
1761     ret = f7_msg->result;
1762     if (ret) {
1763         if (i2c_dev->use_dma)
1764             dmaengine_synchronize(dma->chan_using);
1765 
1766         /*
1767          * It is possible that some unsent data have already been
1768          * written into TXDR. To avoid sending old data in a
1769          * further transfer, flush TXDR in case of any error
1770          */
1771         writel_relaxed(STM32F7_I2C_ISR_TXE,
1772                    i2c_dev->base + STM32F7_I2C_ISR);
1773         goto pm_free;
1774     }
1775 
1776     if (!timeout) {
1777         dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1778         if (i2c_dev->use_dma)
1779             dmaengine_terminate_sync(dma->chan_using);
1780         stm32f7_i2c_wait_free_bus(i2c_dev);
1781         ret = -ETIMEDOUT;
1782         goto pm_free;
1783     }
1784 
1785     /* Check PEC */
1786     if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1787         ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1788         if (ret)
1789             goto pm_free;
1790     }
1791 
1792     if (read_write && size != I2C_SMBUS_QUICK) {
1793         switch (size) {
1794         case I2C_SMBUS_BYTE:
1795         case I2C_SMBUS_BYTE_DATA:
1796             data->byte = f7_msg->smbus_buf[0];
1797         break;
1798         case I2C_SMBUS_WORD_DATA:
1799         case I2C_SMBUS_PROC_CALL:
1800             data->word = f7_msg->smbus_buf[0] |
1801                 (f7_msg->smbus_buf[1] << 8);
1802         break;
1803         case I2C_SMBUS_BLOCK_DATA:
1804         case I2C_SMBUS_BLOCK_PROC_CALL:
1805         for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1806             data->block[i] = f7_msg->smbus_buf[i];
1807         break;
1808         default:
1809             dev_err(dev, "Unsupported smbus transaction\n");
1810             ret = -EINVAL;
1811         }
1812     }
1813 
1814 pm_free:
1815     pm_runtime_mark_last_busy(dev);
1816     pm_runtime_put_autosuspend(dev);
1817     return ret;
1818 }
1819 
1820 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1821                       bool enable)
1822 {
1823     void __iomem *base = i2c_dev->base;
1824     u32 mask = STM32F7_I2C_CR1_WUPEN;
1825 
1826     if (!i2c_dev->wakeup_src)
1827         return;
1828 
1829     if (enable) {
1830         device_set_wakeup_enable(i2c_dev->dev, true);
1831         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1832     } else {
1833         device_set_wakeup_enable(i2c_dev->dev, false);
1834         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1835     }
1836 }
1837 
1838 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1839 {
1840     struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1841     void __iomem *base = i2c_dev->base;
1842     struct device *dev = i2c_dev->dev;
1843     u32 oar1, oar2, mask;
1844     int id, ret;
1845 
1846     if (slave->flags & I2C_CLIENT_PEC) {
1847         dev_err(dev, "SMBus PEC not supported in slave mode\n");
1848         return -EINVAL;
1849     }
1850 
1851     if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1852         dev_err(dev, "Too much slave registered\n");
1853         return -EBUSY;
1854     }
1855 
1856     ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1857     if (ret)
1858         return ret;
1859 
1860     ret = pm_runtime_resume_and_get(dev);
1861     if (ret < 0)
1862         return ret;
1863 
1864     if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1865         stm32f7_i2c_enable_wakeup(i2c_dev, true);
1866 
1867     switch (id) {
1868     case 0:
1869         /* Slave SMBus Host */
1870         i2c_dev->slave[id] = slave;
1871         break;
1872 
1873     case 1:
1874         /* Configure Own Address 1 */
1875         oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1876         oar1 &= ~STM32F7_I2C_OAR1_MASK;
1877         if (slave->flags & I2C_CLIENT_TEN) {
1878             oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1879             oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1880         } else {
1881             oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1882         }
1883         oar1 |= STM32F7_I2C_OAR1_OA1EN;
1884         i2c_dev->slave[id] = slave;
1885         writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1886         break;
1887 
1888     case 2:
1889         /* Configure Own Address 2 */
1890         oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1891         oar2 &= ~STM32F7_I2C_OAR2_MASK;
1892         if (slave->flags & I2C_CLIENT_TEN) {
1893             ret = -EOPNOTSUPP;
1894             goto pm_free;
1895         }
1896 
1897         oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1898         oar2 |= STM32F7_I2C_OAR2_OA2EN;
1899         i2c_dev->slave[id] = slave;
1900         writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1901         break;
1902 
1903     default:
1904         dev_err(dev, "I2C slave id not supported\n");
1905         ret = -ENODEV;
1906         goto pm_free;
1907     }
1908 
1909     /* Enable ACK */
1910     stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1911 
1912     /* Enable Address match interrupt, error interrupt and enable I2C  */
1913     mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1914         STM32F7_I2C_CR1_PE;
1915     stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1916 
1917     ret = 0;
1918 pm_free:
1919     if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1920         stm32f7_i2c_enable_wakeup(i2c_dev, false);
1921 
1922     pm_runtime_mark_last_busy(dev);
1923     pm_runtime_put_autosuspend(dev);
1924 
1925     return ret;
1926 }
1927 
1928 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1929 {
1930     struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1931     void __iomem *base = i2c_dev->base;
1932     u32 mask;
1933     int id, ret;
1934 
1935     ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1936     if (ret)
1937         return ret;
1938 
1939     WARN_ON(!i2c_dev->slave[id]);
1940 
1941     ret = pm_runtime_resume_and_get(i2c_dev->dev);
1942     if (ret < 0)
1943         return ret;
1944 
1945     if (id == 1) {
1946         mask = STM32F7_I2C_OAR1_OA1EN;
1947         stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1948     } else if (id == 2) {
1949         mask = STM32F7_I2C_OAR2_OA2EN;
1950         stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1951     }
1952 
1953     i2c_dev->slave[id] = NULL;
1954 
1955     if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1956         stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1957         stm32f7_i2c_enable_wakeup(i2c_dev, false);
1958     }
1959 
1960     pm_runtime_mark_last_busy(i2c_dev->dev);
1961     pm_runtime_put_autosuspend(i2c_dev->dev);
1962 
1963     return 0;
1964 }
1965 
1966 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1967                       bool enable)
1968 {
1969     int ret;
1970 
1971     if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1972         IS_ERR_OR_NULL(i2c_dev->regmap))
1973         /* Optional */
1974         return 0;
1975 
1976     if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1977         ret = regmap_update_bits(i2c_dev->regmap,
1978                      i2c_dev->fmp_sreg,
1979                      i2c_dev->fmp_mask,
1980                      enable ? i2c_dev->fmp_mask : 0);
1981     else
1982         ret = regmap_write(i2c_dev->regmap,
1983                    enable ? i2c_dev->fmp_sreg :
1984                         i2c_dev->fmp_creg,
1985                    i2c_dev->fmp_mask);
1986 
1987     return ret;
1988 }
1989 
1990 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1991                       struct stm32f7_i2c_dev *i2c_dev)
1992 {
1993     struct device_node *np = pdev->dev.of_node;
1994     int ret;
1995 
1996     i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1997     if (IS_ERR(i2c_dev->regmap))
1998         /* Optional */
1999         return 0;
2000 
2001     ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
2002                      &i2c_dev->fmp_sreg);
2003     if (ret)
2004         return ret;
2005 
2006     i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
2007                    i2c_dev->setup.fmp_clr_offset;
2008 
2009     return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
2010                       &i2c_dev->fmp_mask);
2011 }
2012 
2013 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2014 {
2015     struct i2c_adapter *adap = &i2c_dev->adap;
2016     void __iomem *base = i2c_dev->base;
2017     struct i2c_client *client;
2018 
2019     client = i2c_new_slave_host_notify_device(adap);
2020     if (IS_ERR(client))
2021         return PTR_ERR(client);
2022 
2023     i2c_dev->host_notify_client = client;
2024 
2025     /* Enable SMBus Host address */
2026     stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2027 
2028     return 0;
2029 }
2030 
2031 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2032 {
2033     void __iomem *base = i2c_dev->base;
2034 
2035     if (i2c_dev->host_notify_client) {
2036         /* Disable SMBus Host address */
2037         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2038                      STM32F7_I2C_CR1_SMBHEN);
2039         i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2040     }
2041 }
2042 
2043 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2044 {
2045     struct stm32f7_i2c_alert *alert;
2046     struct i2c_adapter *adap = &i2c_dev->adap;
2047     struct device *dev = i2c_dev->dev;
2048     void __iomem *base = i2c_dev->base;
2049 
2050     alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
2051     if (!alert)
2052         return -ENOMEM;
2053 
2054     alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
2055     if (IS_ERR(alert->ara))
2056         return PTR_ERR(alert->ara);
2057 
2058     i2c_dev->alert = alert;
2059 
2060     /* Enable SMBus Alert */
2061     stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2062 
2063     return 0;
2064 }
2065 
2066 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2067 {
2068     struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2069     void __iomem *base = i2c_dev->base;
2070 
2071     if (alert) {
2072         /* Disable SMBus Alert */
2073         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2074                      STM32F7_I2C_CR1_ALERTEN);
2075         i2c_unregister_device(alert->ara);
2076     }
2077 }
2078 
2079 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2080 {
2081     struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2082 
2083     u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2084            I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2085            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2086            I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2087            I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2088            I2C_FUNC_SMBUS_I2C_BLOCK;
2089 
2090     if (i2c_dev->smbus_mode)
2091         func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2092 
2093     return func;
2094 }
2095 
2096 static const struct i2c_algorithm stm32f7_i2c_algo = {
2097     .master_xfer = stm32f7_i2c_xfer,
2098     .smbus_xfer = stm32f7_i2c_smbus_xfer,
2099     .functionality = stm32f7_i2c_func,
2100     .reg_slave = stm32f7_i2c_reg_slave,
2101     .unreg_slave = stm32f7_i2c_unreg_slave,
2102 };
2103 
2104 static int stm32f7_i2c_probe(struct platform_device *pdev)
2105 {
2106     struct stm32f7_i2c_dev *i2c_dev;
2107     const struct stm32f7_i2c_setup *setup;
2108     struct resource *res;
2109     struct i2c_adapter *adap;
2110     struct reset_control *rst;
2111     dma_addr_t phy_addr;
2112     int irq_error, irq_event, ret;
2113 
2114     i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2115     if (!i2c_dev)
2116         return -ENOMEM;
2117 
2118     i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2119     if (IS_ERR(i2c_dev->base))
2120         return PTR_ERR(i2c_dev->base);
2121     phy_addr = (dma_addr_t)res->start;
2122 
2123     irq_event = platform_get_irq(pdev, 0);
2124     if (irq_event <= 0)
2125         return irq_event ? : -ENOENT;
2126 
2127     irq_error = platform_get_irq(pdev, 1);
2128     if (irq_error <= 0)
2129         return irq_error ? : -ENOENT;
2130 
2131     i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2132                             "wakeup-source");
2133 
2134     i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2135     if (IS_ERR(i2c_dev->clk))
2136         return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2137                      "Failed to get controller clock\n");
2138 
2139     ret = clk_prepare_enable(i2c_dev->clk);
2140     if (ret) {
2141         dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2142         return ret;
2143     }
2144 
2145     rst = devm_reset_control_get(&pdev->dev, NULL);
2146     if (IS_ERR(rst)) {
2147         ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2148                     "Error: Missing reset ctrl\n");
2149         goto clk_free;
2150     }
2151     reset_control_assert(rst);
2152     udelay(2);
2153     reset_control_deassert(rst);
2154 
2155     i2c_dev->dev = &pdev->dev;
2156 
2157     ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2158                     stm32f7_i2c_isr_event,
2159                     stm32f7_i2c_isr_event_thread,
2160                     IRQF_ONESHOT,
2161                     pdev->name, i2c_dev);
2162     if (ret) {
2163         dev_err(&pdev->dev, "Failed to request irq event %i\n",
2164             irq_event);
2165         goto clk_free;
2166     }
2167 
2168     ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2169                    pdev->name, i2c_dev);
2170     if (ret) {
2171         dev_err(&pdev->dev, "Failed to request irq error %i\n",
2172             irq_error);
2173         goto clk_free;
2174     }
2175 
2176     setup = of_device_get_match_data(&pdev->dev);
2177     if (!setup) {
2178         dev_err(&pdev->dev, "Can't get device data\n");
2179         ret = -ENODEV;
2180         goto clk_free;
2181     }
2182     i2c_dev->setup = *setup;
2183 
2184     ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2185     if (ret)
2186         goto clk_free;
2187 
2188     /* Setup Fast mode plus if necessary */
2189     if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2190         ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2191         if (ret)
2192             goto clk_free;
2193         ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2194         if (ret)
2195             goto clk_free;
2196     }
2197 
2198     adap = &i2c_dev->adap;
2199     i2c_set_adapdata(adap, i2c_dev);
2200     snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2201          &res->start);
2202     adap->owner = THIS_MODULE;
2203     adap->timeout = 2 * HZ;
2204     adap->retries = 3;
2205     adap->algo = &stm32f7_i2c_algo;
2206     adap->dev.parent = &pdev->dev;
2207     adap->dev.of_node = pdev->dev.of_node;
2208 
2209     init_completion(&i2c_dev->complete);
2210 
2211     /* Init DMA config if supported */
2212     i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2213                          STM32F7_I2C_TXDR,
2214                          STM32F7_I2C_RXDR);
2215     if (IS_ERR(i2c_dev->dma)) {
2216         ret = PTR_ERR(i2c_dev->dma);
2217         /* DMA support is optional, only report other errors */
2218         if (ret != -ENODEV)
2219             goto fmp_clear;
2220         dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2221         i2c_dev->dma = NULL;
2222     }
2223 
2224     if (i2c_dev->wakeup_src) {
2225         device_set_wakeup_capable(i2c_dev->dev, true);
2226 
2227         ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2228         if (ret) {
2229             dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2230             goto clr_wakeup_capable;
2231         }
2232     }
2233 
2234     platform_set_drvdata(pdev, i2c_dev);
2235 
2236     pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2237                      STM32F7_AUTOSUSPEND_DELAY);
2238     pm_runtime_use_autosuspend(i2c_dev->dev);
2239     pm_runtime_set_active(i2c_dev->dev);
2240     pm_runtime_enable(i2c_dev->dev);
2241 
2242     pm_runtime_get_noresume(&pdev->dev);
2243 
2244     stm32f7_i2c_hw_config(i2c_dev);
2245 
2246     i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2247 
2248     ret = i2c_add_adapter(adap);
2249     if (ret)
2250         goto pm_disable;
2251 
2252     if (i2c_dev->smbus_mode) {
2253         ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2254         if (ret) {
2255             dev_err(i2c_dev->dev,
2256                 "failed to enable SMBus Host-Notify protocol (%d)\n",
2257                 ret);
2258             goto i2c_adapter_remove;
2259         }
2260     }
2261 
2262     if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
2263         ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2264         if (ret) {
2265             dev_err(i2c_dev->dev,
2266                 "failed to enable SMBus alert protocol (%d)\n",
2267                 ret);
2268             goto i2c_disable_smbus_host;
2269         }
2270     }
2271 
2272     dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2273 
2274     pm_runtime_mark_last_busy(i2c_dev->dev);
2275     pm_runtime_put_autosuspend(i2c_dev->dev);
2276 
2277     return 0;
2278 
2279 i2c_disable_smbus_host:
2280     stm32f7_i2c_disable_smbus_host(i2c_dev);
2281 
2282 i2c_adapter_remove:
2283     i2c_del_adapter(adap);
2284 
2285 pm_disable:
2286     pm_runtime_put_noidle(i2c_dev->dev);
2287     pm_runtime_disable(i2c_dev->dev);
2288     pm_runtime_set_suspended(i2c_dev->dev);
2289     pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2290 
2291     if (i2c_dev->wakeup_src)
2292         dev_pm_clear_wake_irq(i2c_dev->dev);
2293 
2294 clr_wakeup_capable:
2295     if (i2c_dev->wakeup_src)
2296         device_set_wakeup_capable(i2c_dev->dev, false);
2297 
2298     if (i2c_dev->dma) {
2299         stm32_i2c_dma_free(i2c_dev->dma);
2300         i2c_dev->dma = NULL;
2301     }
2302 
2303 fmp_clear:
2304     stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2305 
2306 clk_free:
2307     clk_disable_unprepare(i2c_dev->clk);
2308 
2309     return ret;
2310 }
2311 
2312 static int stm32f7_i2c_remove(struct platform_device *pdev)
2313 {
2314     struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2315 
2316     stm32f7_i2c_disable_smbus_alert(i2c_dev);
2317     stm32f7_i2c_disable_smbus_host(i2c_dev);
2318 
2319     i2c_del_adapter(&i2c_dev->adap);
2320     pm_runtime_get_sync(i2c_dev->dev);
2321 
2322     if (i2c_dev->wakeup_src) {
2323         dev_pm_clear_wake_irq(i2c_dev->dev);
2324         /*
2325          * enforce that wakeup is disabled and that the device
2326          * is marked as non wakeup capable
2327          */
2328         device_init_wakeup(i2c_dev->dev, false);
2329     }
2330 
2331     pm_runtime_put_noidle(i2c_dev->dev);
2332     pm_runtime_disable(i2c_dev->dev);
2333     pm_runtime_set_suspended(i2c_dev->dev);
2334     pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2335 
2336     if (i2c_dev->dma) {
2337         stm32_i2c_dma_free(i2c_dev->dma);
2338         i2c_dev->dma = NULL;
2339     }
2340 
2341     stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2342 
2343     clk_disable_unprepare(i2c_dev->clk);
2344 
2345     return 0;
2346 }
2347 
2348 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2349 {
2350     struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2351 
2352     if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2353         clk_disable_unprepare(i2c_dev->clk);
2354 
2355     return 0;
2356 }
2357 
2358 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2359 {
2360     struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2361     int ret;
2362 
2363     if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2364         ret = clk_prepare_enable(i2c_dev->clk);
2365         if (ret) {
2366             dev_err(dev, "failed to prepare_enable clock\n");
2367             return ret;
2368         }
2369     }
2370 
2371     return 0;
2372 }
2373 
2374 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2375 {
2376     int ret;
2377     struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2378 
2379     ret = pm_runtime_resume_and_get(i2c_dev->dev);
2380     if (ret < 0)
2381         return ret;
2382 
2383     backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2384     backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2385     backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2386     backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2387     backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2388     stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2389 
2390     pm_runtime_put_sync(i2c_dev->dev);
2391 
2392     return ret;
2393 }
2394 
2395 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2396 {
2397     u32 cr1;
2398     int ret;
2399     struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2400 
2401     ret = pm_runtime_resume_and_get(i2c_dev->dev);
2402     if (ret < 0)
2403         return ret;
2404 
2405     cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2406     if (cr1 & STM32F7_I2C_CR1_PE)
2407         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2408                      STM32F7_I2C_CR1_PE);
2409 
2410     writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2411     writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2412                i2c_dev->base + STM32F7_I2C_CR1);
2413     if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2414         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2415                      STM32F7_I2C_CR1_PE);
2416     writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2417     writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2418     writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2419     stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2420 
2421     pm_runtime_put_sync(i2c_dev->dev);
2422 
2423     return ret;
2424 }
2425 
2426 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2427 {
2428     struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2429     int ret;
2430 
2431     i2c_mark_adapter_suspended(&i2c_dev->adap);
2432 
2433     if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2434         ret = stm32f7_i2c_regs_backup(i2c_dev);
2435         if (ret < 0) {
2436             i2c_mark_adapter_resumed(&i2c_dev->adap);
2437             return ret;
2438         }
2439 
2440         pinctrl_pm_select_sleep_state(dev);
2441         pm_runtime_force_suspend(dev);
2442     }
2443 
2444     return 0;
2445 }
2446 
2447 static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2448 {
2449     struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2450     int ret;
2451 
2452     if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2453         ret = pm_runtime_force_resume(dev);
2454         if (ret < 0)
2455             return ret;
2456         pinctrl_pm_select_default_state(dev);
2457 
2458         ret = stm32f7_i2c_regs_restore(i2c_dev);
2459         if (ret < 0)
2460             return ret;
2461     }
2462 
2463     i2c_mark_adapter_resumed(&i2c_dev->adap);
2464 
2465     return 0;
2466 }
2467 
2468 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2469     SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2470                stm32f7_i2c_runtime_resume, NULL)
2471     SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2472 };
2473 
2474 static const struct of_device_id stm32f7_i2c_match[] = {
2475     { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2476     { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2477     { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup},
2478     {},
2479 };
2480 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2481 
2482 static struct platform_driver stm32f7_i2c_driver = {
2483     .driver = {
2484         .name = "stm32f7-i2c",
2485         .of_match_table = stm32f7_i2c_match,
2486         .pm = &stm32f7_i2c_pm_ops,
2487     },
2488     .probe = stm32f7_i2c_probe,
2489     .remove = stm32f7_i2c_remove,
2490 };
2491 
2492 module_platform_driver(stm32f7_i2c_driver);
2493 
2494 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2495 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2496 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!