i2c/busses/i2c-stm32f4.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for STMicroelectronics STM32 I2C controller
0004  *
0005  * This I2C controller is described in the STM32F429/439 Soc reference manual.
0006  * Please see below a link to the documentation:
0007  * http://www.st.com/resource/en/reference_manual/DM00031020.pdf
0008  *
0009  * Copyright (C) M'boumba Cedric Madianga 2016
0010  * Copyright (C) STMicroelectronics 2017
0011  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
0012  *
0013  * This driver is based on i2c-st.c
0014  *
0015  */
0016
0017 #include <linux/clk.h>
0018 #include <linux/delay.h>
0019 #include <linux/err.h>
0020 #include <linux/i2c.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/io.h>
0023 #include <linux/iopoll.h>
0024 #include <linux/module.h>
0025 #include <linux/of_address.h>
0026 #include <linux/of_irq.h>
0027 #include <linux/of.h>
0028 #include <linux/platform_device.h>
0029 #include <linux/reset.h>
0030
0031 #include "i2c-stm32.h"
0032
0033 /* STM32F4 I2C offset registers */
0034 #define STM32F4_I2C_CR1         0x00
0035 #define STM32F4_I2C_CR2         0x04
0036 #define STM32F4_I2C_DR          0x10
0037 #define STM32F4_I2C_SR1         0x14
0038 #define STM32F4_I2C_SR2         0x18
0039 #define STM32F4_I2C_CCR         0x1C
0040 #define STM32F4_I2C_TRISE       0x20
0041 #define STM32F4_I2C_FLTR        0x24
0042
0043 /* STM32F4 I2C control 1*/
0044 #define STM32F4_I2C_CR1_POS     BIT(11)
0045 #define STM32F4_I2C_CR1_ACK     BIT(10)
0046 #define STM32F4_I2C_CR1_STOP        BIT(9)
0047 #define STM32F4_I2C_CR1_START       BIT(8)
0048 #define STM32F4_I2C_CR1_PE      BIT(0)
0049
0050 /* STM32F4 I2C control 2 */
0051 #define STM32F4_I2C_CR2_FREQ_MASK   GENMASK(5, 0)
0052 #define STM32F4_I2C_CR2_FREQ(n)     ((n) & STM32F4_I2C_CR2_FREQ_MASK)
0053 #define STM32F4_I2C_CR2_ITBUFEN     BIT(10)
0054 #define STM32F4_I2C_CR2_ITEVTEN     BIT(9)
0055 #define STM32F4_I2C_CR2_ITERREN     BIT(8)
0056 #define STM32F4_I2C_CR2_IRQ_MASK    (STM32F4_I2C_CR2_ITBUFEN | \
0057                      STM32F4_I2C_CR2_ITEVTEN | \
0058                      STM32F4_I2C_CR2_ITERREN)
0059
0060 /* STM32F4 I2C Status 1 */
0061 #define STM32F4_I2C_SR1_AF      BIT(10)
0062 #define STM32F4_I2C_SR1_ARLO        BIT(9)
0063 #define STM32F4_I2C_SR1_BERR        BIT(8)
0064 #define STM32F4_I2C_SR1_TXE     BIT(7)
0065 #define STM32F4_I2C_SR1_RXNE        BIT(6)
0066 #define STM32F4_I2C_SR1_BTF     BIT(2)
0067 #define STM32F4_I2C_SR1_ADDR        BIT(1)
0068 #define STM32F4_I2C_SR1_SB      BIT(0)
0069 #define STM32F4_I2C_SR1_ITEVTEN_MASK    (STM32F4_I2C_SR1_BTF | \
0070                      STM32F4_I2C_SR1_ADDR | \
0071                      STM32F4_I2C_SR1_SB)
0072 #define STM32F4_I2C_SR1_ITBUFEN_MASK    (STM32F4_I2C_SR1_TXE | \
0073                      STM32F4_I2C_SR1_RXNE)
0074 #define STM32F4_I2C_SR1_ITERREN_MASK    (STM32F4_I2C_SR1_AF | \
0075                      STM32F4_I2C_SR1_ARLO | \
0076                      STM32F4_I2C_SR1_BERR)
0077
0078 /* STM32F4 I2C Status 2 */
0079 #define STM32F4_I2C_SR2_BUSY        BIT(1)
0080
0081 /* STM32F4 I2C Control Clock */
0082 #define STM32F4_I2C_CCR_CCR_MASK    GENMASK(11, 0)
0083 #define STM32F4_I2C_CCR_CCR(n)      ((n) & STM32F4_I2C_CCR_CCR_MASK)
0084 #define STM32F4_I2C_CCR_FS      BIT(15)
0085 #define STM32F4_I2C_CCR_DUTY        BIT(14)
0086
0087 /* STM32F4 I2C Trise */
0088 #define STM32F4_I2C_TRISE_VALUE_MASK    GENMASK(5, 0)
0089 #define STM32F4_I2C_TRISE_VALUE(n)  ((n) & STM32F4_I2C_TRISE_VALUE_MASK)
0090
0091 #define STM32F4_I2C_MIN_STANDARD_FREQ   2U
0092 #define STM32F4_I2C_MIN_FAST_FREQ   6U
0093 #define STM32F4_I2C_MAX_FREQ        46U
0094 #define HZ_TO_MHZ           1000000
0095
0096 /**
0097  * struct stm32f4_i2c_msg - client specific data
0098  * @addr: 8-bit slave addr, including r/w bit
0099  * @count: number of bytes to be transferred
0100  * @buf: data buffer
0101  * @result: result of the transfer
0102  * @stop: last I2C msg to be sent, i.e. STOP to be generated
0103  */
0104 struct stm32f4_i2c_msg {
0105     u8 addr;
0106     u32 count;
0107     u8 *buf;
0108     int result;
0109     bool stop;
0110 };
0111
0112 /**
0113  * struct stm32f4_i2c_dev - private data of the controller
0114  * @adap: I2C adapter for this controller
0115  * @dev: device for this controller
0116  * @base: virtual memory area
0117  * @complete: completion of I2C message
0118  * @clk: hw i2c clock
0119  * @speed: I2C clock frequency of the controller. Standard or Fast are supported
0120  * @parent_rate: I2C clock parent rate in MHz
0121  * @msg: I2C transfer information
0122  */
0123 struct stm32f4_i2c_dev {
0124     struct i2c_adapter adap;
0125     struct device *dev;
0126     void __iomem *base;
0127     struct completion complete;
0128     struct clk *clk;
0129     int speed;
0130     int parent_rate;
0131     struct stm32f4_i2c_msg msg;
0132 };
0133
0134 static inline void stm32f4_i2c_set_bits(void __iomem *reg, u32 mask)
0135 {
0136     writel_relaxed(readl_relaxed(reg) | mask, reg);
0137 }
0138
0139 static inline void stm32f4_i2c_clr_bits(void __iomem *reg, u32 mask)
0140 {
0141     writel_relaxed(readl_relaxed(reg) & ~mask, reg);
0142 }
0143
0144 static void stm32f4_i2c_disable_irq(struct stm32f4_i2c_dev *i2c_dev)
0145 {
0146     void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
0147
0148     stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_IRQ_MASK);
0149 }
0150
0151 static int stm32f4_i2c_set_periph_clk_freq(struct stm32f4_i2c_dev *i2c_dev)
0152 {
0153     u32 freq;
0154     u32 cr2 = 0;
0155
0156     i2c_dev->parent_rate = clk_get_rate(i2c_dev->clk);
0157     freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
0158
0159     if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
0160         /*
0161          * To reach 100 kHz, the parent clk frequency should be between
0162          * a minimum value of 2 MHz and a maximum value of 46 MHz due
0163          * to hardware limitation
0164          */
0165         if (freq < STM32F4_I2C_MIN_STANDARD_FREQ ||
0166             freq > STM32F4_I2C_MAX_FREQ) {
0167             dev_err(i2c_dev->dev,
0168                 "bad parent clk freq for standard mode\n");
0169             return -EINVAL;
0170         }
0171     } else {
0172         /*
0173          * To be as close as possible to 400 kHz, the parent clk
0174          * frequency should be between a minimum value of 6 MHz and a
0175          * maximum value of 46 MHz due to hardware limitation
0176          */
0177         if (freq < STM32F4_I2C_MIN_FAST_FREQ ||
0178             freq > STM32F4_I2C_MAX_FREQ) {
0179             dev_err(i2c_dev->dev,
0180                 "bad parent clk freq for fast mode\n");
0181             return -EINVAL;
0182         }
0183     }
0184
0185     cr2 |= STM32F4_I2C_CR2_FREQ(freq);
0186     writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
0187
0188     return 0;
0189 }
0190
0191 static void stm32f4_i2c_set_rise_time(struct stm32f4_i2c_dev *i2c_dev)
0192 {
0193     u32 freq = DIV_ROUND_UP(i2c_dev->parent_rate, HZ_TO_MHZ);
0194     u32 trise;
0195
0196     /*
0197      * These bits must be programmed with the maximum SCL rise time given in
0198      * the I2C bus specification, incremented by 1.
0199      *
0200      * In standard mode, the maximum allowed SCL rise time is 1000 ns.
0201      * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to
0202      * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be
0203      * programmed with 0x9. (1000 ns / 125 ns + 1)
0204      * So, for I2C standard mode TRISE = FREQ[5:0] + 1
0205      *
0206      * In fast mode, the maximum allowed SCL rise time is 300 ns.
0207      * If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to
0208      * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be
0209      * programmed with 0x3. (300 ns / 125 ns + 1)
0210      * So, for I2C fast mode TRISE = FREQ[5:0] * 300 / 1000 + 1
0211      *
0212      * Function stm32f4_i2c_set_periph_clk_freq made sure that parent rate
0213      * is not higher than 46 MHz . As a result trise is at most 4 bits wide
0214      * and so fits into the TRISE bits [5:0].
0215      */
0216     if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD)
0217         trise = freq + 1;
0218     else
0219         trise = freq * 3 / 10 + 1;
0220
0221     writel_relaxed(STM32F4_I2C_TRISE_VALUE(trise),
0222                i2c_dev->base + STM32F4_I2C_TRISE);
0223 }
0224
0225 static void stm32f4_i2c_set_speed_mode(struct stm32f4_i2c_dev *i2c_dev)
0226 {
0227     u32 val;
0228     u32 ccr = 0;
0229
0230     if (i2c_dev->speed == STM32_I2C_SPEED_STANDARD) {
0231         /*
0232          * In standard mode:
0233          * t_scl_high = t_scl_low = CCR * I2C parent clk period
0234          * So to reach 100 kHz, we have:
0235          * CCR = I2C parent rate / (100 kHz * 2)
0236          *
0237          * For example with parent rate = 2 MHz:
0238          * CCR = 2000000 / (100000 * 2) = 10
0239          * t_scl_high = t_scl_low = 10 * (1 / 2000000) = 5000 ns
0240          * t_scl_high + t_scl_low = 10000 ns so 100 kHz is reached
0241          *
0242          * Function stm32f4_i2c_set_periph_clk_freq made sure that
0243          * parent rate is not higher than 46 MHz . As a result val
0244          * is at most 8 bits wide and so fits into the CCR bits [11:0].
0245          */
0246         val = i2c_dev->parent_rate / (I2C_MAX_STANDARD_MODE_FREQ * 2);
0247     } else {
0248         /*
0249          * In fast mode, we compute CCR with duty = 0 as with low
0250          * frequencies we are not able to reach 400 kHz.
0251          * In that case:
0252          * t_scl_high = CCR * I2C parent clk period
0253          * t_scl_low = 2 * CCR * I2C parent clk period
0254          * So, CCR = I2C parent rate / (400 kHz * 3)
0255          *
0256          * For example with parent rate = 6 MHz:
0257          * CCR = 6000000 / (400000 * 3) = 5
0258          * t_scl_high = 5 * (1 / 6000000) = 833 ns > 600 ns
0259          * t_scl_low = 2 * 5 * (1 / 6000000) = 1667 ns > 1300 ns
0260          * t_scl_high + t_scl_low = 2500 ns so 400 kHz is reached
0261          *
0262          * Function stm32f4_i2c_set_periph_clk_freq made sure that
0263          * parent rate is not higher than 46 MHz . As a result val
0264          * is at most 6 bits wide and so fits into the CCR bits [11:0].
0265          */
0266         val = DIV_ROUND_UP(i2c_dev->parent_rate, I2C_MAX_FAST_MODE_FREQ * 3);
0267
0268         /* Select Fast mode */
0269         ccr |= STM32F4_I2C_CCR_FS;
0270     }
0271
0272     ccr |= STM32F4_I2C_CCR_CCR(val);
0273     writel_relaxed(ccr, i2c_dev->base + STM32F4_I2C_CCR);
0274 }
0275
0276 /**
0277  * stm32f4_i2c_hw_config() - Prepare I2C block
0278  * @i2c_dev: Controller's private data
0279  */
0280 static int stm32f4_i2c_hw_config(struct stm32f4_i2c_dev *i2c_dev)
0281 {
0282     int ret;
0283
0284     ret = stm32f4_i2c_set_periph_clk_freq(i2c_dev);
0285     if (ret)
0286         return ret;
0287
0288     stm32f4_i2c_set_rise_time(i2c_dev);
0289
0290     stm32f4_i2c_set_speed_mode(i2c_dev);
0291
0292     /* Enable I2C */
0293     writel_relaxed(STM32F4_I2C_CR1_PE, i2c_dev->base + STM32F4_I2C_CR1);
0294
0295     return 0;
0296 }
0297
0298 static int stm32f4_i2c_wait_free_bus(struct stm32f4_i2c_dev *i2c_dev)
0299 {
0300     u32 status;
0301     int ret;
0302
0303     ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F4_I2C_SR2,
0304                      status,
0305                      !(status & STM32F4_I2C_SR2_BUSY),
0306                      10, 1000);
0307     if (ret) {
0308         dev_dbg(i2c_dev->dev, "bus not free\n");
0309         ret = -EBUSY;
0310     }
0311
0312     return ret;
0313 }
0314
0315 /**
0316  * stm32f4_i2c_write_byte() - Write a byte in the data register
0317  * @i2c_dev: Controller's private data
0318  * @byte: Data to write in the register
0319  */
0320 static void stm32f4_i2c_write_byte(struct stm32f4_i2c_dev *i2c_dev, u8 byte)
0321 {
0322     writel_relaxed(byte, i2c_dev->base + STM32F4_I2C_DR);
0323 }
0324
0325 /**
0326  * stm32f4_i2c_write_msg() - Fill the data register in write mode
0327  * @i2c_dev: Controller's private data
0328  *
0329  * This function fills the data register with I2C transfer buffer
0330  */
0331 static void stm32f4_i2c_write_msg(struct stm32f4_i2c_dev *i2c_dev)
0332 {
0333     struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
0334
0335     stm32f4_i2c_write_byte(i2c_dev, *msg->buf++);
0336     msg->count--;
0337 }
0338
0339 static void stm32f4_i2c_read_msg(struct stm32f4_i2c_dev *i2c_dev)
0340 {
0341     struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
0342     u32 rbuf;
0343
0344     rbuf = readl_relaxed(i2c_dev->base + STM32F4_I2C_DR);
0345     *msg->buf++ = rbuf;
0346     msg->count--;
0347 }
0348
0349 static void stm32f4_i2c_terminate_xfer(struct stm32f4_i2c_dev *i2c_dev)
0350 {
0351     struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
0352     void __iomem *reg;
0353
0354     stm32f4_i2c_disable_irq(i2c_dev);
0355
0356     reg = i2c_dev->base + STM32F4_I2C_CR1;
0357     if (msg->stop)
0358         stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
0359     else
0360         stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
0361
0362     complete(&i2c_dev->complete);
0363 }
0364
0365 /**
0366  * stm32f4_i2c_handle_write() - Handle FIFO empty interrupt in case of write
0367  * @i2c_dev: Controller's private data
0368  */
0369 static void stm32f4_i2c_handle_write(struct stm32f4_i2c_dev *i2c_dev)
0370 {
0371     struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
0372     void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
0373
0374     if (msg->count) {
0375         stm32f4_i2c_write_msg(i2c_dev);
0376         if (!msg->count) {
0377             /*
0378              * Disable buffer interrupts for RX not empty and TX
0379              * empty events
0380              */
0381             stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN);
0382         }
0383     } else {
0384         stm32f4_i2c_terminate_xfer(i2c_dev);
0385     }
0386 }
0387
0388 /**
0389  * stm32f4_i2c_handle_read() - Handle FIFO empty interrupt in case of read
0390  * @i2c_dev: Controller's private data
0391  *
0392  * This function is called when a new data is received in data register
0393  */
0394 static void stm32f4_i2c_handle_read(struct stm32f4_i2c_dev *i2c_dev)
0395 {
0396     struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
0397     void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR2;
0398
0399     switch (msg->count) {
0400     case 1:
0401         stm32f4_i2c_disable_irq(i2c_dev);
0402         stm32f4_i2c_read_msg(i2c_dev);
0403         complete(&i2c_dev->complete);
0404         break;
0405     /*
0406      * For 2-byte reception, 3-byte reception and for Data N-2, N-1 and N
0407      * for N-byte reception with N > 3, we do not have to read the data
0408      * register when RX not empty event occurs as we have to wait for byte
0409      * transferred finished event before reading data.
0410      * So, here we just disable buffer interrupt in order to avoid another
0411      * system preemption due to RX not empty event.
0412      */
0413     case 2:
0414     case 3:
0415         stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR2_ITBUFEN);
0416         break;
0417     /*
0418      * For N byte reception with N > 3 we directly read data register
0419      * until N-2 data.
0420      */
0421     default:
0422         stm32f4_i2c_read_msg(i2c_dev);
0423     }
0424 }
0425
0426 /**
0427  * stm32f4_i2c_handle_rx_done() - Handle byte transfer finished interrupt
0428  * in case of read
0429  * @i2c_dev: Controller's private data
0430  *
0431  * This function is called when a new data is received in the shift register
0432  * but data register has not been read yet.
0433  */
0434 static void stm32f4_i2c_handle_rx_done(struct stm32f4_i2c_dev *i2c_dev)
0435 {
0436     struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
0437     void __iomem *reg;
0438     u32 mask;
0439     int i;
0440
0441     switch (msg->count) {
0442     case 2:
0443         /*
0444          * In order to correctly send the Stop or Repeated Start
0445          * condition on the I2C bus, the STOP/START bit has to be set
0446          * before reading the last two bytes (data N-1 and N).
0447          * After that, we could read the last two bytes, disable
0448          * remaining interrupts and notify the end of xfer to the
0449          * client
0450          */
0451         reg = i2c_dev->base + STM32F4_I2C_CR1;
0452         if (msg->stop)
0453             stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
0454         else
0455             stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
0456
0457         for (i = 2; i > 0; i--)
0458             stm32f4_i2c_read_msg(i2c_dev);
0459
0460         reg = i2c_dev->base + STM32F4_I2C_CR2;
0461         mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN;
0462         stm32f4_i2c_clr_bits(reg, mask);
0463
0464         complete(&i2c_dev->complete);
0465         break;
0466     case 3:
0467         /*
0468          * In order to correctly generate the NACK pulse after the last
0469          * received data byte, we have to enable NACK before reading N-2
0470          * data
0471          */
0472         reg = i2c_dev->base + STM32F4_I2C_CR1;
0473         stm32f4_i2c_clr_bits(reg, STM32F4_I2C_CR1_ACK);
0474         stm32f4_i2c_read_msg(i2c_dev);
0475         break;
0476     default:
0477         stm32f4_i2c_read_msg(i2c_dev);
0478     }
0479 }
0480
0481 /**
0482  * stm32f4_i2c_handle_rx_addr() - Handle address matched interrupt in case of
0483  * master receiver
0484  * @i2c_dev: Controller's private data
0485  */
0486 static void stm32f4_i2c_handle_rx_addr(struct stm32f4_i2c_dev *i2c_dev)
0487 {
0488     struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
0489     u32 cr1;
0490
0491     switch (msg->count) {
0492     case 0:
0493         stm32f4_i2c_terminate_xfer(i2c_dev);
0494
0495         /* Clear ADDR flag */
0496         readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
0497         break;
0498     case 1:
0499         /*
0500          * Single byte reception:
0501          * Enable NACK and reset POS (Acknowledge position).
0502          * Then, clear ADDR flag and set STOP or RepSTART.
0503          * In that way, the NACK and STOP or RepStart pulses will be
0504          * sent as soon as the byte will be received in shift register
0505          */
0506         cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
0507         cr1 &= ~(STM32F4_I2C_CR1_ACK | STM32F4_I2C_CR1_POS);
0508         writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
0509
0510         readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
0511
0512         if (msg->stop)
0513             cr1 |= STM32F4_I2C_CR1_STOP;
0514         else
0515             cr1 |= STM32F4_I2C_CR1_START;
0516         writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
0517         break;
0518     case 2:
0519         /*
0520          * 2-byte reception:
0521          * Enable NACK, set POS (NACK position) and clear ADDR flag.
0522          * In that way, NACK will be sent for the next byte which will
0523          * be received in the shift register instead of the current
0524          * one.
0525          */
0526         cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
0527         cr1 &= ~STM32F4_I2C_CR1_ACK;
0528         cr1 |= STM32F4_I2C_CR1_POS;
0529         writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
0530
0531         readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
0532         break;
0533
0534     default:
0535         /*
0536          * N-byte reception:
0537          * Enable ACK, reset POS (ACK position) and clear ADDR flag.
0538          * In that way, ACK will be sent as soon as the current byte
0539          * will be received in the shift register
0540          */
0541         cr1 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR1);
0542         cr1 |= STM32F4_I2C_CR1_ACK;
0543         cr1 &= ~STM32F4_I2C_CR1_POS;
0544         writel_relaxed(cr1, i2c_dev->base + STM32F4_I2C_CR1);
0545
0546         readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
0547         break;
0548     }
0549 }
0550
0551 /**
0552  * stm32f4_i2c_isr_event() - Interrupt routine for I2C bus event
0553  * @irq: interrupt number
0554  * @data: Controller's private data
0555  */
0556 static irqreturn_t stm32f4_i2c_isr_event(int irq, void *data)
0557 {
0558     struct stm32f4_i2c_dev *i2c_dev = data;
0559     struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
0560     u32 possible_status = STM32F4_I2C_SR1_ITEVTEN_MASK;
0561     u32 status, ien, event, cr2;
0562
0563     cr2 = readl_relaxed(i2c_dev->base + STM32F4_I2C_CR2);
0564     ien = cr2 & STM32F4_I2C_CR2_IRQ_MASK;
0565
0566     /* Update possible_status if buffer interrupt is enabled */
0567     if (ien & STM32F4_I2C_CR2_ITBUFEN)
0568         possible_status |= STM32F4_I2C_SR1_ITBUFEN_MASK;
0569
0570     status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
0571     event = status & possible_status;
0572     if (!event) {
0573         dev_dbg(i2c_dev->dev,
0574             "spurious evt irq (status=0x%08x, ien=0x%08x)\n",
0575             status, ien);
0576         return IRQ_NONE;
0577     }
0578
0579     /* Start condition generated */
0580     if (event & STM32F4_I2C_SR1_SB)
0581         stm32f4_i2c_write_byte(i2c_dev, msg->addr);
0582
0583     /* I2C Address sent */
0584     if (event & STM32F4_I2C_SR1_ADDR) {
0585         if (msg->addr & I2C_M_RD)
0586             stm32f4_i2c_handle_rx_addr(i2c_dev);
0587         else
0588             readl_relaxed(i2c_dev->base + STM32F4_I2C_SR2);
0589
0590         /*
0591          * Enable buffer interrupts for RX not empty and TX empty
0592          * events
0593          */
0594         cr2 |= STM32F4_I2C_CR2_ITBUFEN;
0595         writel_relaxed(cr2, i2c_dev->base + STM32F4_I2C_CR2);
0596     }
0597
0598     /* TX empty */
0599     if ((event & STM32F4_I2C_SR1_TXE) && !(msg->addr & I2C_M_RD))
0600         stm32f4_i2c_handle_write(i2c_dev);
0601
0602     /* RX not empty */
0603     if ((event & STM32F4_I2C_SR1_RXNE) && (msg->addr & I2C_M_RD))
0604         stm32f4_i2c_handle_read(i2c_dev);
0605
0606     /*
0607      * The BTF (Byte Transfer finished) event occurs when:
0608      * - in reception : a new byte is received in the shift register
0609      * but the previous byte has not been read yet from data register
0610      * - in transmission: a new byte should be sent but the data register
0611      * has not been written yet
0612      */
0613     if (event & STM32F4_I2C_SR1_BTF) {
0614         if (msg->addr & I2C_M_RD)
0615             stm32f4_i2c_handle_rx_done(i2c_dev);
0616         else
0617             stm32f4_i2c_handle_write(i2c_dev);
0618     }
0619
0620     return IRQ_HANDLED;
0621 }
0622
0623 /**
0624  * stm32f4_i2c_isr_error() - Interrupt routine for I2C bus error
0625  * @irq: interrupt number
0626  * @data: Controller's private data
0627  */
0628 static irqreturn_t stm32f4_i2c_isr_error(int irq, void *data)
0629 {
0630     struct stm32f4_i2c_dev *i2c_dev = data;
0631     struct stm32f4_i2c_msg *msg = &i2c_dev->msg;
0632     void __iomem *reg;
0633     u32 status;
0634
0635     status = readl_relaxed(i2c_dev->base + STM32F4_I2C_SR1);
0636
0637     /* Arbitration lost */
0638     if (status & STM32F4_I2C_SR1_ARLO) {
0639         status &= ~STM32F4_I2C_SR1_ARLO;
0640         writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
0641         msg->result = -EAGAIN;
0642     }
0643
0644     /*
0645      * Acknowledge failure:
0646      * In master transmitter mode a Stop must be generated by software
0647      */
0648     if (status & STM32F4_I2C_SR1_AF) {
0649         if (!(msg->addr & I2C_M_RD)) {
0650             reg = i2c_dev->base + STM32F4_I2C_CR1;
0651             stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_STOP);
0652         }
0653         status &= ~STM32F4_I2C_SR1_AF;
0654         writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
0655         msg->result = -EIO;
0656     }
0657
0658     /* Bus error */
0659     if (status & STM32F4_I2C_SR1_BERR) {
0660         status &= ~STM32F4_I2C_SR1_BERR;
0661         writel_relaxed(status, i2c_dev->base + STM32F4_I2C_SR1);
0662         msg->result = -EIO;
0663     }
0664
0665     stm32f4_i2c_disable_irq(i2c_dev);
0666     complete(&i2c_dev->complete);
0667
0668     return IRQ_HANDLED;
0669 }
0670
0671 /**
0672  * stm32f4_i2c_xfer_msg() - Transfer a single I2C message
0673  * @i2c_dev: Controller's private data
0674  * @msg: I2C message to transfer
0675  * @is_first: first message of the sequence
0676  * @is_last: last message of the sequence
0677  */
0678 static int stm32f4_i2c_xfer_msg(struct stm32f4_i2c_dev *i2c_dev,
0679                 struct i2c_msg *msg, bool is_first,
0680                 bool is_last)
0681 {
0682     struct stm32f4_i2c_msg *f4_msg = &i2c_dev->msg;
0683     void __iomem *reg = i2c_dev->base + STM32F4_I2C_CR1;
0684     unsigned long timeout;
0685     u32 mask;
0686     int ret;
0687
0688     f4_msg->addr = i2c_8bit_addr_from_msg(msg);
0689     f4_msg->buf = msg->buf;
0690     f4_msg->count = msg->len;
0691     f4_msg->result = 0;
0692     f4_msg->stop = is_last;
0693
0694     reinit_completion(&i2c_dev->complete);
0695
0696     /* Enable events and errors interrupts */
0697     mask = STM32F4_I2C_CR2_ITEVTEN | STM32F4_I2C_CR2_ITERREN;
0698     stm32f4_i2c_set_bits(i2c_dev->base + STM32F4_I2C_CR2, mask);
0699
0700     if (is_first) {
0701         ret = stm32f4_i2c_wait_free_bus(i2c_dev);
0702         if (ret)
0703             return ret;
0704
0705         /* START generation */
0706         stm32f4_i2c_set_bits(reg, STM32F4_I2C_CR1_START);
0707     }
0708
0709     timeout = wait_for_completion_timeout(&i2c_dev->complete,
0710                           i2c_dev->adap.timeout);
0711     ret = f4_msg->result;
0712
0713     if (!timeout)
0714         ret = -ETIMEDOUT;
0715
0716     return ret;
0717 }
0718
0719 /**
0720  * stm32f4_i2c_xfer() - Transfer combined I2C message
0721  * @i2c_adap: Adapter pointer to the controller
0722  * @msgs: Pointer to data to be written.
0723  * @num: Number of messages to be executed
0724  */
0725 static int stm32f4_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[],
0726                 int num)
0727 {
0728     struct stm32f4_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
0729     int ret, i;
0730
0731     ret = clk_enable(i2c_dev->clk);
0732     if (ret) {
0733         dev_err(i2c_dev->dev, "Failed to enable clock\n");
0734         return ret;
0735     }
0736
0737     for (i = 0; i < num && !ret; i++)
0738         ret = stm32f4_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0,
0739                        i == num - 1);
0740
0741     clk_disable(i2c_dev->clk);
0742
0743     return (ret < 0) ? ret : num;
0744 }
0745
0746 static u32 stm32f4_i2c_func(struct i2c_adapter *adap)
0747 {
0748     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0749 }
0750
0751 static const struct i2c_algorithm stm32f4_i2c_algo = {
0752     .master_xfer = stm32f4_i2c_xfer,
0753     .functionality = stm32f4_i2c_func,
0754 };
0755
0756 static int stm32f4_i2c_probe(struct platform_device *pdev)
0757 {
0758     struct device_node *np = pdev->dev.of_node;
0759     struct stm32f4_i2c_dev *i2c_dev;
0760     struct resource *res;
0761     u32 irq_event, irq_error, clk_rate;
0762     struct i2c_adapter *adap;
0763     struct reset_control *rst;
0764     int ret;
0765
0766     i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
0767     if (!i2c_dev)
0768         return -ENOMEM;
0769
0770     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0771     i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
0772     if (IS_ERR(i2c_dev->base))
0773         return PTR_ERR(i2c_dev->base);
0774
0775     irq_event = irq_of_parse_and_map(np, 0);
0776     if (!irq_event) {
0777         dev_err(&pdev->dev, "IRQ event missing or invalid\n");
0778         return -EINVAL;
0779     }
0780
0781     irq_error = irq_of_parse_and_map(np, 1);
0782     if (!irq_error) {
0783         dev_err(&pdev->dev, "IRQ error missing or invalid\n");
0784         return -EINVAL;
0785     }
0786
0787     i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
0788     if (IS_ERR(i2c_dev->clk)) {
0789         dev_err(&pdev->dev, "Error: Missing controller clock\n");
0790         return PTR_ERR(i2c_dev->clk);
0791     }
0792     ret = clk_prepare_enable(i2c_dev->clk);
0793     if (ret) {
0794         dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n");
0795         return ret;
0796     }
0797
0798     rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0799     if (IS_ERR(rst)) {
0800         ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
0801                     "Error: Missing reset ctrl\n");
0802         goto clk_free;
0803     }
0804     reset_control_assert(rst);
0805     udelay(2);
0806     reset_control_deassert(rst);
0807
0808     i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
0809     ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
0810     if (!ret && clk_rate >= I2C_MAX_FAST_MODE_FREQ)
0811         i2c_dev->speed = STM32_I2C_SPEED_FAST;
0812
0813     i2c_dev->dev = &pdev->dev;
0814
0815     ret = devm_request_irq(&pdev->dev, irq_event, stm32f4_i2c_isr_event, 0,
0816                    pdev->name, i2c_dev);
0817     if (ret) {
0818         dev_err(&pdev->dev, "Failed to request irq event %i\n",
0819             irq_event);
0820         goto clk_free;
0821     }
0822
0823     ret = devm_request_irq(&pdev->dev, irq_error, stm32f4_i2c_isr_error, 0,
0824                    pdev->name, i2c_dev);
0825     if (ret) {
0826         dev_err(&pdev->dev, "Failed to request irq error %i\n",
0827             irq_error);
0828         goto clk_free;
0829     }
0830
0831     ret = stm32f4_i2c_hw_config(i2c_dev);
0832     if (ret)
0833         goto clk_free;
0834
0835     adap = &i2c_dev->adap;
0836     i2c_set_adapdata(adap, i2c_dev);
0837     snprintf(adap->name, sizeof(adap->name), "STM32 I2C(%pa)", &res->start);
0838     adap->owner = THIS_MODULE;
0839     adap->timeout = 2 * HZ;
0840     adap->retries = 0;
0841     adap->algo = &stm32f4_i2c_algo;
0842     adap->dev.parent = &pdev->dev;
0843     adap->dev.of_node = pdev->dev.of_node;
0844
0845     init_completion(&i2c_dev->complete);
0846
0847     ret = i2c_add_adapter(adap);
0848     if (ret)
0849         goto clk_free;
0850
0851     platform_set_drvdata(pdev, i2c_dev);
0852
0853     clk_disable(i2c_dev->clk);
0854
0855     dev_info(i2c_dev->dev, "STM32F4 I2C driver registered\n");
0856
0857     return 0;
0858
0859 clk_free:
0860     clk_disable_unprepare(i2c_dev->clk);
0861     return ret;
0862 }
0863
0864 static int stm32f4_i2c_remove(struct platform_device *pdev)
0865 {
0866     struct stm32f4_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
0867
0868     i2c_del_adapter(&i2c_dev->adap);
0869
0870     clk_unprepare(i2c_dev->clk);
0871
0872     return 0;
0873 }
0874
0875 static const struct of_device_id stm32f4_i2c_match[] = {
0876     { .compatible = "st,stm32f4-i2c", },
0877     {},
0878 };
0879 MODULE_DEVICE_TABLE(of, stm32f4_i2c_match);
0880
0881 static struct platform_driver stm32f4_i2c_driver = {
0882     .driver = {
0883         .name = "stm32f4-i2c",
0884         .of_match_table = stm32f4_i2c_match,
0885     },
0886     .probe = stm32f4_i2c_probe,
0887     .remove = stm32f4_i2c_remove,
0888 };
0889
0890 module_platform_driver(stm32f4_i2c_driver);
0891
0892 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
0893 MODULE_DESCRIPTION("STMicroelectronics STM32F4 I2C driver");
0894 MODULE_LICENSE("GPL v2");