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0001 /*
0002  * Copyright (C) 2017 Spreadtrum Communications Inc.
0003  *
0004  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/delay.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/i2c.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/pm_runtime.h>
0020 
0021 #define I2C_CTL         0x00
0022 #define I2C_ADDR_CFG        0x04
0023 #define I2C_COUNT       0x08
0024 #define I2C_RX          0x0c
0025 #define I2C_TX          0x10
0026 #define I2C_STATUS      0x14
0027 #define I2C_HSMODE_CFG      0x18
0028 #define I2C_VERSION     0x1c
0029 #define ADDR_DVD0       0x20
0030 #define ADDR_DVD1       0x24
0031 #define ADDR_STA0_DVD       0x28
0032 #define ADDR_RST        0x2c
0033 
0034 /* I2C_CTL */
0035 #define STP_EN          BIT(20)
0036 #define FIFO_AF_LVL_MASK    GENMASK(19, 16)
0037 #define FIFO_AF_LVL     16
0038 #define FIFO_AE_LVL_MASK    GENMASK(15, 12)
0039 #define FIFO_AE_LVL     12
0040 #define I2C_DMA_EN      BIT(11)
0041 #define FULL_INTEN      BIT(10)
0042 #define EMPTY_INTEN     BIT(9)
0043 #define I2C_DVD_OPT     BIT(8)
0044 #define I2C_OUT_OPT     BIT(7)
0045 #define I2C_TRIM_OPT        BIT(6)
0046 #define I2C_HS_MODE     BIT(4)
0047 #define I2C_MODE        BIT(3)
0048 #define I2C_EN          BIT(2)
0049 #define I2C_INT_EN      BIT(1)
0050 #define I2C_START       BIT(0)
0051 
0052 /* I2C_STATUS */
0053 #define SDA_IN          BIT(21)
0054 #define SCL_IN          BIT(20)
0055 #define FIFO_FULL       BIT(4)
0056 #define FIFO_EMPTY      BIT(3)
0057 #define I2C_INT         BIT(2)
0058 #define I2C_RX_ACK      BIT(1)
0059 #define I2C_BUSY        BIT(0)
0060 
0061 /* ADDR_RST */
0062 #define I2C_RST         BIT(0)
0063 
0064 #define I2C_FIFO_DEEP       12
0065 #define I2C_FIFO_FULL_THLD  15
0066 #define I2C_FIFO_EMPTY_THLD 4
0067 #define I2C_DATA_STEP       8
0068 #define I2C_ADDR_DVD0_CALC(high, low)   \
0069     ((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
0070 #define I2C_ADDR_DVD1_CALC(high, low)   \
0071     (((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
0072 
0073 /* timeout (ms) for pm runtime autosuspend */
0074 #define SPRD_I2C_PM_TIMEOUT 1000
0075 /* timeout (ms) for transfer message */
0076 #define I2C_XFER_TIMEOUT    1000
0077 
0078 /* SPRD i2c data structure */
0079 struct sprd_i2c {
0080     struct i2c_adapter adap;
0081     struct device *dev;
0082     void __iomem *base;
0083     struct i2c_msg *msg;
0084     struct clk *clk;
0085     u32 src_clk;
0086     u32 bus_freq;
0087     struct completion complete;
0088     u8 *buf;
0089     u32 count;
0090     int irq;
0091     int err;
0092 };
0093 
0094 static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
0095 {
0096     writel(count, i2c_dev->base + I2C_COUNT);
0097 }
0098 
0099 static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
0100 {
0101     u32 tmp = readl(i2c_dev->base + I2C_CTL);
0102 
0103     if (stop)
0104         writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
0105     else
0106         writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
0107 }
0108 
0109 static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
0110 {
0111     u32 tmp = readl(i2c_dev->base + I2C_CTL);
0112 
0113     writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
0114 }
0115 
0116 static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
0117 {
0118     u32 tmp = readl(i2c_dev->base + I2C_STATUS);
0119 
0120     writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
0121 }
0122 
0123 static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
0124 {
0125     u32 tmp = readl(i2c_dev->base + I2C_STATUS);
0126 
0127     writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
0128 }
0129 
0130 static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
0131 {
0132     writel(I2C_RST, i2c_dev->base + ADDR_RST);
0133 }
0134 
0135 static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
0136 {
0137     writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
0138 }
0139 
0140 static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
0141 {
0142     u32 i;
0143 
0144     for (i = 0; i < len; i++)
0145         writeb(buf[i], i2c_dev->base + I2C_TX);
0146 }
0147 
0148 static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
0149 {
0150     u32 i;
0151 
0152     for (i = 0; i < len; i++)
0153         buf[i] = readb(i2c_dev->base + I2C_RX);
0154 }
0155 
0156 static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
0157 {
0158     u32 tmp = readl(i2c_dev->base + I2C_CTL);
0159 
0160     tmp &= ~FIFO_AF_LVL_MASK;
0161     tmp |= full_thld << FIFO_AF_LVL;
0162     writel(tmp, i2c_dev->base + I2C_CTL);
0163 };
0164 
0165 static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
0166 {
0167     u32 tmp = readl(i2c_dev->base + I2C_CTL);
0168 
0169     tmp &= ~FIFO_AE_LVL_MASK;
0170     tmp |= empty_thld << FIFO_AE_LVL;
0171     writel(tmp, i2c_dev->base + I2C_CTL);
0172 };
0173 
0174 static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
0175 {
0176     u32 tmp = readl(i2c_dev->base + I2C_CTL);
0177 
0178     if (enable)
0179         tmp |= FULL_INTEN;
0180     else
0181         tmp &= ~FULL_INTEN;
0182 
0183     writel(tmp, i2c_dev->base + I2C_CTL);
0184 };
0185 
0186 static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
0187 {
0188     u32 tmp = readl(i2c_dev->base + I2C_CTL);
0189 
0190     if (enable)
0191         tmp |= EMPTY_INTEN;
0192     else
0193         tmp &= ~EMPTY_INTEN;
0194 
0195     writel(tmp, i2c_dev->base + I2C_CTL);
0196 };
0197 
0198 static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
0199 {
0200     u32 tmp = readl(i2c_dev->base + I2C_CTL);
0201 
0202     writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
0203 }
0204 
0205 static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
0206 {
0207     u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
0208 
0209     writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
0210 }
0211 
0212 static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
0213 {
0214     u32 i2c_count = i2c_dev->count;
0215     u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
0216     struct i2c_msg *msg = i2c_dev->msg;
0217 
0218     if (msg->flags & I2C_M_RD) {
0219         sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
0220         i2c_dev->count -= I2C_FIFO_FULL_THLD;
0221         i2c_dev->buf += I2C_FIFO_FULL_THLD;
0222 
0223         /*
0224          * If the read data count is larger than rx fifo full threshold,
0225          * we should enable the rx fifo full interrupt to read data
0226          * again.
0227          */
0228         if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
0229             sprd_i2c_set_fifo_full_int(i2c_dev, 1);
0230     } else {
0231         sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
0232         i2c_dev->buf += need_tran;
0233         i2c_dev->count -= need_tran;
0234 
0235         /*
0236          * If the write data count is arger than tx fifo depth which
0237          * means we can not write all data in one time, then we should
0238          * enable the tx fifo empty interrupt to write again.
0239          */
0240         if (i2c_count > I2C_FIFO_DEEP)
0241             sprd_i2c_set_fifo_empty_int(i2c_dev, 1);
0242     }
0243 }
0244 
0245 static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap,
0246                    struct i2c_msg *msg, bool is_last_msg)
0247 {
0248     struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
0249     unsigned long time_left;
0250 
0251     i2c_dev->msg = msg;
0252     i2c_dev->buf = msg->buf;
0253     i2c_dev->count = msg->len;
0254 
0255     reinit_completion(&i2c_dev->complete);
0256     sprd_i2c_reset_fifo(i2c_dev);
0257     sprd_i2c_set_devaddr(i2c_dev, msg);
0258     sprd_i2c_set_count(i2c_dev, msg->len);
0259 
0260     if (msg->flags & I2C_M_RD) {
0261         sprd_i2c_opt_mode(i2c_dev, 1);
0262         sprd_i2c_send_stop(i2c_dev, 1);
0263     } else {
0264         sprd_i2c_opt_mode(i2c_dev, 0);
0265         sprd_i2c_send_stop(i2c_dev, !!is_last_msg);
0266     }
0267 
0268     /*
0269      * We should enable rx fifo full interrupt to get data when receiving
0270      * full data.
0271      */
0272     if (msg->flags & I2C_M_RD)
0273         sprd_i2c_set_fifo_full_int(i2c_dev, 1);
0274     else
0275         sprd_i2c_data_transfer(i2c_dev);
0276 
0277     sprd_i2c_opt_start(i2c_dev);
0278 
0279     time_left = wait_for_completion_timeout(&i2c_dev->complete,
0280                 msecs_to_jiffies(I2C_XFER_TIMEOUT));
0281     if (!time_left)
0282         return -ETIMEDOUT;
0283 
0284     return i2c_dev->err;
0285 }
0286 
0287 static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
0288                 struct i2c_msg *msgs, int num)
0289 {
0290     struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
0291     int im, ret;
0292 
0293     ret = pm_runtime_resume_and_get(i2c_dev->dev);
0294     if (ret < 0)
0295         return ret;
0296 
0297     for (im = 0; im < num - 1; im++) {
0298         ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0);
0299         if (ret)
0300             goto err_msg;
0301     }
0302 
0303     ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1);
0304 
0305 err_msg:
0306     pm_runtime_mark_last_busy(i2c_dev->dev);
0307     pm_runtime_put_autosuspend(i2c_dev->dev);
0308 
0309     return ret < 0 ? ret : im;
0310 }
0311 
0312 static u32 sprd_i2c_func(struct i2c_adapter *adap)
0313 {
0314     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0315 }
0316 
0317 static const struct i2c_algorithm sprd_i2c_algo = {
0318     .master_xfer = sprd_i2c_master_xfer,
0319     .functionality = sprd_i2c_func,
0320 };
0321 
0322 static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq)
0323 {
0324     u32 apb_clk = i2c_dev->src_clk;
0325     /*
0326      * From I2C databook, the prescale calculation formula:
0327      * prescale = freq_i2c / (4 * freq_scl) - 1;
0328      */
0329     u32 i2c_dvd = apb_clk / (4 * freq) - 1;
0330     /*
0331      * From I2C databook, the high period of SCL clock is recommended as
0332      * 40% (2/5), and the low period of SCL clock is recommended as 60%
0333      * (3/5), then the formula should be:
0334      * high = (prescale * 2 * 2) / 5
0335      * low = (prescale * 2 * 3) / 5
0336      */
0337     u32 high = ((i2c_dvd << 1) * 2) / 5;
0338     u32 low = ((i2c_dvd << 1) * 3) / 5;
0339     u32 div0 = I2C_ADDR_DVD0_CALC(high, low);
0340     u32 div1 = I2C_ADDR_DVD1_CALC(high, low);
0341 
0342     writel(div0, i2c_dev->base + ADDR_DVD0);
0343     writel(div1, i2c_dev->base + ADDR_DVD1);
0344 
0345     /* Start hold timing = hold time(us) * source clock */
0346     if (freq == I2C_MAX_FAST_MODE_FREQ)
0347         writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
0348     else if (freq == I2C_MAX_STANDARD_MODE_FREQ)
0349         writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
0350 }
0351 
0352 static void sprd_i2c_enable(struct sprd_i2c *i2c_dev)
0353 {
0354     u32 tmp = I2C_DVD_OPT;
0355 
0356     writel(tmp, i2c_dev->base + I2C_CTL);
0357 
0358     sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD);
0359     sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD);
0360 
0361     sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq);
0362     sprd_i2c_reset_fifo(i2c_dev);
0363     sprd_i2c_clear_irq(i2c_dev);
0364 
0365     tmp = readl(i2c_dev->base + I2C_CTL);
0366     writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
0367 }
0368 
0369 static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id)
0370 {
0371     struct sprd_i2c *i2c_dev = dev_id;
0372     struct i2c_msg *msg = i2c_dev->msg;
0373     bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
0374     u32 i2c_tran;
0375 
0376     if (msg->flags & I2C_M_RD)
0377         i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
0378     else
0379         i2c_tran = i2c_dev->count;
0380 
0381     /*
0382      * If we got one ACK from slave when writing data, and we did not
0383      * finish this transmission (i2c_tran is not zero), then we should
0384      * continue to write data.
0385      *
0386      * For reading data, ack is always true, if i2c_tran is not 0 which
0387      * means we still need to contine to read data from slave.
0388      */
0389     if (i2c_tran && ack) {
0390         sprd_i2c_data_transfer(i2c_dev);
0391         return IRQ_HANDLED;
0392     }
0393 
0394     i2c_dev->err = 0;
0395 
0396     /*
0397      * If we did not get one ACK from slave when writing data, we should
0398      * return -EIO to notify users.
0399      */
0400     if (!ack)
0401         i2c_dev->err = -EIO;
0402     else if (msg->flags & I2C_M_RD && i2c_dev->count)
0403         sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count);
0404 
0405     /* Transmission is done and clear ack and start operation */
0406     sprd_i2c_clear_ack(i2c_dev);
0407     sprd_i2c_clear_start(i2c_dev);
0408     complete(&i2c_dev->complete);
0409 
0410     return IRQ_HANDLED;
0411 }
0412 
0413 static irqreturn_t sprd_i2c_isr(int irq, void *dev_id)
0414 {
0415     struct sprd_i2c *i2c_dev = dev_id;
0416     struct i2c_msg *msg = i2c_dev->msg;
0417     bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
0418     u32 i2c_tran;
0419 
0420     if (msg->flags & I2C_M_RD)
0421         i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
0422     else
0423         i2c_tran = i2c_dev->count;
0424 
0425     /*
0426      * If we did not get one ACK from slave when writing data, then we
0427      * should finish this transmission since we got some errors.
0428      *
0429      * When writing data, if i2c_tran == 0 which means we have writen
0430      * done all data, then we can finish this transmission.
0431      *
0432      * When reading data, if conut < rx fifo full threshold, which
0433      * means we can read all data in one time, then we can finish this
0434      * transmission too.
0435      */
0436     if (!i2c_tran || !ack) {
0437         sprd_i2c_clear_start(i2c_dev);
0438         sprd_i2c_clear_irq(i2c_dev);
0439     }
0440 
0441     sprd_i2c_set_fifo_empty_int(i2c_dev, 0);
0442     sprd_i2c_set_fifo_full_int(i2c_dev, 0);
0443 
0444     return IRQ_WAKE_THREAD;
0445 }
0446 
0447 static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev)
0448 {
0449     struct clk *clk_i2c, *clk_parent;
0450 
0451     clk_i2c = devm_clk_get(i2c_dev->dev, "i2c");
0452     if (IS_ERR(clk_i2c)) {
0453         dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n",
0454              i2c_dev->adap.nr);
0455         clk_i2c = NULL;
0456     }
0457 
0458     clk_parent = devm_clk_get(i2c_dev->dev, "source");
0459     if (IS_ERR(clk_parent)) {
0460         dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n",
0461              i2c_dev->adap.nr);
0462         clk_parent = NULL;
0463     }
0464 
0465     if (clk_set_parent(clk_i2c, clk_parent))
0466         i2c_dev->src_clk = clk_get_rate(clk_i2c);
0467     else
0468         i2c_dev->src_clk = 26000000;
0469 
0470     dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n",
0471         i2c_dev->adap.nr, i2c_dev->src_clk);
0472 
0473     i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable");
0474     if (IS_ERR(i2c_dev->clk)) {
0475         dev_err(i2c_dev->dev, "i2c%d can't get the enable clock\n",
0476             i2c_dev->adap.nr);
0477         return PTR_ERR(i2c_dev->clk);
0478     }
0479 
0480     return 0;
0481 }
0482 
0483 static int sprd_i2c_probe(struct platform_device *pdev)
0484 {
0485     struct device *dev = &pdev->dev;
0486     struct sprd_i2c *i2c_dev;
0487     u32 prop;
0488     int ret;
0489 
0490     pdev->id = of_alias_get_id(dev->of_node, "i2c");
0491 
0492     i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL);
0493     if (!i2c_dev)
0494         return -ENOMEM;
0495 
0496     i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
0497     if (IS_ERR(i2c_dev->base))
0498         return PTR_ERR(i2c_dev->base);
0499 
0500     i2c_dev->irq = platform_get_irq(pdev, 0);
0501     if (i2c_dev->irq < 0)
0502         return i2c_dev->irq;
0503 
0504     i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
0505     init_completion(&i2c_dev->complete);
0506     snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
0507          "%s", "sprd-i2c");
0508 
0509     i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
0510     i2c_dev->adap.owner = THIS_MODULE;
0511     i2c_dev->dev = dev;
0512     i2c_dev->adap.retries = 3;
0513     i2c_dev->adap.algo = &sprd_i2c_algo;
0514     i2c_dev->adap.algo_data = i2c_dev;
0515     i2c_dev->adap.dev.parent = dev;
0516     i2c_dev->adap.nr = pdev->id;
0517     i2c_dev->adap.dev.of_node = dev->of_node;
0518 
0519     if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop))
0520         i2c_dev->bus_freq = prop;
0521 
0522     /* We only support 100k and 400k now, otherwise will return error. */
0523     if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ &&
0524         i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ)
0525         return -EINVAL;
0526 
0527     ret = sprd_i2c_clk_init(i2c_dev);
0528     if (ret)
0529         return ret;
0530 
0531     platform_set_drvdata(pdev, i2c_dev);
0532 
0533     ret = clk_prepare_enable(i2c_dev->clk);
0534     if (ret)
0535         return ret;
0536 
0537     sprd_i2c_enable(i2c_dev);
0538 
0539     pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT);
0540     pm_runtime_use_autosuspend(i2c_dev->dev);
0541     pm_runtime_set_active(i2c_dev->dev);
0542     pm_runtime_enable(i2c_dev->dev);
0543 
0544     ret = pm_runtime_get_sync(i2c_dev->dev);
0545     if (ret < 0)
0546         goto err_rpm_put;
0547 
0548     ret = devm_request_threaded_irq(dev, i2c_dev->irq,
0549         sprd_i2c_isr, sprd_i2c_isr_thread,
0550         IRQF_NO_SUSPEND | IRQF_ONESHOT,
0551         pdev->name, i2c_dev);
0552     if (ret) {
0553         dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq);
0554         goto err_rpm_put;
0555     }
0556 
0557     ret = i2c_add_numbered_adapter(&i2c_dev->adap);
0558     if (ret) {
0559         dev_err(&pdev->dev, "add adapter failed\n");
0560         goto err_rpm_put;
0561     }
0562 
0563     pm_runtime_mark_last_busy(i2c_dev->dev);
0564     pm_runtime_put_autosuspend(i2c_dev->dev);
0565     return 0;
0566 
0567 err_rpm_put:
0568     pm_runtime_put_noidle(i2c_dev->dev);
0569     pm_runtime_disable(i2c_dev->dev);
0570     clk_disable_unprepare(i2c_dev->clk);
0571     return ret;
0572 }
0573 
0574 static int sprd_i2c_remove(struct platform_device *pdev)
0575 {
0576     struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
0577     int ret;
0578 
0579     ret = pm_runtime_resume_and_get(i2c_dev->dev);
0580     if (ret < 0)
0581         return ret;
0582 
0583     i2c_del_adapter(&i2c_dev->adap);
0584     clk_disable_unprepare(i2c_dev->clk);
0585 
0586     pm_runtime_put_noidle(i2c_dev->dev);
0587     pm_runtime_disable(i2c_dev->dev);
0588 
0589     return 0;
0590 }
0591 
0592 static int __maybe_unused sprd_i2c_suspend_noirq(struct device *dev)
0593 {
0594     struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
0595 
0596     i2c_mark_adapter_suspended(&i2c_dev->adap);
0597     return pm_runtime_force_suspend(dev);
0598 }
0599 
0600 static int __maybe_unused sprd_i2c_resume_noirq(struct device *dev)
0601 {
0602     struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
0603 
0604     i2c_mark_adapter_resumed(&i2c_dev->adap);
0605     return pm_runtime_force_resume(dev);
0606 }
0607 
0608 static int __maybe_unused sprd_i2c_runtime_suspend(struct device *dev)
0609 {
0610     struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
0611 
0612     clk_disable_unprepare(i2c_dev->clk);
0613 
0614     return 0;
0615 }
0616 
0617 static int __maybe_unused sprd_i2c_runtime_resume(struct device *dev)
0618 {
0619     struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
0620     int ret;
0621 
0622     ret = clk_prepare_enable(i2c_dev->clk);
0623     if (ret)
0624         return ret;
0625 
0626     sprd_i2c_enable(i2c_dev);
0627 
0628     return 0;
0629 }
0630 
0631 static const struct dev_pm_ops sprd_i2c_pm_ops = {
0632     SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend,
0633                sprd_i2c_runtime_resume, NULL)
0634 
0635     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq,
0636                       sprd_i2c_resume_noirq)
0637 };
0638 
0639 static const struct of_device_id sprd_i2c_of_match[] = {
0640     { .compatible = "sprd,sc9860-i2c", },
0641     {},
0642 };
0643 MODULE_DEVICE_TABLE(of, sprd_i2c_of_match);
0644 
0645 static struct platform_driver sprd_i2c_driver = {
0646     .probe = sprd_i2c_probe,
0647     .remove = sprd_i2c_remove,
0648     .driver = {
0649            .name = "sprd-i2c",
0650            .of_match_table = sprd_i2c_of_match,
0651            .pm = &sprd_i2c_pm_ops,
0652     },
0653 };
0654 
0655 module_platform_driver(sprd_i2c_driver);
0656 
0657 MODULE_DESCRIPTION("Spreadtrum I2C master controller driver");
0658 MODULE_LICENSE("GPL v2");
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