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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* linux/drivers/i2c/busses/i2c-s3c2410.c
0003  *
0004  * Copyright (C) 2004,2005,2009 Simtec Electronics
0005  *  Ben Dooks <ben@simtec.co.uk>
0006  *
0007  * S3C2410 I2C Controller
0008 */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 
0013 #include <linux/i2c.h>
0014 #include <linux/init.h>
0015 #include <linux/time.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/delay.h>
0018 #include <linux/errno.h>
0019 #include <linux/err.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/clk.h>
0023 #include <linux/cpufreq.h>
0024 #include <linux/slab.h>
0025 #include <linux/io.h>
0026 #include <linux/of.h>
0027 #include <linux/of_device.h>
0028 #include <linux/gpio/consumer.h>
0029 #include <linux/pinctrl/consumer.h>
0030 #include <linux/mfd/syscon.h>
0031 #include <linux/regmap.h>
0032 
0033 #include <asm/irq.h>
0034 
0035 #include <linux/platform_data/i2c-s3c2410.h>
0036 
0037 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
0038 
0039 #define S3C2410_IICCON          0x00
0040 #define S3C2410_IICSTAT         0x04
0041 #define S3C2410_IICADD          0x08
0042 #define S3C2410_IICDS           0x0C
0043 #define S3C2440_IICLC           0x10
0044 
0045 #define S3C2410_IICCON_ACKEN        (1 << 7)
0046 #define S3C2410_IICCON_TXDIV_16     (0 << 6)
0047 #define S3C2410_IICCON_TXDIV_512    (1 << 6)
0048 #define S3C2410_IICCON_IRQEN        (1 << 5)
0049 #define S3C2410_IICCON_IRQPEND      (1 << 4)
0050 #define S3C2410_IICCON_SCALE(x)     ((x) & 0xf)
0051 #define S3C2410_IICCON_SCALEMASK    (0xf)
0052 
0053 #define S3C2410_IICSTAT_MASTER_RX   (2 << 6)
0054 #define S3C2410_IICSTAT_MASTER_TX   (3 << 6)
0055 #define S3C2410_IICSTAT_SLAVE_RX    (0 << 6)
0056 #define S3C2410_IICSTAT_SLAVE_TX    (1 << 6)
0057 #define S3C2410_IICSTAT_MODEMASK    (3 << 6)
0058 
0059 #define S3C2410_IICSTAT_START       (1 << 5)
0060 #define S3C2410_IICSTAT_BUSBUSY     (1 << 5)
0061 #define S3C2410_IICSTAT_TXRXEN      (1 << 4)
0062 #define S3C2410_IICSTAT_ARBITR      (1 << 3)
0063 #define S3C2410_IICSTAT_ASSLAVE     (1 << 2)
0064 #define S3C2410_IICSTAT_ADDR0       (1 << 1)
0065 #define S3C2410_IICSTAT_LASTBIT     (1 << 0)
0066 
0067 #define S3C2410_IICLC_SDA_DELAY0    (0 << 0)
0068 #define S3C2410_IICLC_SDA_DELAY5    (1 << 0)
0069 #define S3C2410_IICLC_SDA_DELAY10   (2 << 0)
0070 #define S3C2410_IICLC_SDA_DELAY15   (3 << 0)
0071 #define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
0072 
0073 #define S3C2410_IICLC_FILTER_ON     (1 << 2)
0074 
0075 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
0076 #define QUIRK_S3C2440       (1 << 0)
0077 #define QUIRK_HDMIPHY       (1 << 1)
0078 #define QUIRK_NO_GPIO       (1 << 2)
0079 #define QUIRK_POLL      (1 << 3)
0080 
0081 /* Max time to wait for bus to become idle after a xfer (in us) */
0082 #define S3C2410_IDLE_TIMEOUT    5000
0083 
0084 /* Exynos5 Sysreg offset */
0085 #define EXYNOS5_SYS_I2C_CFG 0x0234
0086 
0087 /* i2c controller state */
0088 enum s3c24xx_i2c_state {
0089     STATE_IDLE,
0090     STATE_START,
0091     STATE_READ,
0092     STATE_WRITE,
0093     STATE_STOP
0094 };
0095 
0096 struct s3c24xx_i2c {
0097     wait_queue_head_t   wait;
0098     kernel_ulong_t      quirks;
0099 
0100     struct i2c_msg      *msg;
0101     unsigned int        msg_num;
0102     unsigned int        msg_idx;
0103     unsigned int        msg_ptr;
0104 
0105     unsigned int        tx_setup;
0106     unsigned int        irq;
0107 
0108     enum s3c24xx_i2c_state  state;
0109     unsigned long       clkrate;
0110 
0111     void __iomem        *regs;
0112     struct clk      *clk;
0113     struct device       *dev;
0114     struct i2c_adapter  adap;
0115 
0116     struct s3c2410_platform_i2c *pdata;
0117     struct gpio_desc    *gpios[2];
0118     struct pinctrl          *pctrl;
0119 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
0120     struct notifier_block   freq_transition;
0121 #endif
0122     struct regmap       *sysreg;
0123     unsigned int        sys_i2c_cfg;
0124 };
0125 
0126 static const struct platform_device_id s3c24xx_driver_ids[] = {
0127     {
0128         .name       = "s3c2410-i2c",
0129         .driver_data    = 0,
0130     }, {
0131         .name       = "s3c2440-i2c",
0132         .driver_data    = QUIRK_S3C2440,
0133     }, {
0134         .name       = "s3c2440-hdmiphy-i2c",
0135         .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
0136     }, { },
0137 };
0138 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
0139 
0140 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
0141 
0142 #ifdef CONFIG_OF
0143 static const struct of_device_id s3c24xx_i2c_match[] = {
0144     { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
0145     { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
0146     { .compatible = "samsung,s3c2440-hdmiphy-i2c",
0147       .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
0148     { .compatible = "samsung,exynos5-sata-phy-i2c",
0149       .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
0150     {},
0151 };
0152 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
0153 #endif
0154 
0155 /*
0156  * Get controller type either from device tree or platform device variant.
0157  */
0158 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
0159 {
0160     if (pdev->dev.of_node)
0161         return (kernel_ulong_t)of_device_get_match_data(&pdev->dev);
0162 
0163     return platform_get_device_id(pdev)->driver_data;
0164 }
0165 
0166 /*
0167  * Complete the message and wake up the caller, using the given return code,
0168  * or zero to mean ok.
0169  */
0170 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
0171 {
0172     dev_dbg(i2c->dev, "master_complete %d\n", ret);
0173 
0174     i2c->msg_ptr = 0;
0175     i2c->msg = NULL;
0176     i2c->msg_idx++;
0177     i2c->msg_num = 0;
0178     if (ret)
0179         i2c->msg_idx = ret;
0180 
0181     if (!(i2c->quirks & QUIRK_POLL))
0182         wake_up(&i2c->wait);
0183 }
0184 
0185 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
0186 {
0187     unsigned long tmp;
0188 
0189     tmp = readl(i2c->regs + S3C2410_IICCON);
0190     writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
0191 }
0192 
0193 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
0194 {
0195     unsigned long tmp;
0196 
0197     tmp = readl(i2c->regs + S3C2410_IICCON);
0198     writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
0199 }
0200 
0201 /* irq enable/disable functions */
0202 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
0203 {
0204     unsigned long tmp;
0205 
0206     tmp = readl(i2c->regs + S3C2410_IICCON);
0207     writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
0208 }
0209 
0210 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
0211 {
0212     unsigned long tmp;
0213 
0214     tmp = readl(i2c->regs + S3C2410_IICCON);
0215     writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
0216 }
0217 
0218 static bool is_ack(struct s3c24xx_i2c *i2c)
0219 {
0220     int tries;
0221 
0222     for (tries = 50; tries; --tries) {
0223         if (readl(i2c->regs + S3C2410_IICCON)
0224             & S3C2410_IICCON_IRQPEND) {
0225             if (!(readl(i2c->regs + S3C2410_IICSTAT)
0226                 & S3C2410_IICSTAT_LASTBIT))
0227                 return true;
0228         }
0229         usleep_range(1000, 2000);
0230     }
0231     dev_err(i2c->dev, "ack was not received\n");
0232     return false;
0233 }
0234 
0235 /*
0236  * put the start of a message onto the bus
0237  */
0238 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
0239                       struct i2c_msg *msg)
0240 {
0241     unsigned int addr = (msg->addr & 0x7f) << 1;
0242     unsigned long stat;
0243     unsigned long iiccon;
0244 
0245     stat = 0;
0246     stat |=  S3C2410_IICSTAT_TXRXEN;
0247 
0248     if (msg->flags & I2C_M_RD) {
0249         stat |= S3C2410_IICSTAT_MASTER_RX;
0250         addr |= 1;
0251     } else
0252         stat |= S3C2410_IICSTAT_MASTER_TX;
0253 
0254     if (msg->flags & I2C_M_REV_DIR_ADDR)
0255         addr ^= 1;
0256 
0257     /* todo - check for whether ack wanted or not */
0258     s3c24xx_i2c_enable_ack(i2c);
0259 
0260     iiccon = readl(i2c->regs + S3C2410_IICCON);
0261     writel(stat, i2c->regs + S3C2410_IICSTAT);
0262 
0263     dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
0264     writeb(addr, i2c->regs + S3C2410_IICDS);
0265 
0266     /*
0267      * delay here to ensure the data byte has gotten onto the bus
0268      * before the transaction is started
0269      */
0270     ndelay(i2c->tx_setup);
0271 
0272     dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
0273     writel(iiccon, i2c->regs + S3C2410_IICCON);
0274 
0275     stat |= S3C2410_IICSTAT_START;
0276     writel(stat, i2c->regs + S3C2410_IICSTAT);
0277 
0278     if (i2c->quirks & QUIRK_POLL) {
0279         while ((i2c->msg_num != 0) && is_ack(i2c)) {
0280             i2c_s3c_irq_nextbyte(i2c, stat);
0281             stat = readl(i2c->regs + S3C2410_IICSTAT);
0282 
0283             if (stat & S3C2410_IICSTAT_ARBITR)
0284                 dev_err(i2c->dev, "deal with arbitration loss\n");
0285         }
0286     }
0287 }
0288 
0289 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
0290 {
0291     unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
0292 
0293     dev_dbg(i2c->dev, "STOP\n");
0294 
0295     /*
0296      * The datasheet says that the STOP sequence should be:
0297      *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
0298      *  2) I2CCON.4 = 0 - Clear IRQPEND
0299      *  3) Wait until the stop condition takes effect.
0300      *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
0301      *
0302      * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
0303      *
0304      * However, after much experimentation, it appears that:
0305      * a) normal buses automatically clear BUSY and transition from
0306      *    Master->Slave when they complete generating a STOP condition.
0307      *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
0308      *    after starting the STOP generation here.
0309      * b) HDMIPHY bus does neither, so there is no way to do step 3.
0310      *    There is no indication when this bus has finished generating
0311      *    STOP.
0312      *
0313      * In fact, we have found that as soon as the IRQPEND bit is cleared in
0314      * step 2, the HDMIPHY bus generates the STOP condition, and then
0315      * immediately starts transferring another data byte, even though the
0316      * bus is supposedly stopped.  This is presumably because the bus is
0317      * still in "Master" mode, and its BUSY bit is still set.
0318      *
0319      * To avoid these extra post-STOP transactions on HDMI phy devices, we
0320      * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
0321      * instead of first generating a proper STOP condition.  This should
0322      * float SDA & SCK terminating the transfer.  Subsequent transfers
0323      *  start with a proper START condition, and proceed normally.
0324      *
0325      * The HDMIPHY bus is an internal bus that always has exactly two
0326      * devices, the host as Master and the HDMIPHY device as the slave.
0327      * Skipping the STOP condition has been tested on this bus and works.
0328      */
0329     if (i2c->quirks & QUIRK_HDMIPHY) {
0330         /* Stop driving the I2C pins */
0331         iicstat &= ~S3C2410_IICSTAT_TXRXEN;
0332     } else {
0333         /* stop the transfer */
0334         iicstat &= ~S3C2410_IICSTAT_START;
0335     }
0336     writel(iicstat, i2c->regs + S3C2410_IICSTAT);
0337 
0338     i2c->state = STATE_STOP;
0339 
0340     s3c24xx_i2c_master_complete(i2c, ret);
0341     s3c24xx_i2c_disable_irq(i2c);
0342 }
0343 
0344 /*
0345  * helper functions to determine the current state in the set of
0346  * messages we are sending
0347  */
0348 
0349 /*
0350  * returns TRUE if the current message is the last in the set
0351  */
0352 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
0353 {
0354     return i2c->msg_idx >= (i2c->msg_num - 1);
0355 }
0356 
0357 /*
0358  * returns TRUE if we this is the last byte in the current message
0359  */
0360 static inline int is_msglast(struct s3c24xx_i2c *i2c)
0361 {
0362     /*
0363      * msg->len is always 1 for the first byte of smbus block read.
0364      * Actual length will be read from slave. More bytes will be
0365      * read according to the length then.
0366      */
0367     if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
0368         return 0;
0369 
0370     return i2c->msg_ptr == i2c->msg->len-1;
0371 }
0372 
0373 /*
0374  * returns TRUE if we reached the end of the current message
0375  */
0376 static inline int is_msgend(struct s3c24xx_i2c *i2c)
0377 {
0378     return i2c->msg_ptr >= i2c->msg->len;
0379 }
0380 
0381 /*
0382  * process an interrupt and work out what to do
0383  */
0384 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
0385 {
0386     unsigned long tmp;
0387     unsigned char byte;
0388     int ret = 0;
0389 
0390     switch (i2c->state) {
0391 
0392     case STATE_IDLE:
0393         dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
0394         goto out;
0395 
0396     case STATE_STOP:
0397         dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
0398         s3c24xx_i2c_disable_irq(i2c);
0399         goto out_ack;
0400 
0401     case STATE_START:
0402         /*
0403          * last thing we did was send a start condition on the
0404          * bus, or started a new i2c message
0405          */
0406         if (iicstat & S3C2410_IICSTAT_LASTBIT &&
0407             !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
0408             /* ack was not received... */
0409             dev_dbg(i2c->dev, "ack was not received\n");
0410             s3c24xx_i2c_stop(i2c, -ENXIO);
0411             goto out_ack;
0412         }
0413 
0414         if (i2c->msg->flags & I2C_M_RD)
0415             i2c->state = STATE_READ;
0416         else
0417             i2c->state = STATE_WRITE;
0418 
0419         /*
0420          * Terminate the transfer if there is nothing to do
0421          * as this is used by the i2c probe to find devices.
0422          */
0423         if (is_lastmsg(i2c) && i2c->msg->len == 0) {
0424             s3c24xx_i2c_stop(i2c, 0);
0425             goto out_ack;
0426         }
0427 
0428         if (i2c->state == STATE_READ)
0429             goto prepare_read;
0430 
0431         /*
0432          * fall through to the write state, as we will need to
0433          * send a byte as well
0434          */
0435         fallthrough;
0436     case STATE_WRITE:
0437         /*
0438          * we are writing data to the device... check for the
0439          * end of the message, and if so, work out what to do
0440          */
0441         if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
0442             if (iicstat & S3C2410_IICSTAT_LASTBIT) {
0443                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
0444 
0445                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
0446                 goto out_ack;
0447             }
0448         }
0449 
0450  retry_write:
0451 
0452         if (!is_msgend(i2c)) {
0453             byte = i2c->msg->buf[i2c->msg_ptr++];
0454             writeb(byte, i2c->regs + S3C2410_IICDS);
0455 
0456             /*
0457              * delay after writing the byte to allow the
0458              * data setup time on the bus, as writing the
0459              * data to the register causes the first bit
0460              * to appear on SDA, and SCL will change as
0461              * soon as the interrupt is acknowledged
0462              */
0463             ndelay(i2c->tx_setup);
0464 
0465         } else if (!is_lastmsg(i2c)) {
0466             /* we need to go to the next i2c message */
0467 
0468             dev_dbg(i2c->dev, "WRITE: Next Message\n");
0469 
0470             i2c->msg_ptr = 0;
0471             i2c->msg_idx++;
0472             i2c->msg++;
0473 
0474             /* check to see if we need to do another message */
0475             if (i2c->msg->flags & I2C_M_NOSTART) {
0476 
0477                 if (i2c->msg->flags & I2C_M_RD) {
0478                     /*
0479                      * cannot do this, the controller
0480                      * forces us to send a new START
0481                      * when we change direction
0482                      */
0483                     dev_dbg(i2c->dev,
0484                         "missing START before write->read\n");
0485                     s3c24xx_i2c_stop(i2c, -EINVAL);
0486                     break;
0487                 }
0488 
0489                 goto retry_write;
0490             } else {
0491                 /* send the new start */
0492                 s3c24xx_i2c_message_start(i2c, i2c->msg);
0493                 i2c->state = STATE_START;
0494             }
0495 
0496         } else {
0497             /* send stop */
0498             s3c24xx_i2c_stop(i2c, 0);
0499         }
0500         break;
0501 
0502     case STATE_READ:
0503         /*
0504          * we have a byte of data in the data register, do
0505          * something with it, and then work out whether we are
0506          * going to do any more read/write
0507          */
0508         byte = readb(i2c->regs + S3C2410_IICDS);
0509         i2c->msg->buf[i2c->msg_ptr++] = byte;
0510 
0511         /* Add actual length to read for smbus block read */
0512         if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
0513             i2c->msg->len += byte;
0514  prepare_read:
0515         if (is_msglast(i2c)) {
0516             /* last byte of buffer */
0517 
0518             if (is_lastmsg(i2c))
0519                 s3c24xx_i2c_disable_ack(i2c);
0520 
0521         } else if (is_msgend(i2c)) {
0522             /*
0523              * ok, we've read the entire buffer, see if there
0524              * is anything else we need to do
0525              */
0526             if (is_lastmsg(i2c)) {
0527                 /* last message, send stop and complete */
0528                 dev_dbg(i2c->dev, "READ: Send Stop\n");
0529 
0530                 s3c24xx_i2c_stop(i2c, 0);
0531             } else {
0532                 /* go to the next transfer */
0533                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
0534 
0535                 i2c->msg_ptr = 0;
0536                 i2c->msg_idx++;
0537                 i2c->msg++;
0538             }
0539         }
0540 
0541         break;
0542     }
0543 
0544     /* acknowlegde the IRQ and get back on with the work */
0545 
0546  out_ack:
0547     tmp = readl(i2c->regs + S3C2410_IICCON);
0548     tmp &= ~S3C2410_IICCON_IRQPEND;
0549     writel(tmp, i2c->regs + S3C2410_IICCON);
0550  out:
0551     return ret;
0552 }
0553 
0554 /*
0555  * top level IRQ servicing routine
0556  */
0557 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
0558 {
0559     struct s3c24xx_i2c *i2c = dev_id;
0560     unsigned long status;
0561     unsigned long tmp;
0562 
0563     status = readl(i2c->regs + S3C2410_IICSTAT);
0564 
0565     if (status & S3C2410_IICSTAT_ARBITR) {
0566         /* deal with arbitration loss */
0567         dev_err(i2c->dev, "deal with arbitration loss\n");
0568     }
0569 
0570     if (i2c->state == STATE_IDLE) {
0571         dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
0572 
0573         tmp = readl(i2c->regs + S3C2410_IICCON);
0574         tmp &= ~S3C2410_IICCON_IRQPEND;
0575         writel(tmp, i2c->regs +  S3C2410_IICCON);
0576         goto out;
0577     }
0578 
0579     /*
0580      * pretty much this leaves us with the fact that we've
0581      * transmitted or received whatever byte we last sent
0582      */
0583     i2c_s3c_irq_nextbyte(i2c, status);
0584 
0585  out:
0586     return IRQ_HANDLED;
0587 }
0588 
0589 /*
0590  * Disable the bus so that we won't get any interrupts from now on, or try
0591  * to drive any lines. This is the default state when we don't have
0592  * anything to send/receive.
0593  *
0594  * If there is an event on the bus, or we have a pre-existing event at
0595  * kernel boot time, we may not notice the event and the I2C controller
0596  * will lock the bus with the I2C clock line low indefinitely.
0597  */
0598 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
0599 {
0600     unsigned long tmp;
0601 
0602     /* Stop driving the I2C pins */
0603     tmp = readl(i2c->regs + S3C2410_IICSTAT);
0604     tmp &= ~S3C2410_IICSTAT_TXRXEN;
0605     writel(tmp, i2c->regs + S3C2410_IICSTAT);
0606 
0607     /* We don't expect any interrupts now, and don't want send acks */
0608     tmp = readl(i2c->regs + S3C2410_IICCON);
0609     tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
0610         S3C2410_IICCON_ACKEN);
0611     writel(tmp, i2c->regs + S3C2410_IICCON);
0612 }
0613 
0614 
0615 /*
0616  * get the i2c bus for a master transaction
0617  */
0618 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
0619 {
0620     unsigned long iicstat;
0621     int timeout = 400;
0622 
0623     while (timeout-- > 0) {
0624         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
0625 
0626         if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
0627             return 0;
0628 
0629         msleep(1);
0630     }
0631 
0632     return -ETIMEDOUT;
0633 }
0634 
0635 /*
0636  * wait for the i2c bus to become idle.
0637  */
0638 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
0639 {
0640     unsigned long iicstat;
0641     ktime_t start, now;
0642     unsigned long delay;
0643     int spins;
0644 
0645     /* ensure the stop has been through the bus */
0646 
0647     dev_dbg(i2c->dev, "waiting for bus idle\n");
0648 
0649     start = now = ktime_get();
0650 
0651     /*
0652      * Most of the time, the bus is already idle within a few usec of the
0653      * end of a transaction.  However, really slow i2c devices can stretch
0654      * the clock, delaying STOP generation.
0655      *
0656      * On slower SoCs this typically happens within a very small number of
0657      * instructions so busy wait briefly to avoid scheduling overhead.
0658      */
0659     spins = 3;
0660     iicstat = readl(i2c->regs + S3C2410_IICSTAT);
0661     while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
0662         cpu_relax();
0663         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
0664     }
0665 
0666     /*
0667      * If we do get an appreciable delay as a compromise between idle
0668      * detection latency for the normal, fast case, and system load in the
0669      * slow device case, use an exponential back off in the polling loop,
0670      * up to 1/10th of the total timeout, then continue to poll at a
0671      * constant rate up to the timeout.
0672      */
0673     delay = 1;
0674     while ((iicstat & S3C2410_IICSTAT_START) &&
0675            ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
0676         usleep_range(delay, 2 * delay);
0677         if (delay < S3C2410_IDLE_TIMEOUT / 10)
0678             delay <<= 1;
0679         now = ktime_get();
0680         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
0681     }
0682 
0683     if (iicstat & S3C2410_IICSTAT_START)
0684         dev_warn(i2c->dev, "timeout waiting for bus idle\n");
0685 }
0686 
0687 /*
0688  * this starts an i2c transfer
0689  */
0690 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
0691                   struct i2c_msg *msgs, int num)
0692 {
0693     unsigned long timeout;
0694     int ret;
0695 
0696     ret = s3c24xx_i2c_set_master(i2c);
0697     if (ret != 0) {
0698         dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
0699         ret = -EAGAIN;
0700         goto out;
0701     }
0702 
0703     i2c->msg     = msgs;
0704     i2c->msg_num = num;
0705     i2c->msg_ptr = 0;
0706     i2c->msg_idx = 0;
0707     i2c->state   = STATE_START;
0708 
0709     s3c24xx_i2c_enable_irq(i2c);
0710     s3c24xx_i2c_message_start(i2c, msgs);
0711 
0712     if (i2c->quirks & QUIRK_POLL) {
0713         ret = i2c->msg_idx;
0714 
0715         if (ret != num)
0716             dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
0717 
0718         goto out;
0719     }
0720 
0721     timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
0722 
0723     ret = i2c->msg_idx;
0724 
0725     /*
0726      * Having these next two as dev_err() makes life very
0727      * noisy when doing an i2cdetect
0728      */
0729     if (timeout == 0)
0730         dev_dbg(i2c->dev, "timeout\n");
0731     else if (ret != num)
0732         dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
0733 
0734     /* For QUIRK_HDMIPHY, bus is already disabled */
0735     if (i2c->quirks & QUIRK_HDMIPHY)
0736         goto out;
0737 
0738     s3c24xx_i2c_wait_idle(i2c);
0739 
0740     s3c24xx_i2c_disable_bus(i2c);
0741 
0742  out:
0743     i2c->state = STATE_IDLE;
0744 
0745     return ret;
0746 }
0747 
0748 /*
0749  * first port of call from the i2c bus code when an message needs
0750  * transferring across the i2c bus.
0751  */
0752 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
0753             struct i2c_msg *msgs, int num)
0754 {
0755     struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
0756     int retry;
0757     int ret;
0758 
0759     ret = clk_enable(i2c->clk);
0760     if (ret)
0761         return ret;
0762 
0763     for (retry = 0; retry < adap->retries; retry++) {
0764 
0765         ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
0766 
0767         if (ret != -EAGAIN) {
0768             clk_disable(i2c->clk);
0769             return ret;
0770         }
0771 
0772         dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
0773 
0774         udelay(100);
0775     }
0776 
0777     clk_disable(i2c->clk);
0778     return -EREMOTEIO;
0779 }
0780 
0781 /* declare our i2c functionality */
0782 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
0783 {
0784     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL_ALL | I2C_FUNC_NOSTART |
0785         I2C_FUNC_PROTOCOL_MANGLING;
0786 }
0787 
0788 /* i2c bus registration info */
0789 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
0790     .master_xfer        = s3c24xx_i2c_xfer,
0791     .functionality      = s3c24xx_i2c_func,
0792 };
0793 
0794 /*
0795  * return the divisor settings for a given frequency
0796  */
0797 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
0798                    unsigned int *div1, unsigned int *divs)
0799 {
0800     unsigned int calc_divs = clkin / wanted;
0801     unsigned int calc_div1;
0802 
0803     if (calc_divs > (16*16))
0804         calc_div1 = 512;
0805     else
0806         calc_div1 = 16;
0807 
0808     calc_divs += calc_div1-1;
0809     calc_divs /= calc_div1;
0810 
0811     if (calc_divs == 0)
0812         calc_divs = 1;
0813     if (calc_divs > 17)
0814         calc_divs = 17;
0815 
0816     *divs = calc_divs;
0817     *div1 = calc_div1;
0818 
0819     return clkin / (calc_divs * calc_div1);
0820 }
0821 
0822 /*
0823  * work out a divisor for the user requested frequency setting,
0824  * either by the requested frequency, or scanning the acceptable
0825  * range of frequencies until something is found
0826  */
0827 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
0828 {
0829     struct s3c2410_platform_i2c *pdata = i2c->pdata;
0830     unsigned long clkin = clk_get_rate(i2c->clk);
0831     unsigned int divs, div1;
0832     unsigned long target_frequency;
0833     u32 iiccon;
0834     int freq;
0835 
0836     i2c->clkrate = clkin;
0837     clkin /= 1000;  /* clkin now in KHz */
0838 
0839     dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
0840 
0841     target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ;
0842 
0843     target_frequency /= 1000; /* Target frequency now in KHz */
0844 
0845     freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
0846 
0847     if (freq > target_frequency) {
0848         dev_err(i2c->dev,
0849             "Unable to achieve desired frequency %luKHz."   \
0850             " Lowest achievable %dKHz\n", target_frequency, freq);
0851         return -EINVAL;
0852     }
0853 
0854     *got = freq;
0855 
0856     iiccon = readl(i2c->regs + S3C2410_IICCON);
0857     iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
0858     iiccon |= (divs-1);
0859 
0860     if (div1 == 512)
0861         iiccon |= S3C2410_IICCON_TXDIV_512;
0862 
0863     if (i2c->quirks & QUIRK_POLL)
0864         iiccon |= S3C2410_IICCON_SCALE(2);
0865 
0866     writel(iiccon, i2c->regs + S3C2410_IICCON);
0867 
0868     if (i2c->quirks & QUIRK_S3C2440) {
0869         unsigned long sda_delay;
0870 
0871         if (pdata->sda_delay) {
0872             sda_delay = clkin * pdata->sda_delay;
0873             sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
0874             sda_delay = DIV_ROUND_UP(sda_delay, 5);
0875             if (sda_delay > 3)
0876                 sda_delay = 3;
0877             sda_delay |= S3C2410_IICLC_FILTER_ON;
0878         } else
0879             sda_delay = 0;
0880 
0881         dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
0882         writel(sda_delay, i2c->regs + S3C2440_IICLC);
0883     }
0884 
0885     return 0;
0886 }
0887 
0888 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
0889 
0890 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
0891 
0892 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
0893                       unsigned long val, void *data)
0894 {
0895     struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
0896     unsigned int got;
0897     int delta_f;
0898     int ret;
0899 
0900     delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
0901 
0902     /* if we're post-change and the input clock has slowed down
0903      * or at pre-change and the clock is about to speed up, then
0904      * adjust our clock rate. <0 is slow, >0 speedup.
0905      */
0906 
0907     if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
0908         (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
0909         i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
0910         ret = s3c24xx_i2c_clockrate(i2c, &got);
0911         i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
0912 
0913         if (ret < 0)
0914             dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
0915         else
0916             dev_info(i2c->dev, "setting freq %d\n", got);
0917     }
0918 
0919     return 0;
0920 }
0921 
0922 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
0923 {
0924     i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
0925 
0926     return cpufreq_register_notifier(&i2c->freq_transition,
0927                      CPUFREQ_TRANSITION_NOTIFIER);
0928 }
0929 
0930 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
0931 {
0932     cpufreq_unregister_notifier(&i2c->freq_transition,
0933                     CPUFREQ_TRANSITION_NOTIFIER);
0934 }
0935 
0936 #else
0937 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
0938 {
0939     return 0;
0940 }
0941 
0942 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
0943 {
0944 }
0945 #endif
0946 
0947 #ifdef CONFIG_OF
0948 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
0949 {
0950     int i;
0951 
0952     if (i2c->quirks & QUIRK_NO_GPIO)
0953         return 0;
0954 
0955     for (i = 0; i < 2; i++) {
0956         i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL,
0957                              i, GPIOD_ASIS);
0958         if (IS_ERR(i2c->gpios[i])) {
0959             dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i);
0960             return -EINVAL;
0961         }
0962     }
0963     return 0;
0964 }
0965 
0966 #else
0967 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
0968 {
0969     return 0;
0970 }
0971 #endif
0972 
0973 /*
0974  * initialise the controller, set the IO lines and frequency
0975  */
0976 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
0977 {
0978     struct s3c2410_platform_i2c *pdata;
0979     unsigned int freq;
0980 
0981     /* get the plafrom data */
0982 
0983     pdata = i2c->pdata;
0984 
0985     /* write slave address */
0986 
0987     writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
0988 
0989     dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
0990 
0991     writel(0, i2c->regs + S3C2410_IICCON);
0992     writel(0, i2c->regs + S3C2410_IICSTAT);
0993 
0994     /* we need to work out the divisors for the clock... */
0995 
0996     if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
0997         dev_err(i2c->dev, "cannot meet bus frequency required\n");
0998         return -EINVAL;
0999     }
1000 
1001     /* todo - check that the i2c lines aren't being dragged anywhere */
1002 
1003     dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1004     dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1005         readl(i2c->regs + S3C2410_IICCON));
1006 
1007     return 0;
1008 }
1009 
1010 #ifdef CONFIG_OF
1011 /*
1012  * Parse the device tree node and retreive the platform data.
1013  */
1014 static void
1015 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1016 {
1017     struct s3c2410_platform_i2c *pdata = i2c->pdata;
1018     int id;
1019 
1020     if (!np)
1021         return;
1022 
1023     pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1024     of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1025     of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1026     of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1027                 (u32 *)&pdata->frequency);
1028     /*
1029      * Exynos5's legacy i2c controller and new high speed i2c
1030      * controller have muxed interrupt sources. By default the
1031      * interrupts for 4-channel HS-I2C controller are enabled.
1032      * If nodes for first four channels of legacy i2c controller
1033      * are available then re-configure the interrupts via the
1034      * system register.
1035      */
1036     id = of_alias_get_id(np, "i2c");
1037     i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1038             "samsung,sysreg-phandle");
1039     if (IS_ERR(i2c->sysreg))
1040         return;
1041 
1042     regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1043 }
1044 #else
1045 static void
1046 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
1047 #endif
1048 
1049 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1050 {
1051     struct s3c24xx_i2c *i2c;
1052     struct s3c2410_platform_i2c *pdata = NULL;
1053     struct resource *res;
1054     int ret;
1055 
1056     if (!pdev->dev.of_node) {
1057         pdata = dev_get_platdata(&pdev->dev);
1058         if (!pdata) {
1059             dev_err(&pdev->dev, "no platform data\n");
1060             return -EINVAL;
1061         }
1062     }
1063 
1064     i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1065     if (!i2c)
1066         return -ENOMEM;
1067 
1068     i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1069     if (!i2c->pdata)
1070         return -ENOMEM;
1071 
1072     i2c->quirks = s3c24xx_get_device_quirks(pdev);
1073     i2c->sysreg = ERR_PTR(-ENOENT);
1074     if (pdata)
1075         memcpy(i2c->pdata, pdata, sizeof(*pdata));
1076     else
1077         s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1078 
1079     strscpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1080     i2c->adap.owner = THIS_MODULE;
1081     i2c->adap.algo = &s3c24xx_i2c_algorithm;
1082     i2c->adap.retries = 2;
1083     i2c->adap.class = I2C_CLASS_DEPRECATED;
1084     i2c->tx_setup = 50;
1085 
1086     init_waitqueue_head(&i2c->wait);
1087 
1088     /* find the clock and enable it */
1089     i2c->dev = &pdev->dev;
1090     i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1091     if (IS_ERR(i2c->clk)) {
1092         dev_err(&pdev->dev, "cannot get clock\n");
1093         return -ENOENT;
1094     }
1095 
1096     dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1097 
1098     /* map the registers */
1099     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1100     i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1101 
1102     if (IS_ERR(i2c->regs))
1103         return PTR_ERR(i2c->regs);
1104 
1105     dev_dbg(&pdev->dev, "registers %p (%p)\n",
1106         i2c->regs, res);
1107 
1108     /* setup info block for the i2c core */
1109     i2c->adap.algo_data = i2c;
1110     i2c->adap.dev.parent = &pdev->dev;
1111     i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1112 
1113     /* inititalise the i2c gpio lines */
1114     if (i2c->pdata->cfg_gpio)
1115         i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1116     else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1117         return -EINVAL;
1118 
1119     /* initialise the i2c controller */
1120     ret = clk_prepare_enable(i2c->clk);
1121     if (ret) {
1122         dev_err(&pdev->dev, "I2C clock enable failed\n");
1123         return ret;
1124     }
1125 
1126     ret = s3c24xx_i2c_init(i2c);
1127     clk_disable(i2c->clk);
1128     if (ret != 0) {
1129         dev_err(&pdev->dev, "I2C controller init failed\n");
1130         clk_unprepare(i2c->clk);
1131         return ret;
1132     }
1133 
1134     /*
1135      * find the IRQ for this unit (note, this relies on the init call to
1136      * ensure no current IRQs pending
1137      */
1138     if (!(i2c->quirks & QUIRK_POLL)) {
1139         i2c->irq = ret = platform_get_irq(pdev, 0);
1140         if (ret < 0) {
1141             dev_err(&pdev->dev, "cannot find IRQ\n");
1142             clk_unprepare(i2c->clk);
1143             return ret;
1144         }
1145 
1146         ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1147                        0, dev_name(&pdev->dev), i2c);
1148         if (ret != 0) {
1149             dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1150             clk_unprepare(i2c->clk);
1151             return ret;
1152         }
1153     }
1154 
1155     ret = s3c24xx_i2c_register_cpufreq(i2c);
1156     if (ret < 0) {
1157         dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1158         clk_unprepare(i2c->clk);
1159         return ret;
1160     }
1161 
1162     /*
1163      * Note, previous versions of the driver used i2c_add_adapter()
1164      * to add the bus at any number. We now pass the bus number via
1165      * the platform data, so if unset it will now default to always
1166      * being bus 0.
1167      */
1168     i2c->adap.nr = i2c->pdata->bus_num;
1169     i2c->adap.dev.of_node = pdev->dev.of_node;
1170 
1171     platform_set_drvdata(pdev, i2c);
1172 
1173     pm_runtime_enable(&pdev->dev);
1174 
1175     ret = i2c_add_numbered_adapter(&i2c->adap);
1176     if (ret < 0) {
1177         pm_runtime_disable(&pdev->dev);
1178         s3c24xx_i2c_deregister_cpufreq(i2c);
1179         clk_unprepare(i2c->clk);
1180         return ret;
1181     }
1182 
1183     dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1184     return 0;
1185 }
1186 
1187 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1188 {
1189     struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1190 
1191     clk_unprepare(i2c->clk);
1192 
1193     pm_runtime_disable(&pdev->dev);
1194 
1195     s3c24xx_i2c_deregister_cpufreq(i2c);
1196 
1197     i2c_del_adapter(&i2c->adap);
1198 
1199     return 0;
1200 }
1201 
1202 #ifdef CONFIG_PM_SLEEP
1203 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1204 {
1205     struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1206 
1207     i2c_mark_adapter_suspended(&i2c->adap);
1208 
1209     if (!IS_ERR(i2c->sysreg))
1210         regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1211 
1212     return 0;
1213 }
1214 
1215 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1216 {
1217     struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1218     int ret;
1219 
1220     if (!IS_ERR(i2c->sysreg))
1221         regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1222 
1223     ret = clk_enable(i2c->clk);
1224     if (ret)
1225         return ret;
1226     s3c24xx_i2c_init(i2c);
1227     clk_disable(i2c->clk);
1228     i2c_mark_adapter_resumed(&i2c->adap);
1229 
1230     return 0;
1231 }
1232 #endif
1233 
1234 #ifdef CONFIG_PM
1235 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1236     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1237                       s3c24xx_i2c_resume_noirq)
1238 };
1239 
1240 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1241 #else
1242 #define S3C24XX_DEV_PM_OPS NULL
1243 #endif
1244 
1245 static struct platform_driver s3c24xx_i2c_driver = {
1246     .probe      = s3c24xx_i2c_probe,
1247     .remove     = s3c24xx_i2c_remove,
1248     .id_table   = s3c24xx_driver_ids,
1249     .driver     = {
1250         .name   = "s3c-i2c",
1251         .pm = S3C24XX_DEV_PM_OPS,
1252         .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1253     },
1254 };
1255 
1256 static int __init i2c_adap_s3c_init(void)
1257 {
1258     return platform_driver_register(&s3c24xx_i2c_driver);
1259 }
1260 subsys_initcall(i2c_adap_s3c_init);
1261 
1262 static void __exit i2c_adap_s3c_exit(void)
1263 {
1264     platform_driver_unregister(&s3c24xx_i2c_driver);
1265 }
1266 module_exit(i2c_adap_s3c_exit);
1267 
1268 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1269 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1270 MODULE_LICENSE("GPL");
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