i2c/busses/i2c-rzv2m.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for the Renesas RZ/V2M I2C unit
0004  *
0005  * Copyright (C) 2016-2022 Renesas Electronics Corporation
0006  */
0007
0008 #include <linux/bits.h>
0009 #include <linux/clk.h>
0010 #include <linux/device.h>
0011 #include <linux/err.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/i2c.h>
0016 #include <linux/jiffies.h>
0017 #include <linux/kernel.h>
0018 #include <linux/math64.h>
0019 #include <linux/module.h>
0020 #include <linux/mod_devicetable.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/reset.h>
0024
0025 /* Register offsets */
0026 #define IICB0DAT    0x00        /* Data Register */
0027 #define IICB0CTL0   0x08        /* Control Register 0 */
0028 #define IICB0TRG    0x0C        /* Trigger Register */
0029 #define IICB0STR0   0x10        /* Status Register 0 */
0030 #define IICB0CTL1   0x20        /* Control Register 1 */
0031 #define IICB0WL     0x24        /* Low Level Width Setting Reg */
0032 #define IICB0WH     0x28        /* How Level Width Setting Reg */
0033
0034 /* IICB0CTL0 */
0035 #define IICB0IICE   BIT(7)      /* I2C Enable */
0036 #define IICB0SLWT   BIT(1)      /* Interrupt Request Timing */
0037 #define IICB0SLAC   BIT(0)      /* Acknowledge */
0038
0039 /* IICB0TRG */
0040 #define IICB0WRET   BIT(2)      /* Quit Wait Trigger */
0041 #define IICB0STT    BIT(1)      /* Create Start Condition Trigger */
0042 #define IICB0SPT    BIT(0)      /* Create Stop Condition Trigger */
0043
0044 /* IICB0STR0 */
0045 #define IICB0SSAC   BIT(8)      /* Ack Flag */
0046 #define IICB0SSBS   BIT(6)      /* Bus Flag */
0047 #define IICB0SSSP   BIT(4)      /* Stop Condition Flag */
0048
0049 /* IICB0CTL1 */
0050 #define IICB0MDSC   BIT(7)      /* Bus Mode */
0051 #define IICB0SLSE   BIT(1)      /* Start condition output */
0052
0053 #define bit_setl(addr, val)     writel(readl(addr) | (val), (addr))
0054 #define bit_clrl(addr, val)     writel(readl(addr) & ~(val), (addr))
0055
0056 struct rzv2m_i2c_priv {
0057     void __iomem *base;
0058     struct i2c_adapter adap;
0059     struct clk *clk;
0060     int bus_mode;
0061     struct completion msg_tia_done;
0062     u32 iicb0wl;
0063     u32 iicb0wh;
0064 };
0065
0066 enum bcr_index {
0067     RZV2M_I2C_100K = 0,
0068     RZV2M_I2C_400K,
0069 };
0070
0071 struct bitrate_config {
0072     unsigned int percent_low;
0073     unsigned int min_hold_time_ns;
0074 };
0075
0076 static const struct bitrate_config bitrate_configs[] = {
0077     [RZV2M_I2C_100K] = { 47, 3450 },
0078     [RZV2M_I2C_400K] = { 52, 900 },
0079 };
0080
0081 static irqreturn_t rzv2m_i2c_tia_irq_handler(int this_irq, void *dev_id)
0082 {
0083     struct rzv2m_i2c_priv *priv = dev_id;
0084
0085     complete(&priv->msg_tia_done);
0086
0087     return IRQ_HANDLED;
0088 }
0089
0090 /* Calculate IICB0WL and IICB0WH */
0091 static int rzv2m_i2c_clock_calculate(struct device *dev,
0092                      struct rzv2m_i2c_priv *priv)
0093 {
0094     const struct bitrate_config *config;
0095     unsigned int hold_time_ns;
0096     unsigned int total_pclks;
0097     unsigned int trf_pclks;
0098     unsigned long pclk_hz;
0099     struct i2c_timings t;
0100     u32 trf_ns;
0101
0102     i2c_parse_fw_timings(dev, &t, true);
0103
0104     pclk_hz = clk_get_rate(priv->clk);
0105     total_pclks = pclk_hz / t.bus_freq_hz;
0106
0107     trf_ns = t.scl_rise_ns + t.scl_fall_ns;
0108     trf_pclks = mul_u64_u32_div(pclk_hz, trf_ns, NSEC_PER_SEC);
0109
0110     /* Config setting */
0111     switch (t.bus_freq_hz) {
0112     case I2C_MAX_FAST_MODE_FREQ:
0113         priv->bus_mode = RZV2M_I2C_400K;
0114         break;
0115     case I2C_MAX_STANDARD_MODE_FREQ:
0116         priv->bus_mode = RZV2M_I2C_100K;
0117         break;
0118     default:
0119         dev_err(dev, "transfer speed is invalid\n");
0120         return -EINVAL;
0121     }
0122     config = &bitrate_configs[priv->bus_mode];
0123
0124     /* IICB0WL = (percent_low / Transfer clock) x PCLK */
0125     priv->iicb0wl = total_pclks * config->percent_low / 100;
0126     if (priv->iicb0wl > (BIT(10) - 1))
0127         return -EINVAL;
0128
0129     /* IICB0WH = ((percent_high / Transfer clock) x PCLK) - (tR + tF) */
0130     priv->iicb0wh = total_pclks - priv->iicb0wl - trf_pclks;
0131     if (priv->iicb0wh > (BIT(10) - 1))
0132         return -EINVAL;
0133
0134     /*
0135      * Data hold time must be less than 0.9us in fast mode and
0136      * 3.45us in standard mode.
0137      * Data hold time = IICB0WL[9:2] / PCLK
0138      */
0139     hold_time_ns = div64_ul((u64)(priv->iicb0wl >> 2) * NSEC_PER_SEC, pclk_hz);
0140     if (hold_time_ns > config->min_hold_time_ns) {
0141         dev_err(dev, "data hold time %dns is over %dns\n",
0142             hold_time_ns, config->min_hold_time_ns);
0143         return -EINVAL;
0144     }
0145
0146     return 0;
0147 }
0148
0149 static void rzv2m_i2c_init(struct rzv2m_i2c_priv *priv)
0150 {
0151     u32 i2c_ctl0;
0152     u32 i2c_ctl1;
0153
0154     /* i2c disable */
0155     writel(0, priv->base + IICB0CTL0);
0156
0157     /* IICB0CTL1 setting */
0158     i2c_ctl1 = IICB0SLSE;
0159     if (priv->bus_mode == RZV2M_I2C_400K)
0160         i2c_ctl1 |= IICB0MDSC;
0161     writel(i2c_ctl1, priv->base + IICB0CTL1);
0162
0163     /* IICB0WL IICB0WH setting */
0164     writel(priv->iicb0wl, priv->base + IICB0WL);
0165     writel(priv->iicb0wh, priv->base + IICB0WH);
0166
0167     /* i2c enable after setting */
0168     i2c_ctl0 = IICB0SLWT | IICB0SLAC | IICB0IICE;
0169     writel(i2c_ctl0, priv->base + IICB0CTL0);
0170 }
0171
0172 static int rzv2m_i2c_write_with_ack(struct rzv2m_i2c_priv *priv, u32 data)
0173 {
0174     unsigned long time_left;
0175
0176     reinit_completion(&priv->msg_tia_done);
0177
0178     writel(data, priv->base + IICB0DAT);
0179
0180     time_left = wait_for_completion_timeout(&priv->msg_tia_done,
0181                         priv->adap.timeout);
0182     if (!time_left)
0183         return -ETIMEDOUT;
0184
0185     /* Confirm ACK */
0186     if ((readl(priv->base + IICB0STR0) & IICB0SSAC) != IICB0SSAC)
0187         return -ENXIO;
0188
0189     return 0;
0190 }
0191
0192 static int rzv2m_i2c_read_with_ack(struct rzv2m_i2c_priv *priv, u8 *data,
0193                    bool last)
0194 {
0195     unsigned long time_left;
0196     u32 data_tmp;
0197
0198     reinit_completion(&priv->msg_tia_done);
0199
0200     /* Interrupt request timing : 8th clock */
0201     bit_clrl(priv->base + IICB0CTL0, IICB0SLWT);
0202
0203     /* Exit the wait state */
0204     writel(IICB0WRET, priv->base + IICB0TRG);
0205
0206     /* Wait for transaction */
0207     time_left = wait_for_completion_timeout(&priv->msg_tia_done,
0208                         priv->adap.timeout);
0209     if (!time_left)
0210         return -ETIMEDOUT;
0211
0212     if (last) {
0213         /* Disable ACK */
0214         bit_clrl(priv->base + IICB0CTL0, IICB0SLAC);
0215
0216         /* Read data*/
0217         data_tmp = readl(priv->base + IICB0DAT);
0218
0219         /* Interrupt request timing : 9th clock */
0220         bit_setl(priv->base + IICB0CTL0, IICB0SLWT);
0221
0222         /* Exit the wait state */
0223         writel(IICB0WRET, priv->base + IICB0TRG);
0224
0225         /* Wait for transaction */
0226         time_left = wait_for_completion_timeout(&priv->msg_tia_done,
0227                             priv->adap.timeout);
0228         if (!time_left)
0229             return -ETIMEDOUT;
0230
0231         /* Enable ACK */
0232         bit_setl(priv->base + IICB0CTL0, IICB0SLAC);
0233     } else {
0234         /* Read data */
0235         data_tmp = readl(priv->base + IICB0DAT);
0236     }
0237
0238     *data = data_tmp;
0239
0240     return 0;
0241 }
0242
0243 static int rzv2m_i2c_send(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
0244               unsigned int *count)
0245 {
0246     unsigned int i;
0247     int ret;
0248
0249     for (i = 0; i < msg->len; i++) {
0250         ret = rzv2m_i2c_write_with_ack(priv, msg->buf[i]);
0251         if (ret < 0)
0252             return ret;
0253     }
0254     *count = i;
0255
0256     return 0;
0257 }
0258
0259 static int rzv2m_i2c_receive(struct rzv2m_i2c_priv *priv, struct i2c_msg *msg,
0260                  unsigned int *count)
0261 {
0262     unsigned int i;
0263     int ret;
0264
0265     for (i = 0; i < msg->len; i++) {
0266         ret = rzv2m_i2c_read_with_ack(priv, &msg->buf[i],
0267                           (msg->len - 1) == i);
0268         if (ret < 0)
0269             return ret;
0270     }
0271     *count = i;
0272
0273     return 0;
0274 }
0275
0276 static int rzv2m_i2c_send_address(struct rzv2m_i2c_priv *priv,
0277                   struct i2c_msg *msg)
0278 {
0279     u32 addr;
0280     int ret;
0281
0282     if (msg->flags & I2C_M_TEN) {
0283         /*
0284          * 10-bit address
0285          *   addr_1: 5'b11110 | addr[9:8] | (R/nW)
0286          *   addr_2: addr[7:0]
0287          */
0288         addr = 0xf0 | ((msg->addr & GENMASK(9, 8)) >> 7);
0289         addr |= !!(msg->flags & I2C_M_RD);
0290         /* Send 1st address(extend code) */
0291         ret = rzv2m_i2c_write_with_ack(priv, addr);
0292         if (ret)
0293             return ret;
0294
0295         /* Send 2nd address */
0296         ret = rzv2m_i2c_write_with_ack(priv, msg->addr & 0xff);
0297     } else {
0298         /* 7-bit address */
0299         addr = i2c_8bit_addr_from_msg(msg);
0300         ret = rzv2m_i2c_write_with_ack(priv, addr);
0301     }
0302
0303     return ret;
0304 }
0305
0306 static int rzv2m_i2c_stop_condition(struct rzv2m_i2c_priv *priv)
0307 {
0308     u32 value;
0309
0310     /* Send stop condition */
0311     writel(IICB0SPT, priv->base + IICB0TRG);
0312     return readl_poll_timeout(priv->base + IICB0STR0,
0313                   value, value & IICB0SSSP,
0314                   100, jiffies_to_usecs(priv->adap.timeout));
0315 }
0316
0317 static int rzv2m_i2c_master_xfer_msg(struct rzv2m_i2c_priv *priv,
0318                   struct i2c_msg *msg, int stop)
0319 {
0320     unsigned int count = 0;
0321     int ret, read = !!(msg->flags & I2C_M_RD);
0322
0323     /* Send start condition */
0324     writel(IICB0STT, priv->base + IICB0TRG);
0325
0326     ret = rzv2m_i2c_send_address(priv, msg);
0327     if (!ret) {
0328         if (read)
0329             ret = rzv2m_i2c_receive(priv, msg, &count);
0330         else
0331             ret = rzv2m_i2c_send(priv, msg, &count);
0332
0333         if (!ret && stop)
0334             ret = rzv2m_i2c_stop_condition(priv);
0335     }
0336
0337     if (ret == -ENXIO)
0338         rzv2m_i2c_stop_condition(priv);
0339     else if (ret < 0)
0340         rzv2m_i2c_init(priv);
0341     else
0342         ret = count;
0343
0344     return ret;
0345 }
0346
0347 static int rzv2m_i2c_master_xfer(struct i2c_adapter *adap,
0348                  struct i2c_msg *msgs, int num)
0349 {
0350     struct rzv2m_i2c_priv *priv = i2c_get_adapdata(adap);
0351     struct device *dev = priv->adap.dev.parent;
0352     unsigned int i;
0353     int ret;
0354
0355     ret = pm_runtime_resume_and_get(dev);
0356     if (ret < 0)
0357         return ret;
0358
0359     if (readl(priv->base + IICB0STR0) & IICB0SSBS) {
0360         ret = -EAGAIN;
0361         goto out;
0362     }
0363
0364     /* I2C main transfer */
0365     for (i = 0; i < num; i++) {
0366         ret = rzv2m_i2c_master_xfer_msg(priv, &msgs[i], i == (num - 1));
0367         if (ret < 0)
0368             goto out;
0369     }
0370     ret = num;
0371
0372 out:
0373     pm_runtime_mark_last_busy(dev);
0374     pm_runtime_put_autosuspend(dev);
0375
0376     return ret;
0377 }
0378
0379 static u32 rzv2m_i2c_func(struct i2c_adapter *adap)
0380 {
0381     return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
0382            I2C_FUNC_10BIT_ADDR;
0383 }
0384
0385 static const struct i2c_adapter_quirks rzv2m_i2c_quirks = {
0386     .flags = I2C_AQ_NO_ZERO_LEN,
0387 };
0388
0389 static struct i2c_algorithm rzv2m_i2c_algo = {
0390     .master_xfer = rzv2m_i2c_master_xfer,
0391     .functionality = rzv2m_i2c_func,
0392 };
0393
0394 static int rzv2m_i2c_probe(struct platform_device *pdev)
0395 {
0396     struct device *dev = &pdev->dev;
0397     struct rzv2m_i2c_priv *priv;
0398     struct reset_control *rstc;
0399     struct i2c_adapter *adap;
0400     struct resource *res;
0401     int irq, ret;
0402
0403     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0404     if (!priv)
0405         return -ENOMEM;
0406
0407     priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0408     if (IS_ERR(priv->base))
0409         return PTR_ERR(priv->base);
0410
0411     priv->clk = devm_clk_get(dev, NULL);
0412     if (IS_ERR(priv->clk))
0413         return dev_err_probe(dev, PTR_ERR(priv->clk), "Can't get clock\n");
0414
0415     rstc = devm_reset_control_get_shared(dev, NULL);
0416     if (IS_ERR(rstc))
0417         return dev_err_probe(dev, PTR_ERR(rstc), "Missing reset ctrl\n");
0418     /*
0419      * The reset also affects other HW that is not under the control
0420      * of Linux. Therefore, all we can do is deassert the reset.
0421      */
0422     reset_control_deassert(rstc);
0423
0424     irq = platform_get_irq(pdev, 0);
0425     if (irq < 0)
0426         return irq;
0427
0428     ret = devm_request_irq(dev, irq, rzv2m_i2c_tia_irq_handler, 0,
0429                    dev_name(dev), priv);
0430     if (ret < 0)
0431         return dev_err_probe(dev, ret, "Unable to request irq %d\n", irq);
0432
0433     adap = &priv->adap;
0434     adap->nr = pdev->id;
0435     adap->algo = &rzv2m_i2c_algo;
0436     adap->quirks = &rzv2m_i2c_quirks;
0437     adap->dev.parent = dev;
0438     adap->owner = THIS_MODULE;
0439     device_set_node(&adap->dev, dev_fwnode(dev));
0440     i2c_set_adapdata(adap, priv);
0441     strscpy(adap->name, pdev->name, sizeof(adap->name));
0442     init_completion(&priv->msg_tia_done);
0443
0444     ret = rzv2m_i2c_clock_calculate(dev, priv);
0445     if (ret < 0)
0446         return ret;
0447
0448     pm_runtime_enable(dev);
0449
0450     pm_runtime_get_sync(dev);
0451     rzv2m_i2c_init(priv);
0452     pm_runtime_put(dev);
0453
0454     platform_set_drvdata(pdev, priv);
0455
0456     ret = i2c_add_numbered_adapter(adap);
0457     if (ret < 0)
0458         pm_runtime_disable(dev);
0459
0460     return ret;
0461 }
0462
0463 static int rzv2m_i2c_remove(struct platform_device *pdev)
0464 {
0465     struct rzv2m_i2c_priv *priv = platform_get_drvdata(pdev);
0466     struct device *dev = priv->adap.dev.parent;
0467
0468     i2c_del_adapter(&priv->adap);
0469     bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
0470     pm_runtime_disable(dev);
0471
0472     return 0;
0473 }
0474
0475 static int rzv2m_i2c_suspend(struct device *dev)
0476 {
0477     struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
0478     int ret;
0479
0480     ret = pm_runtime_resume_and_get(dev);
0481     if (ret < 0)
0482         return ret;
0483
0484     bit_clrl(priv->base + IICB0CTL0, IICB0IICE);
0485     pm_runtime_put(dev);
0486
0487     return 0;
0488 }
0489
0490 static int rzv2m_i2c_resume(struct device *dev)
0491 {
0492     struct rzv2m_i2c_priv *priv = dev_get_drvdata(dev);
0493     int ret;
0494
0495     ret = rzv2m_i2c_clock_calculate(dev, priv);
0496     if (ret < 0)
0497         return ret;
0498
0499     ret = pm_runtime_resume_and_get(dev);
0500     if (ret < 0)
0501         return ret;
0502
0503     rzv2m_i2c_init(priv);
0504     pm_runtime_put(dev);
0505
0506     return 0;
0507 }
0508
0509 static const struct of_device_id rzv2m_i2c_ids[] = {
0510     { .compatible = "renesas,rzv2m-i2c" },
0511     { }
0512 };
0513 MODULE_DEVICE_TABLE(of, rzv2m_i2c_ids);
0514
0515 static const struct dev_pm_ops rzv2m_i2c_pm_ops = {
0516     SYSTEM_SLEEP_PM_OPS(rzv2m_i2c_suspend, rzv2m_i2c_resume)
0517 };
0518
0519 static struct platform_driver rzv2m_i2c_driver = {
0520     .driver = {
0521         .name = "rzv2m-i2c",
0522         .of_match_table = rzv2m_i2c_ids,
0523         .pm = pm_sleep_ptr(&rzv2m_i2c_pm_ops),
0524     },
0525     .probe  = rzv2m_i2c_probe,
0526     .remove = rzv2m_i2c_remove,
0527 };
0528 module_platform_driver(rzv2m_i2c_driver);
0529
0530 MODULE_DESCRIPTION("RZ/V2M I2C bus driver");
0531 MODULE_AUTHOR("Renesas Electronics Corporation");
0532 MODULE_LICENSE("GPL");