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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for I2C adapter in Rockchip RK3xxx SoC
0004  *
0005  * Max Schwarz <max.schwarz@online.de>
0006  * based on the patches by Rockchip Inc.
0007  */
0008 
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/i2c.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/errno.h>
0015 #include <linux/err.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/io.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/spinlock.h>
0021 #include <linux/clk.h>
0022 #include <linux/wait.h>
0023 #include <linux/mfd/syscon.h>
0024 #include <linux/regmap.h>
0025 #include <linux/math64.h>
0026 
0027 
0028 /* Register Map */
0029 #define REG_CON        0x00 /* control register */
0030 #define REG_CLKDIV     0x04 /* clock divisor register */
0031 #define REG_MRXADDR    0x08 /* slave address for REGISTER_TX */
0032 #define REG_MRXRADDR   0x0c /* slave register address for REGISTER_TX */
0033 #define REG_MTXCNT     0x10 /* number of bytes to be transmitted */
0034 #define REG_MRXCNT     0x14 /* number of bytes to be received */
0035 #define REG_IEN        0x18 /* interrupt enable */
0036 #define REG_IPD        0x1c /* interrupt pending */
0037 #define REG_FCNT       0x20 /* finished count */
0038 
0039 /* Data buffer offsets */
0040 #define TXBUFFER_BASE 0x100
0041 #define RXBUFFER_BASE 0x200
0042 
0043 /* REG_CON bits */
0044 #define REG_CON_EN        BIT(0)
0045 enum {
0046     REG_CON_MOD_TX = 0,      /* transmit data */
0047     REG_CON_MOD_REGISTER_TX, /* select register and restart */
0048     REG_CON_MOD_RX,          /* receive data */
0049     REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes
0050                   * register addr */
0051 };
0052 #define REG_CON_MOD(mod)  ((mod) << 1)
0053 #define REG_CON_MOD_MASK  (BIT(1) | BIT(2))
0054 #define REG_CON_START     BIT(3)
0055 #define REG_CON_STOP      BIT(4)
0056 #define REG_CON_LASTACK   BIT(5) /* 1: send NACK after last received byte */
0057 #define REG_CON_ACTACK    BIT(6) /* 1: stop if NACK is received */
0058 
0059 #define REG_CON_TUNING_MASK GENMASK_ULL(15, 8)
0060 
0061 #define REG_CON_SDA_CFG(cfg) ((cfg) << 8)
0062 #define REG_CON_STA_CFG(cfg) ((cfg) << 12)
0063 #define REG_CON_STO_CFG(cfg) ((cfg) << 14)
0064 
0065 /* REG_MRXADDR bits */
0066 #define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */
0067 
0068 /* REG_IEN/REG_IPD bits */
0069 #define REG_INT_BTF       BIT(0) /* a byte was transmitted */
0070 #define REG_INT_BRF       BIT(1) /* a byte was received */
0071 #define REG_INT_MBTF      BIT(2) /* master data transmit finished */
0072 #define REG_INT_MBRF      BIT(3) /* master data receive finished */
0073 #define REG_INT_START     BIT(4) /* START condition generated */
0074 #define REG_INT_STOP      BIT(5) /* STOP condition generated */
0075 #define REG_INT_NAKRCV    BIT(6) /* NACK received */
0076 #define REG_INT_ALL       0x7f
0077 
0078 /* Constants */
0079 #define WAIT_TIMEOUT      1000 /* ms */
0080 #define DEFAULT_SCL_RATE  (100 * 1000) /* Hz */
0081 
0082 /**
0083  * struct i2c_spec_values:
0084  * @min_hold_start_ns: min hold time (repeated) START condition
0085  * @min_low_ns: min LOW period of the SCL clock
0086  * @min_high_ns: min HIGH period of the SCL cloc
0087  * @min_setup_start_ns: min set-up time for a repeated START conditio
0088  * @max_data_hold_ns: max data hold time
0089  * @min_data_setup_ns: min data set-up time
0090  * @min_setup_stop_ns: min set-up time for STOP condition
0091  * @min_hold_buffer_ns: min bus free time between a STOP and
0092  * START condition
0093  */
0094 struct i2c_spec_values {
0095     unsigned long min_hold_start_ns;
0096     unsigned long min_low_ns;
0097     unsigned long min_high_ns;
0098     unsigned long min_setup_start_ns;
0099     unsigned long max_data_hold_ns;
0100     unsigned long min_data_setup_ns;
0101     unsigned long min_setup_stop_ns;
0102     unsigned long min_hold_buffer_ns;
0103 };
0104 
0105 static const struct i2c_spec_values standard_mode_spec = {
0106     .min_hold_start_ns = 4000,
0107     .min_low_ns = 4700,
0108     .min_high_ns = 4000,
0109     .min_setup_start_ns = 4700,
0110     .max_data_hold_ns = 3450,
0111     .min_data_setup_ns = 250,
0112     .min_setup_stop_ns = 4000,
0113     .min_hold_buffer_ns = 4700,
0114 };
0115 
0116 static const struct i2c_spec_values fast_mode_spec = {
0117     .min_hold_start_ns = 600,
0118     .min_low_ns = 1300,
0119     .min_high_ns = 600,
0120     .min_setup_start_ns = 600,
0121     .max_data_hold_ns = 900,
0122     .min_data_setup_ns = 100,
0123     .min_setup_stop_ns = 600,
0124     .min_hold_buffer_ns = 1300,
0125 };
0126 
0127 static const struct i2c_spec_values fast_mode_plus_spec = {
0128     .min_hold_start_ns = 260,
0129     .min_low_ns = 500,
0130     .min_high_ns = 260,
0131     .min_setup_start_ns = 260,
0132     .max_data_hold_ns = 400,
0133     .min_data_setup_ns = 50,
0134     .min_setup_stop_ns = 260,
0135     .min_hold_buffer_ns = 500,
0136 };
0137 
0138 /**
0139  * struct rk3x_i2c_calced_timings:
0140  * @div_low: Divider output for low
0141  * @div_high: Divider output for high
0142  * @tuning: Used to adjust setup/hold data time,
0143  * setup/hold start time and setup stop time for
0144  * v1's calc_timings, the tuning should all be 0
0145  * for old hardware anyone using v0's calc_timings.
0146  */
0147 struct rk3x_i2c_calced_timings {
0148     unsigned long div_low;
0149     unsigned long div_high;
0150     unsigned int tuning;
0151 };
0152 
0153 enum rk3x_i2c_state {
0154     STATE_IDLE,
0155     STATE_START,
0156     STATE_READ,
0157     STATE_WRITE,
0158     STATE_STOP
0159 };
0160 
0161 /**
0162  * struct rk3x_i2c_soc_data:
0163  * @grf_offset: offset inside the grf regmap for setting the i2c type
0164  * @calc_timings: Callback function for i2c timing information calculated
0165  */
0166 struct rk3x_i2c_soc_data {
0167     int grf_offset;
0168     int (*calc_timings)(unsigned long, struct i2c_timings *,
0169                 struct rk3x_i2c_calced_timings *);
0170 };
0171 
0172 /**
0173  * struct rk3x_i2c - private data of the controller
0174  * @adap: corresponding I2C adapter
0175  * @dev: device for this controller
0176  * @soc_data: related soc data struct
0177  * @regs: virtual memory area
0178  * @clk: function clk for rk3399 or function & Bus clks for others
0179  * @pclk: Bus clk for rk3399
0180  * @clk_rate_nb: i2c clk rate change notify
0181  * @t: I2C known timing information
0182  * @lock: spinlock for the i2c bus
0183  * @wait: the waitqueue to wait for i2c transfer
0184  * @busy: the condition for the event to wait for
0185  * @msg: current i2c message
0186  * @addr: addr of i2c slave device
0187  * @mode: mode of i2c transfer
0188  * @is_last_msg: flag determines whether it is the last msg in this transfer
0189  * @state: state of i2c transfer
0190  * @processed: byte length which has been send or received
0191  * @error: error code for i2c transfer
0192  */
0193 struct rk3x_i2c {
0194     struct i2c_adapter adap;
0195     struct device *dev;
0196     const struct rk3x_i2c_soc_data *soc_data;
0197 
0198     /* Hardware resources */
0199     void __iomem *regs;
0200     struct clk *clk;
0201     struct clk *pclk;
0202     struct notifier_block clk_rate_nb;
0203 
0204     /* Settings */
0205     struct i2c_timings t;
0206 
0207     /* Synchronization & notification */
0208     spinlock_t lock;
0209     wait_queue_head_t wait;
0210     bool busy;
0211 
0212     /* Current message */
0213     struct i2c_msg *msg;
0214     u8 addr;
0215     unsigned int mode;
0216     bool is_last_msg;
0217 
0218     /* I2C state machine */
0219     enum rk3x_i2c_state state;
0220     unsigned int processed;
0221     int error;
0222 };
0223 
0224 static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value,
0225                   unsigned int offset)
0226 {
0227     writel(value, i2c->regs + offset);
0228 }
0229 
0230 static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset)
0231 {
0232     return readl(i2c->regs + offset);
0233 }
0234 
0235 /* Reset all interrupt pending bits */
0236 static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c)
0237 {
0238     i2c_writel(i2c, REG_INT_ALL, REG_IPD);
0239 }
0240 
0241 /**
0242  * Generate a START condition, which triggers a REG_INT_START interrupt.
0243  */
0244 static void rk3x_i2c_start(struct rk3x_i2c *i2c)
0245 {
0246     u32 val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
0247 
0248     i2c_writel(i2c, REG_INT_START, REG_IEN);
0249 
0250     /* enable adapter with correct mode, send START condition */
0251     val |= REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START;
0252 
0253     /* if we want to react to NACK, set ACTACK bit */
0254     if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
0255         val |= REG_CON_ACTACK;
0256 
0257     i2c_writel(i2c, val, REG_CON);
0258 }
0259 
0260 /**
0261  * Generate a STOP condition, which triggers a REG_INT_STOP interrupt.
0262  *
0263  * @error: Error code to return in rk3x_i2c_xfer
0264  */
0265 static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error)
0266 {
0267     unsigned int ctrl;
0268 
0269     i2c->processed = 0;
0270     i2c->msg = NULL;
0271     i2c->error = error;
0272 
0273     if (i2c->is_last_msg) {
0274         /* Enable stop interrupt */
0275         i2c_writel(i2c, REG_INT_STOP, REG_IEN);
0276 
0277         i2c->state = STATE_STOP;
0278 
0279         ctrl = i2c_readl(i2c, REG_CON);
0280         ctrl |= REG_CON_STOP;
0281         i2c_writel(i2c, ctrl, REG_CON);
0282     } else {
0283         /* Signal rk3x_i2c_xfer to start the next message. */
0284         i2c->busy = false;
0285         i2c->state = STATE_IDLE;
0286 
0287         /*
0288          * The HW is actually not capable of REPEATED START. But we can
0289          * get the intended effect by resetting its internal state
0290          * and issuing an ordinary START.
0291          */
0292         ctrl = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
0293         i2c_writel(i2c, ctrl, REG_CON);
0294 
0295         /* signal that we are finished with the current msg */
0296         wake_up(&i2c->wait);
0297     }
0298 }
0299 
0300 /**
0301  * Setup a read according to i2c->msg
0302  */
0303 static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c)
0304 {
0305     unsigned int len = i2c->msg->len - i2c->processed;
0306     u32 con;
0307 
0308     con = i2c_readl(i2c, REG_CON);
0309 
0310     /*
0311      * The hw can read up to 32 bytes at a time. If we need more than one
0312      * chunk, send an ACK after the last byte of the current chunk.
0313      */
0314     if (len > 32) {
0315         len = 32;
0316         con &= ~REG_CON_LASTACK;
0317     } else {
0318         con |= REG_CON_LASTACK;
0319     }
0320 
0321     /* make sure we are in plain RX mode if we read a second chunk */
0322     if (i2c->processed != 0) {
0323         con &= ~REG_CON_MOD_MASK;
0324         con |= REG_CON_MOD(REG_CON_MOD_RX);
0325     }
0326 
0327     i2c_writel(i2c, con, REG_CON);
0328     i2c_writel(i2c, len, REG_MRXCNT);
0329 }
0330 
0331 /**
0332  * Fill the transmit buffer with data from i2c->msg
0333  */
0334 static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c)
0335 {
0336     unsigned int i, j;
0337     u32 cnt = 0;
0338     u32 val;
0339     u8 byte;
0340 
0341     for (i = 0; i < 8; ++i) {
0342         val = 0;
0343         for (j = 0; j < 4; ++j) {
0344             if ((i2c->processed == i2c->msg->len) && (cnt != 0))
0345                 break;
0346 
0347             if (i2c->processed == 0 && cnt == 0)
0348                 byte = (i2c->addr & 0x7f) << 1;
0349             else
0350                 byte = i2c->msg->buf[i2c->processed++];
0351 
0352             val |= byte << (j * 8);
0353             cnt++;
0354         }
0355 
0356         i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i);
0357 
0358         if (i2c->processed == i2c->msg->len)
0359             break;
0360     }
0361 
0362     i2c_writel(i2c, cnt, REG_MTXCNT);
0363 }
0364 
0365 
0366 /* IRQ handlers for individual states */
0367 
0368 static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd)
0369 {
0370     if (!(ipd & REG_INT_START)) {
0371         rk3x_i2c_stop(i2c, -EIO);
0372         dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
0373         rk3x_i2c_clean_ipd(i2c);
0374         return;
0375     }
0376 
0377     /* ack interrupt */
0378     i2c_writel(i2c, REG_INT_START, REG_IPD);
0379 
0380     /* disable start bit */
0381     i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON);
0382 
0383     /* enable appropriate interrupts and transition */
0384     if (i2c->mode == REG_CON_MOD_TX) {
0385         i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN);
0386         i2c->state = STATE_WRITE;
0387         rk3x_i2c_fill_transmit_buf(i2c);
0388     } else {
0389         /* in any other case, we are going to be reading. */
0390         i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN);
0391         i2c->state = STATE_READ;
0392         rk3x_i2c_prepare_read(i2c);
0393     }
0394 }
0395 
0396 static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd)
0397 {
0398     if (!(ipd & REG_INT_MBTF)) {
0399         rk3x_i2c_stop(i2c, -EIO);
0400         dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd);
0401         rk3x_i2c_clean_ipd(i2c);
0402         return;
0403     }
0404 
0405     /* ack interrupt */
0406     i2c_writel(i2c, REG_INT_MBTF, REG_IPD);
0407 
0408     /* are we finished? */
0409     if (i2c->processed == i2c->msg->len)
0410         rk3x_i2c_stop(i2c, i2c->error);
0411     else
0412         rk3x_i2c_fill_transmit_buf(i2c);
0413 }
0414 
0415 static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd)
0416 {
0417     unsigned int i;
0418     unsigned int len = i2c->msg->len - i2c->processed;
0419     u32 val;
0420     u8 byte;
0421 
0422     /* we only care for MBRF here. */
0423     if (!(ipd & REG_INT_MBRF))
0424         return;
0425 
0426     /* ack interrupt (read also produces a spurious START flag, clear it too) */
0427     i2c_writel(i2c, REG_INT_MBRF | REG_INT_START, REG_IPD);
0428 
0429     /* Can only handle a maximum of 32 bytes at a time */
0430     if (len > 32)
0431         len = 32;
0432 
0433     /* read the data from receive buffer */
0434     for (i = 0; i < len; ++i) {
0435         if (i % 4 == 0)
0436             val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4);
0437 
0438         byte = (val >> ((i % 4) * 8)) & 0xff;
0439         i2c->msg->buf[i2c->processed++] = byte;
0440     }
0441 
0442     /* are we finished? */
0443     if (i2c->processed == i2c->msg->len)
0444         rk3x_i2c_stop(i2c, i2c->error);
0445     else
0446         rk3x_i2c_prepare_read(i2c);
0447 }
0448 
0449 static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd)
0450 {
0451     unsigned int con;
0452 
0453     if (!(ipd & REG_INT_STOP)) {
0454         rk3x_i2c_stop(i2c, -EIO);
0455         dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd);
0456         rk3x_i2c_clean_ipd(i2c);
0457         return;
0458     }
0459 
0460     /* ack interrupt */
0461     i2c_writel(i2c, REG_INT_STOP, REG_IPD);
0462 
0463     /* disable STOP bit */
0464     con = i2c_readl(i2c, REG_CON);
0465     con &= ~REG_CON_STOP;
0466     i2c_writel(i2c, con, REG_CON);
0467 
0468     i2c->busy = false;
0469     i2c->state = STATE_IDLE;
0470 
0471     /* signal rk3x_i2c_xfer that we are finished */
0472     wake_up(&i2c->wait);
0473 }
0474 
0475 static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id)
0476 {
0477     struct rk3x_i2c *i2c = dev_id;
0478     unsigned int ipd;
0479 
0480     spin_lock(&i2c->lock);
0481 
0482     ipd = i2c_readl(i2c, REG_IPD);
0483     if (i2c->state == STATE_IDLE) {
0484         dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
0485         rk3x_i2c_clean_ipd(i2c);
0486         goto out;
0487     }
0488 
0489     dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd);
0490 
0491     /* Clean interrupt bits we don't care about */
0492     ipd &= ~(REG_INT_BRF | REG_INT_BTF);
0493 
0494     if (ipd & REG_INT_NAKRCV) {
0495         /*
0496          * We got a NACK in the last operation. Depending on whether
0497          * IGNORE_NAK is set, we have to stop the operation and report
0498          * an error.
0499          */
0500         i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD);
0501 
0502         ipd &= ~REG_INT_NAKRCV;
0503 
0504         if (!(i2c->msg->flags & I2C_M_IGNORE_NAK))
0505             rk3x_i2c_stop(i2c, -ENXIO);
0506     }
0507 
0508     /* is there anything left to handle? */
0509     if ((ipd & REG_INT_ALL) == 0)
0510         goto out;
0511 
0512     switch (i2c->state) {
0513     case STATE_START:
0514         rk3x_i2c_handle_start(i2c, ipd);
0515         break;
0516     case STATE_WRITE:
0517         rk3x_i2c_handle_write(i2c, ipd);
0518         break;
0519     case STATE_READ:
0520         rk3x_i2c_handle_read(i2c, ipd);
0521         break;
0522     case STATE_STOP:
0523         rk3x_i2c_handle_stop(i2c, ipd);
0524         break;
0525     case STATE_IDLE:
0526         break;
0527     }
0528 
0529 out:
0530     spin_unlock(&i2c->lock);
0531     return IRQ_HANDLED;
0532 }
0533 
0534 /**
0535  * Get timing values of I2C specification
0536  *
0537  * @speed: Desired SCL frequency
0538  *
0539  * Returns: Matched i2c spec values.
0540  */
0541 static const struct i2c_spec_values *rk3x_i2c_get_spec(unsigned int speed)
0542 {
0543     if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
0544         return &standard_mode_spec;
0545     else if (speed <= I2C_MAX_FAST_MODE_FREQ)
0546         return &fast_mode_spec;
0547     else
0548         return &fast_mode_plus_spec;
0549 }
0550 
0551 /**
0552  * Calculate divider values for desired SCL frequency
0553  *
0554  * @clk_rate: I2C input clock rate
0555  * @t: Known I2C timing information
0556  * @t_calc: Caculated rk3x private timings that would be written into regs
0557  *
0558  * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
0559  * a best-effort divider value is returned in divs. If the target rate is
0560  * too high, we silently use the highest possible rate.
0561  */
0562 static int rk3x_i2c_v0_calc_timings(unsigned long clk_rate,
0563                     struct i2c_timings *t,
0564                     struct rk3x_i2c_calced_timings *t_calc)
0565 {
0566     unsigned long min_low_ns, min_high_ns;
0567     unsigned long max_low_ns, min_total_ns;
0568 
0569     unsigned long clk_rate_khz, scl_rate_khz;
0570 
0571     unsigned long min_low_div, min_high_div;
0572     unsigned long max_low_div;
0573 
0574     unsigned long min_div_for_hold, min_total_div;
0575     unsigned long extra_div, extra_low_div, ideal_low_div;
0576 
0577     unsigned long data_hold_buffer_ns = 50;
0578     const struct i2c_spec_values *spec;
0579     int ret = 0;
0580 
0581     /* Only support standard-mode and fast-mode */
0582     if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ))
0583         t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
0584 
0585     /* prevent scl_rate_khz from becoming 0 */
0586     if (WARN_ON(t->bus_freq_hz < 1000))
0587         t->bus_freq_hz = 1000;
0588 
0589     /*
0590      * min_low_ns:  The minimum number of ns we need to hold low to
0591      *      meet I2C specification, should include fall time.
0592      * min_high_ns: The minimum number of ns we need to hold high to
0593      *      meet I2C specification, should include rise time.
0594      * max_low_ns:  The maximum number of ns we can hold low to meet
0595      *      I2C specification.
0596      *
0597      * Note: max_low_ns should be (maximum data hold time * 2 - buffer)
0598      *   This is because the i2c host on Rockchip holds the data line
0599      *   for half the low time.
0600      */
0601     spec = rk3x_i2c_get_spec(t->bus_freq_hz);
0602     min_high_ns = t->scl_rise_ns + spec->min_high_ns;
0603 
0604     /*
0605      * Timings for repeated start:
0606      * - controller appears to drop SDA at .875x (7/8) programmed clk high.
0607      * - controller appears to keep SCL high for 2x programmed clk high.
0608      *
0609      * We need to account for those rules in picking our "high" time so
0610      * we meet tSU;STA and tHD;STA times.
0611      */
0612     min_high_ns = max(min_high_ns, DIV_ROUND_UP(
0613         (t->scl_rise_ns + spec->min_setup_start_ns) * 1000, 875));
0614     min_high_ns = max(min_high_ns, DIV_ROUND_UP(
0615         (t->scl_rise_ns + spec->min_setup_start_ns + t->sda_fall_ns +
0616         spec->min_high_ns), 2));
0617 
0618     min_low_ns = t->scl_fall_ns + spec->min_low_ns;
0619     max_low_ns =  spec->max_data_hold_ns * 2 - data_hold_buffer_ns;
0620     min_total_ns = min_low_ns + min_high_ns;
0621 
0622     /* Adjust to avoid overflow */
0623     clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
0624     scl_rate_khz = t->bus_freq_hz / 1000;
0625 
0626     /*
0627      * We need the total div to be >= this number
0628      * so we don't clock too fast.
0629      */
0630     min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
0631 
0632     /* These are the min dividers needed for min hold times. */
0633     min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
0634     min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
0635     min_div_for_hold = (min_low_div + min_high_div);
0636 
0637     /*
0638      * This is the maximum divider so we don't go over the maximum.
0639      * We don't round up here (we round down) since this is a maximum.
0640      */
0641     max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
0642 
0643     if (min_low_div > max_low_div) {
0644         WARN_ONCE(true,
0645               "Conflicting, min_low_div %lu, max_low_div %lu\n",
0646               min_low_div, max_low_div);
0647         max_low_div = min_low_div;
0648     }
0649 
0650     if (min_div_for_hold > min_total_div) {
0651         /*
0652          * Time needed to meet hold requirements is important.
0653          * Just use that.
0654          */
0655         t_calc->div_low = min_low_div;
0656         t_calc->div_high = min_high_div;
0657     } else {
0658         /*
0659          * We've got to distribute some time among the low and high
0660          * so we don't run too fast.
0661          */
0662         extra_div = min_total_div - min_div_for_hold;
0663 
0664         /*
0665          * We'll try to split things up perfectly evenly,
0666          * biasing slightly towards having a higher div
0667          * for low (spend more time low).
0668          */
0669         ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
0670                          scl_rate_khz * 8 * min_total_ns);
0671 
0672         /* Don't allow it to go over the maximum */
0673         if (ideal_low_div > max_low_div)
0674             ideal_low_div = max_low_div;
0675 
0676         /*
0677          * Handle when the ideal low div is going to take up
0678          * more than we have.
0679          */
0680         if (ideal_low_div > min_low_div + extra_div)
0681             ideal_low_div = min_low_div + extra_div;
0682 
0683         /* Give low the "ideal" and give high whatever extra is left */
0684         extra_low_div = ideal_low_div - min_low_div;
0685         t_calc->div_low = ideal_low_div;
0686         t_calc->div_high = min_high_div + (extra_div - extra_low_div);
0687     }
0688 
0689     /*
0690      * Adjust to the fact that the hardware has an implicit "+1".
0691      * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
0692      */
0693     t_calc->div_low--;
0694     t_calc->div_high--;
0695 
0696     /* Give the tuning value 0, that would not update con register */
0697     t_calc->tuning = 0;
0698     /* Maximum divider supported by hw is 0xffff */
0699     if (t_calc->div_low > 0xffff) {
0700         t_calc->div_low = 0xffff;
0701         ret = -EINVAL;
0702     }
0703 
0704     if (t_calc->div_high > 0xffff) {
0705         t_calc->div_high = 0xffff;
0706         ret = -EINVAL;
0707     }
0708 
0709     return ret;
0710 }
0711 
0712 /**
0713  * Calculate timing values for desired SCL frequency
0714  *
0715  * @clk_rate: I2C input clock rate
0716  * @t: Known I2C timing information
0717  * @t_calc: Caculated rk3x private timings that would be written into regs
0718  *
0719  * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
0720  * a best-effort divider value is returned in divs. If the target rate is
0721  * too high, we silently use the highest possible rate.
0722  * The following formulas are v1's method to calculate timings.
0723  *
0724  * l = divl + 1;
0725  * h = divh + 1;
0726  * s = sda_update_config + 1;
0727  * u = start_setup_config + 1;
0728  * p = stop_setup_config + 1;
0729  * T = Tclk_i2c;
0730  *
0731  * tHigh = 8 * h * T;
0732  * tLow = 8 * l * T;
0733  *
0734  * tHD;sda = (l * s + 1) * T;
0735  * tSU;sda = [(8 - s) * l + 1] * T;
0736  * tI2C = 8 * (l + h) * T;
0737  *
0738  * tSU;sta = (8h * u + 1) * T;
0739  * tHD;sta = [8h * (u + 1) - 1] * T;
0740  * tSU;sto = (8h * p + 1) * T;
0741  */
0742 static int rk3x_i2c_v1_calc_timings(unsigned long clk_rate,
0743                     struct i2c_timings *t,
0744                     struct rk3x_i2c_calced_timings *t_calc)
0745 {
0746     unsigned long min_low_ns, min_high_ns;
0747     unsigned long min_setup_start_ns, min_setup_data_ns;
0748     unsigned long min_setup_stop_ns, max_hold_data_ns;
0749 
0750     unsigned long clk_rate_khz, scl_rate_khz;
0751 
0752     unsigned long min_low_div, min_high_div;
0753 
0754     unsigned long min_div_for_hold, min_total_div;
0755     unsigned long extra_div, extra_low_div;
0756     unsigned long sda_update_cfg, stp_sta_cfg, stp_sto_cfg;
0757 
0758     const struct i2c_spec_values *spec;
0759     int ret = 0;
0760 
0761     /* Support standard-mode, fast-mode and fast-mode plus */
0762     if (WARN_ON(t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ))
0763         t->bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
0764 
0765     /* prevent scl_rate_khz from becoming 0 */
0766     if (WARN_ON(t->bus_freq_hz < 1000))
0767         t->bus_freq_hz = 1000;
0768 
0769     /*
0770      * min_low_ns: The minimum number of ns we need to hold low to
0771      *         meet I2C specification, should include fall time.
0772      * min_high_ns: The minimum number of ns we need to hold high to
0773      *          meet I2C specification, should include rise time.
0774      */
0775     spec = rk3x_i2c_get_spec(t->bus_freq_hz);
0776 
0777     /* calculate min-divh and min-divl */
0778     clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
0779     scl_rate_khz = t->bus_freq_hz / 1000;
0780     min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
0781 
0782     min_high_ns = t->scl_rise_ns + spec->min_high_ns;
0783     min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
0784 
0785     min_low_ns = t->scl_fall_ns + spec->min_low_ns;
0786     min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
0787 
0788     /*
0789      * Final divh and divl must be greater than 0, otherwise the
0790      * hardware would not output the i2c clk.
0791      */
0792     min_high_div = (min_high_div < 1) ? 2 : min_high_div;
0793     min_low_div = (min_low_div < 1) ? 2 : min_low_div;
0794 
0795     /* These are the min dividers needed for min hold times. */
0796     min_div_for_hold = (min_low_div + min_high_div);
0797 
0798     /*
0799      * This is the maximum divider so we don't go over the maximum.
0800      * We don't round up here (we round down) since this is a maximum.
0801      */
0802     if (min_div_for_hold >= min_total_div) {
0803         /*
0804          * Time needed to meet hold requirements is important.
0805          * Just use that.
0806          */
0807         t_calc->div_low = min_low_div;
0808         t_calc->div_high = min_high_div;
0809     } else {
0810         /*
0811          * We've got to distribute some time among the low and high
0812          * so we don't run too fast.
0813          * We'll try to split things up by the scale of min_low_div and
0814          * min_high_div, biasing slightly towards having a higher div
0815          * for low (spend more time low).
0816          */
0817         extra_div = min_total_div - min_div_for_hold;
0818         extra_low_div = DIV_ROUND_UP(min_low_div * extra_div,
0819                          min_div_for_hold);
0820 
0821         t_calc->div_low = min_low_div + extra_low_div;
0822         t_calc->div_high = min_high_div + (extra_div - extra_low_div);
0823     }
0824 
0825     /*
0826      * calculate sda data hold count by the rules, data_upd_st:3
0827      * is a appropriate value to reduce calculated times.
0828      */
0829     for (sda_update_cfg = 3; sda_update_cfg > 0; sda_update_cfg--) {
0830         max_hold_data_ns =  DIV_ROUND_UP((sda_update_cfg
0831                          * (t_calc->div_low) + 1)
0832                          * 1000000, clk_rate_khz);
0833         min_setup_data_ns =  DIV_ROUND_UP(((8 - sda_update_cfg)
0834                          * (t_calc->div_low) + 1)
0835                          * 1000000, clk_rate_khz);
0836         if ((max_hold_data_ns < spec->max_data_hold_ns) &&
0837             (min_setup_data_ns > spec->min_data_setup_ns))
0838             break;
0839     }
0840 
0841     /* calculate setup start config */
0842     min_setup_start_ns = t->scl_rise_ns + spec->min_setup_start_ns;
0843     stp_sta_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_start_ns
0844                - 1000000, 8 * 1000000 * (t_calc->div_high));
0845 
0846     /* calculate setup stop config */
0847     min_setup_stop_ns = t->scl_rise_ns + spec->min_setup_stop_ns;
0848     stp_sto_cfg = DIV_ROUND_UP(clk_rate_khz * min_setup_stop_ns
0849                - 1000000, 8 * 1000000 * (t_calc->div_high));
0850 
0851     t_calc->tuning = REG_CON_SDA_CFG(--sda_update_cfg) |
0852              REG_CON_STA_CFG(--stp_sta_cfg) |
0853              REG_CON_STO_CFG(--stp_sto_cfg);
0854 
0855     t_calc->div_low--;
0856     t_calc->div_high--;
0857 
0858     /* Maximum divider supported by hw is 0xffff */
0859     if (t_calc->div_low > 0xffff) {
0860         t_calc->div_low = 0xffff;
0861         ret = -EINVAL;
0862     }
0863 
0864     if (t_calc->div_high > 0xffff) {
0865         t_calc->div_high = 0xffff;
0866         ret = -EINVAL;
0867     }
0868 
0869     return ret;
0870 }
0871 
0872 static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
0873 {
0874     struct i2c_timings *t = &i2c->t;
0875     struct rk3x_i2c_calced_timings calc;
0876     u64 t_low_ns, t_high_ns;
0877     unsigned long flags;
0878     u32 val;
0879     int ret;
0880 
0881     ret = i2c->soc_data->calc_timings(clk_rate, t, &calc);
0882     WARN_ONCE(ret != 0, "Could not reach SCL freq %u", t->bus_freq_hz);
0883 
0884     clk_enable(i2c->pclk);
0885 
0886     spin_lock_irqsave(&i2c->lock, flags);
0887     val = i2c_readl(i2c, REG_CON);
0888     val &= ~REG_CON_TUNING_MASK;
0889     val |= calc.tuning;
0890     i2c_writel(i2c, val, REG_CON);
0891     i2c_writel(i2c, (calc.div_high << 16) | (calc.div_low & 0xffff),
0892            REG_CLKDIV);
0893     spin_unlock_irqrestore(&i2c->lock, flags);
0894 
0895     clk_disable(i2c->pclk);
0896 
0897     t_low_ns = div_u64(((u64)calc.div_low + 1) * 8 * 1000000000, clk_rate);
0898     t_high_ns = div_u64(((u64)calc.div_high + 1) * 8 * 1000000000,
0899                 clk_rate);
0900     dev_dbg(i2c->dev,
0901         "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
0902         clk_rate / 1000,
0903         1000000000 / t->bus_freq_hz,
0904         t_low_ns, t_high_ns);
0905 }
0906 
0907 /**
0908  * rk3x_i2c_clk_notifier_cb - Clock rate change callback
0909  * @nb:     Pointer to notifier block
0910  * @event:  Notification reason
0911  * @data:   Pointer to notification data object
0912  *
0913  * The callback checks whether a valid bus frequency can be generated after the
0914  * change. If so, the change is acknowledged, otherwise the change is aborted.
0915  * New dividers are written to the HW in the pre- or post change notification
0916  * depending on the scaling direction.
0917  *
0918  * Code adapted from i2c-cadence.c.
0919  *
0920  * Return:  NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
0921  *      to acknowledge the change, NOTIFY_DONE if the notification is
0922  *      considered irrelevant.
0923  */
0924 static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
0925                     event, void *data)
0926 {
0927     struct clk_notifier_data *ndata = data;
0928     struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
0929     struct rk3x_i2c_calced_timings calc;
0930 
0931     switch (event) {
0932     case PRE_RATE_CHANGE:
0933         /*
0934          * Try the calculation (but don't store the result) ahead of
0935          * time to see if we need to block the clock change.  Timings
0936          * shouldn't actually take effect until rk3x_i2c_adapt_div().
0937          */
0938         if (i2c->soc_data->calc_timings(ndata->new_rate, &i2c->t,
0939                         &calc) != 0)
0940             return NOTIFY_STOP;
0941 
0942         /* scale up */
0943         if (ndata->new_rate > ndata->old_rate)
0944             rk3x_i2c_adapt_div(i2c, ndata->new_rate);
0945 
0946         return NOTIFY_OK;
0947     case POST_RATE_CHANGE:
0948         /* scale down */
0949         if (ndata->new_rate < ndata->old_rate)
0950             rk3x_i2c_adapt_div(i2c, ndata->new_rate);
0951         return NOTIFY_OK;
0952     case ABORT_RATE_CHANGE:
0953         /* scale up */
0954         if (ndata->new_rate > ndata->old_rate)
0955             rk3x_i2c_adapt_div(i2c, ndata->old_rate);
0956         return NOTIFY_OK;
0957     default:
0958         return NOTIFY_DONE;
0959     }
0960 }
0961 
0962 /**
0963  * Setup I2C registers for an I2C operation specified by msgs, num.
0964  *
0965  * Must be called with i2c->lock held.
0966  *
0967  * @msgs: I2C msgs to process
0968  * @num: Number of msgs
0969  *
0970  * returns: Number of I2C msgs processed or negative in case of error
0971  */
0972 static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num)
0973 {
0974     u32 addr = (msgs[0].addr & 0x7f) << 1;
0975     int ret = 0;
0976 
0977     /*
0978      * The I2C adapter can issue a small (len < 4) write packet before
0979      * reading. This speeds up SMBus-style register reads.
0980      * The MRXADDR/MRXRADDR hold the slave address and the slave register
0981      * address in this case.
0982      */
0983 
0984     if (num >= 2 && msgs[0].len < 4 &&
0985         !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) {
0986         u32 reg_addr = 0;
0987         int i;
0988 
0989         dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n",
0990             addr >> 1);
0991 
0992         /* Fill MRXRADDR with the register address(es) */
0993         for (i = 0; i < msgs[0].len; ++i) {
0994             reg_addr |= msgs[0].buf[i] << (i * 8);
0995             reg_addr |= REG_MRXADDR_VALID(i);
0996         }
0997 
0998         /* msgs[0] is handled by hw. */
0999         i2c->msg = &msgs[1];
1000 
1001         i2c->mode = REG_CON_MOD_REGISTER_TX;
1002 
1003         i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR);
1004         i2c_writel(i2c, reg_addr, REG_MRXRADDR);
1005 
1006         ret = 2;
1007     } else {
1008         /*
1009          * We'll have to do it the boring way and process the msgs
1010          * one-by-one.
1011          */
1012 
1013         if (msgs[0].flags & I2C_M_RD) {
1014             addr |= 1; /* set read bit */
1015 
1016             /*
1017              * We have to transmit the slave addr first. Use
1018              * MOD_REGISTER_TX for that purpose.
1019              */
1020             i2c->mode = REG_CON_MOD_REGISTER_TX;
1021             i2c_writel(i2c, addr | REG_MRXADDR_VALID(0),
1022                    REG_MRXADDR);
1023             i2c_writel(i2c, 0, REG_MRXRADDR);
1024         } else {
1025             i2c->mode = REG_CON_MOD_TX;
1026         }
1027 
1028         i2c->msg = &msgs[0];
1029 
1030         ret = 1;
1031     }
1032 
1033     i2c->addr = msgs[0].addr;
1034     i2c->busy = true;
1035     i2c->state = STATE_START;
1036     i2c->processed = 0;
1037     i2c->error = 0;
1038 
1039     rk3x_i2c_clean_ipd(i2c);
1040 
1041     return ret;
1042 }
1043 
1044 static int rk3x_i2c_wait_xfer_poll(struct rk3x_i2c *i2c)
1045 {
1046     ktime_t timeout = ktime_add_ms(ktime_get(), WAIT_TIMEOUT);
1047 
1048     while (READ_ONCE(i2c->busy) &&
1049            ktime_compare(ktime_get(), timeout) < 0) {
1050         udelay(5);
1051         rk3x_i2c_irq(0, i2c);
1052     }
1053 
1054     return !i2c->busy;
1055 }
1056 
1057 static int rk3x_i2c_xfer_common(struct i2c_adapter *adap,
1058                 struct i2c_msg *msgs, int num, bool polling)
1059 {
1060     struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data;
1061     unsigned long timeout, flags;
1062     u32 val;
1063     int ret = 0;
1064     int i;
1065 
1066     spin_lock_irqsave(&i2c->lock, flags);
1067 
1068     clk_enable(i2c->clk);
1069     clk_enable(i2c->pclk);
1070 
1071     i2c->is_last_msg = false;
1072 
1073     /*
1074      * Process msgs. We can handle more than one message at once (see
1075      * rk3x_i2c_setup()).
1076      */
1077     for (i = 0; i < num; i += ret) {
1078         ret = rk3x_i2c_setup(i2c, msgs + i, num - i);
1079 
1080         if (ret < 0) {
1081             dev_err(i2c->dev, "rk3x_i2c_setup() failed\n");
1082             break;
1083         }
1084 
1085         if (i + ret >= num)
1086             i2c->is_last_msg = true;
1087 
1088         spin_unlock_irqrestore(&i2c->lock, flags);
1089 
1090         rk3x_i2c_start(i2c);
1091 
1092         if (!polling) {
1093             timeout = wait_event_timeout(i2c->wait, !i2c->busy,
1094                              msecs_to_jiffies(WAIT_TIMEOUT));
1095         } else {
1096             timeout = rk3x_i2c_wait_xfer_poll(i2c);
1097         }
1098 
1099         spin_lock_irqsave(&i2c->lock, flags);
1100 
1101         if (timeout == 0) {
1102             dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n",
1103                 i2c_readl(i2c, REG_IPD), i2c->state);
1104 
1105             /* Force a STOP condition without interrupt */
1106             i2c_writel(i2c, 0, REG_IEN);
1107             val = i2c_readl(i2c, REG_CON) & REG_CON_TUNING_MASK;
1108             val |= REG_CON_EN | REG_CON_STOP;
1109             i2c_writel(i2c, val, REG_CON);
1110 
1111             i2c->state = STATE_IDLE;
1112 
1113             ret = -ETIMEDOUT;
1114             break;
1115         }
1116 
1117         if (i2c->error) {
1118             ret = i2c->error;
1119             break;
1120         }
1121     }
1122 
1123     clk_disable(i2c->pclk);
1124     clk_disable(i2c->clk);
1125 
1126     spin_unlock_irqrestore(&i2c->lock, flags);
1127 
1128     return ret < 0 ? ret : num;
1129 }
1130 
1131 static int rk3x_i2c_xfer(struct i2c_adapter *adap,
1132              struct i2c_msg *msgs, int num)
1133 {
1134     return rk3x_i2c_xfer_common(adap, msgs, num, false);
1135 }
1136 
1137 static int rk3x_i2c_xfer_polling(struct i2c_adapter *adap,
1138                  struct i2c_msg *msgs, int num)
1139 {
1140     return rk3x_i2c_xfer_common(adap, msgs, num, true);
1141 }
1142 
1143 static __maybe_unused int rk3x_i2c_resume(struct device *dev)
1144 {
1145     struct rk3x_i2c *i2c = dev_get_drvdata(dev);
1146 
1147     rk3x_i2c_adapt_div(i2c, clk_get_rate(i2c->clk));
1148 
1149     return 0;
1150 }
1151 
1152 static u32 rk3x_i2c_func(struct i2c_adapter *adap)
1153 {
1154     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
1155 }
1156 
1157 static const struct i2c_algorithm rk3x_i2c_algorithm = {
1158     .master_xfer        = rk3x_i2c_xfer,
1159     .master_xfer_atomic = rk3x_i2c_xfer_polling,
1160     .functionality      = rk3x_i2c_func,
1161 };
1162 
1163 static const struct rk3x_i2c_soc_data rv1108_soc_data = {
1164     .grf_offset = -1,
1165     .calc_timings = rk3x_i2c_v1_calc_timings,
1166 };
1167 
1168 static const struct rk3x_i2c_soc_data rk3066_soc_data = {
1169     .grf_offset = 0x154,
1170     .calc_timings = rk3x_i2c_v0_calc_timings,
1171 };
1172 
1173 static const struct rk3x_i2c_soc_data rk3188_soc_data = {
1174     .grf_offset = 0x0a4,
1175     .calc_timings = rk3x_i2c_v0_calc_timings,
1176 };
1177 
1178 static const struct rk3x_i2c_soc_data rk3228_soc_data = {
1179     .grf_offset = -1,
1180     .calc_timings = rk3x_i2c_v0_calc_timings,
1181 };
1182 
1183 static const struct rk3x_i2c_soc_data rk3288_soc_data = {
1184     .grf_offset = -1,
1185     .calc_timings = rk3x_i2c_v0_calc_timings,
1186 };
1187 
1188 static const struct rk3x_i2c_soc_data rk3399_soc_data = {
1189     .grf_offset = -1,
1190     .calc_timings = rk3x_i2c_v1_calc_timings,
1191 };
1192 
1193 static const struct of_device_id rk3x_i2c_match[] = {
1194     {
1195         .compatible = "rockchip,rv1108-i2c",
1196         .data = &rv1108_soc_data
1197     },
1198     {
1199         .compatible = "rockchip,rk3066-i2c",
1200         .data = &rk3066_soc_data
1201     },
1202     {
1203         .compatible = "rockchip,rk3188-i2c",
1204         .data = &rk3188_soc_data
1205     },
1206     {
1207         .compatible = "rockchip,rk3228-i2c",
1208         .data = &rk3228_soc_data
1209     },
1210     {
1211         .compatible = "rockchip,rk3288-i2c",
1212         .data = &rk3288_soc_data
1213     },
1214     {
1215         .compatible = "rockchip,rk3399-i2c",
1216         .data = &rk3399_soc_data
1217     },
1218     {},
1219 };
1220 MODULE_DEVICE_TABLE(of, rk3x_i2c_match);
1221 
1222 static int rk3x_i2c_probe(struct platform_device *pdev)
1223 {
1224     struct device_node *np = pdev->dev.of_node;
1225     const struct of_device_id *match;
1226     struct rk3x_i2c *i2c;
1227     int ret = 0;
1228     int bus_nr;
1229     u32 value;
1230     int irq;
1231     unsigned long clk_rate;
1232 
1233     i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
1234     if (!i2c)
1235         return -ENOMEM;
1236 
1237     match = of_match_node(rk3x_i2c_match, np);
1238     i2c->soc_data = match->data;
1239 
1240     /* use common interface to get I2C timing properties */
1241     i2c_parse_fw_timings(&pdev->dev, &i2c->t, true);
1242 
1243     strscpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name));
1244     i2c->adap.owner = THIS_MODULE;
1245     i2c->adap.algo = &rk3x_i2c_algorithm;
1246     i2c->adap.retries = 3;
1247     i2c->adap.dev.of_node = np;
1248     i2c->adap.algo_data = i2c;
1249     i2c->adap.dev.parent = &pdev->dev;
1250 
1251     i2c->dev = &pdev->dev;
1252 
1253     spin_lock_init(&i2c->lock);
1254     init_waitqueue_head(&i2c->wait);
1255 
1256     i2c->regs = devm_platform_ioremap_resource(pdev, 0);
1257     if (IS_ERR(i2c->regs))
1258         return PTR_ERR(i2c->regs);
1259 
1260     /* Try to set the I2C adapter number from dt */
1261     bus_nr = of_alias_get_id(np, "i2c");
1262 
1263     /*
1264      * Switch to new interface if the SoC also offers the old one.
1265      * The control bit is located in the GRF register space.
1266      */
1267     if (i2c->soc_data->grf_offset >= 0) {
1268         struct regmap *grf;
1269 
1270         grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1271         if (IS_ERR(grf)) {
1272             dev_err(&pdev->dev,
1273                 "rk3x-i2c needs 'rockchip,grf' property\n");
1274             return PTR_ERR(grf);
1275         }
1276 
1277         if (bus_nr < 0) {
1278             dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias");
1279             return -EINVAL;
1280         }
1281 
1282         /* 27+i: write mask, 11+i: value */
1283         value = BIT(27 + bus_nr) | BIT(11 + bus_nr);
1284 
1285         ret = regmap_write(grf, i2c->soc_data->grf_offset, value);
1286         if (ret != 0) {
1287             dev_err(i2c->dev, "Could not write to GRF: %d\n", ret);
1288             return ret;
1289         }
1290     }
1291 
1292     /* IRQ setup */
1293     irq = platform_get_irq(pdev, 0);
1294     if (irq < 0)
1295         return irq;
1296 
1297     ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq,
1298                    0, dev_name(&pdev->dev), i2c);
1299     if (ret < 0) {
1300         dev_err(&pdev->dev, "cannot request IRQ\n");
1301         return ret;
1302     }
1303 
1304     platform_set_drvdata(pdev, i2c);
1305 
1306     if (i2c->soc_data->calc_timings == rk3x_i2c_v0_calc_timings) {
1307         /* Only one clock to use for bus clock and peripheral clock */
1308         i2c->clk = devm_clk_get(&pdev->dev, NULL);
1309         i2c->pclk = i2c->clk;
1310     } else {
1311         i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1312         i2c->pclk = devm_clk_get(&pdev->dev, "pclk");
1313     }
1314 
1315     if (IS_ERR(i2c->clk))
1316         return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk),
1317                      "Can't get bus clk\n");
1318 
1319     if (IS_ERR(i2c->pclk))
1320         return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),
1321                      "Can't get periph clk\n");
1322 
1323     ret = clk_prepare(i2c->clk);
1324     if (ret < 0) {
1325         dev_err(&pdev->dev, "Can't prepare bus clk: %d\n", ret);
1326         return ret;
1327     }
1328     ret = clk_prepare(i2c->pclk);
1329     if (ret < 0) {
1330         dev_err(&pdev->dev, "Can't prepare periph clock: %d\n", ret);
1331         goto err_clk;
1332     }
1333 
1334     i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
1335     ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
1336     if (ret != 0) {
1337         dev_err(&pdev->dev, "Unable to register clock notifier\n");
1338         goto err_pclk;
1339     }
1340 
1341     ret = clk_enable(i2c->clk);
1342     if (ret < 0) {
1343         dev_err(&pdev->dev, "Can't enable bus clk: %d\n", ret);
1344         goto err_clk_notifier;
1345     }
1346 
1347     clk_rate = clk_get_rate(i2c->clk);
1348     rk3x_i2c_adapt_div(i2c, clk_rate);
1349     clk_disable(i2c->clk);
1350 
1351     ret = i2c_add_adapter(&i2c->adap);
1352     if (ret < 0)
1353         goto err_clk_notifier;
1354 
1355     return 0;
1356 
1357 err_clk_notifier:
1358     clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1359 err_pclk:
1360     clk_unprepare(i2c->pclk);
1361 err_clk:
1362     clk_unprepare(i2c->clk);
1363     return ret;
1364 }
1365 
1366 static int rk3x_i2c_remove(struct platform_device *pdev)
1367 {
1368     struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
1369 
1370     i2c_del_adapter(&i2c->adap);
1371 
1372     clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
1373     clk_unprepare(i2c->pclk);
1374     clk_unprepare(i2c->clk);
1375 
1376     return 0;
1377 }
1378 
1379 static SIMPLE_DEV_PM_OPS(rk3x_i2c_pm_ops, NULL, rk3x_i2c_resume);
1380 
1381 static struct platform_driver rk3x_i2c_driver = {
1382     .probe   = rk3x_i2c_probe,
1383     .remove  = rk3x_i2c_remove,
1384     .driver  = {
1385         .name  = "rk3x-i2c",
1386         .of_match_table = rk3x_i2c_match,
1387         .pm = &rk3x_i2c_pm_ops,
1388     },
1389 };
1390 
1391 module_platform_driver(rk3x_i2c_driver);
1392 
1393 MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver");
1394 MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>");
1395 MODULE_LICENSE("GPL v2");
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