i2c/busses/i2c-riic.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas RIIC driver
0004  *
0005  * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
0006  * Copyright (C) 2013 Renesas Solutions Corp.
0007  */
0008
0009 /*
0010  * This i2c core has a lot of interrupts, namely 8. We use their chaining as
0011  * some kind of state machine.
0012  *
0013  * 1) The main xfer routine kicks off a transmission by putting the start bit
0014  * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
0015  * since we need to send the slave address + RW bit in every case.
0016  *
0017  * 2) TIE sends slave address + RW bit and selects how to continue.
0018  *
0019  * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
0020  * are done, we switch over to the transmission done interrupt (TEIE) and mark
0021  * the message as completed (includes sending STOP) there.
0022  *
0023  * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
0024  * needed to start clocking, then we keep receiving until we are done. Note
0025  * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
0026  * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
0027  * message to create the final NACK as sketched in the datasheet. This caused
0028  * some subtle races (when byte n was processed and byte n+1 was already
0029  * waiting), though, and I started with the safe approach.
0030  *
0031  * 4) If we got a NACK somewhere, we flag the error and stop the transmission
0032  * via NAKIE.
0033  *
0034  * Also check the comments in the interrupt routines for some gory details.
0035  */
0036
0037 #include <linux/clk.h>
0038 #include <linux/completion.h>
0039 #include <linux/err.h>
0040 #include <linux/i2c.h>
0041 #include <linux/interrupt.h>
0042 #include <linux/io.h>
0043 #include <linux/module.h>
0044 #include <linux/of.h>
0045 #include <linux/of_device.h>
0046 #include <linux/platform_device.h>
0047 #include <linux/pm_runtime.h>
0048 #include <linux/reset.h>
0049
0050 #define RIIC_ICCR1  0x00
0051 #define RIIC_ICCR2  0x04
0052 #define RIIC_ICMR1  0x08
0053 #define RIIC_ICMR3  0x10
0054 #define RIIC_ICSER  0x18
0055 #define RIIC_ICIER  0x1c
0056 #define RIIC_ICSR2  0x24
0057 #define RIIC_ICBRL  0x34
0058 #define RIIC_ICBRH  0x38
0059 #define RIIC_ICDRT  0x3c
0060 #define RIIC_ICDRR  0x40
0061
0062 #define ICCR1_ICE   0x80
0063 #define ICCR1_IICRST    0x40
0064 #define ICCR1_SOWP  0x10
0065
0066 #define ICCR2_BBSY  0x80
0067 #define ICCR2_SP    0x08
0068 #define ICCR2_RS    0x04
0069 #define ICCR2_ST    0x02
0070
0071 #define ICMR1_CKS_MASK  0x70
0072 #define ICMR1_BCWP  0x08
0073 #define ICMR1_CKS(_x)   ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
0074
0075 #define ICMR3_RDRFS 0x20
0076 #define ICMR3_ACKWP 0x10
0077 #define ICMR3_ACKBT 0x08
0078
0079 #define ICIER_TIE   0x80
0080 #define ICIER_TEIE  0x40
0081 #define ICIER_RIE   0x20
0082 #define ICIER_NAKIE 0x10
0083 #define ICIER_SPIE  0x08
0084
0085 #define ICSR2_NACKF 0x10
0086
0087 #define ICBR_RESERVED   0xe0 /* Should be 1 on writes */
0088
0089 #define RIIC_INIT_MSG   -1
0090
0091 struct riic_dev {
0092     void __iomem *base;
0093     u8 *buf;
0094     struct i2c_msg *msg;
0095     int bytes_left;
0096     int err;
0097     int is_last;
0098     struct completion msg_done;
0099     struct i2c_adapter adapter;
0100     struct clk *clk;
0101 };
0102
0103 struct riic_irq_desc {
0104     int res_num;
0105     irq_handler_t isr;
0106     char *name;
0107 };
0108
0109 static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
0110 {
0111     writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
0112 }
0113
0114 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
0115 {
0116     struct riic_dev *riic = i2c_get_adapdata(adap);
0117     unsigned long time_left;
0118     int i;
0119     u8 start_bit;
0120
0121     pm_runtime_get_sync(adap->dev.parent);
0122
0123     if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
0124         riic->err = -EBUSY;
0125         goto out;
0126     }
0127
0128     reinit_completion(&riic->msg_done);
0129     riic->err = 0;
0130
0131     writeb(0, riic->base + RIIC_ICSR2);
0132
0133     for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
0134         riic->bytes_left = RIIC_INIT_MSG;
0135         riic->buf = msgs[i].buf;
0136         riic->msg = &msgs[i];
0137         riic->is_last = (i == num - 1);
0138
0139         writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
0140
0141         writeb(start_bit, riic->base + RIIC_ICCR2);
0142
0143         time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
0144         if (time_left == 0)
0145             riic->err = -ETIMEDOUT;
0146
0147         if (riic->err)
0148             break;
0149
0150         start_bit = ICCR2_RS;
0151     }
0152
0153  out:
0154     pm_runtime_put(adap->dev.parent);
0155
0156     return riic->err ?: num;
0157 }
0158
0159 static irqreturn_t riic_tdre_isr(int irq, void *data)
0160 {
0161     struct riic_dev *riic = data;
0162     u8 val;
0163
0164     if (!riic->bytes_left)
0165         return IRQ_NONE;
0166
0167     if (riic->bytes_left == RIIC_INIT_MSG) {
0168         if (riic->msg->flags & I2C_M_RD)
0169             /* On read, switch over to receive interrupt */
0170             riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
0171         else
0172             /* On write, initialize length */
0173             riic->bytes_left = riic->msg->len;
0174
0175         val = i2c_8bit_addr_from_msg(riic->msg);
0176     } else {
0177         val = *riic->buf;
0178         riic->buf++;
0179         riic->bytes_left--;
0180     }
0181
0182     /*
0183      * Switch to transmission ended interrupt when done. Do check here
0184      * after bytes_left was initialized to support SMBUS_QUICK (new msg has
0185      * 0 length then)
0186      */
0187     if (riic->bytes_left == 0)
0188         riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
0189
0190     /*
0191      * This acks the TIE interrupt. We get another TIE immediately if our
0192      * value could be moved to the shadow shift register right away. So
0193      * this must be after updates to ICIER (where we want to disable TIE)!
0194      */
0195     writeb(val, riic->base + RIIC_ICDRT);
0196
0197     return IRQ_HANDLED;
0198 }
0199
0200 static irqreturn_t riic_tend_isr(int irq, void *data)
0201 {
0202     struct riic_dev *riic = data;
0203
0204     if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
0205         /* We got a NACKIE */
0206         readb(riic->base + RIIC_ICDRR); /* dummy read */
0207         riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
0208         riic->err = -ENXIO;
0209     } else if (riic->bytes_left) {
0210         return IRQ_NONE;
0211     }
0212
0213     if (riic->is_last || riic->err) {
0214         riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
0215         writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
0216     } else {
0217         /* Transfer is complete, but do not send STOP */
0218         riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
0219         complete(&riic->msg_done);
0220     }
0221
0222     return IRQ_HANDLED;
0223 }
0224
0225 static irqreturn_t riic_rdrf_isr(int irq, void *data)
0226 {
0227     struct riic_dev *riic = data;
0228
0229     if (!riic->bytes_left)
0230         return IRQ_NONE;
0231
0232     if (riic->bytes_left == RIIC_INIT_MSG) {
0233         riic->bytes_left = riic->msg->len;
0234         readb(riic->base + RIIC_ICDRR); /* dummy read */
0235         return IRQ_HANDLED;
0236     }
0237
0238     if (riic->bytes_left == 1) {
0239         /* STOP must come before we set ACKBT! */
0240         if (riic->is_last) {
0241             riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
0242             writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
0243         }
0244
0245         riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
0246
0247     } else {
0248         riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
0249     }
0250
0251     /* Reading acks the RIE interrupt */
0252     *riic->buf = readb(riic->base + RIIC_ICDRR);
0253     riic->buf++;
0254     riic->bytes_left--;
0255
0256     return IRQ_HANDLED;
0257 }
0258
0259 static irqreturn_t riic_stop_isr(int irq, void *data)
0260 {
0261     struct riic_dev *riic = data;
0262
0263     /* read back registers to confirm writes have fully propagated */
0264     writeb(0, riic->base + RIIC_ICSR2);
0265     readb(riic->base + RIIC_ICSR2);
0266     writeb(0, riic->base + RIIC_ICIER);
0267     readb(riic->base + RIIC_ICIER);
0268
0269     complete(&riic->msg_done);
0270
0271     return IRQ_HANDLED;
0272 }
0273
0274 static u32 riic_func(struct i2c_adapter *adap)
0275 {
0276     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0277 }
0278
0279 static const struct i2c_algorithm riic_algo = {
0280     .master_xfer    = riic_xfer,
0281     .functionality  = riic_func,
0282 };
0283
0284 static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
0285 {
0286     int ret = 0;
0287     unsigned long rate;
0288     int total_ticks, cks, brl, brh;
0289
0290     pm_runtime_get_sync(riic->adapter.dev.parent);
0291
0292     if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
0293         dev_err(&riic->adapter.dev,
0294             "unsupported bus speed (%dHz). %d max\n",
0295             t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ);
0296         ret = -EINVAL;
0297         goto out;
0298     }
0299
0300     rate = clk_get_rate(riic->clk);
0301
0302     /*
0303      * Assume the default register settings:
0304      *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
0305      *  FER.NFE = 1 (noise circuit enabled)
0306      *  MR3.NF = 0 (1 cycle of noise filtered out)
0307      *
0308      * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
0309      * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
0310      */
0311
0312     /*
0313      * Determine reference clock rate. We must be able to get the desired
0314      * frequency with only 62 clock ticks max (31 high, 31 low).
0315      * Aim for a duty of 60% LOW, 40% HIGH.
0316      */
0317     total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
0318
0319     for (cks = 0; cks < 7; cks++) {
0320         /*
0321          * 60% low time must be less than BRL + 2 + 1
0322          * BRL max register value is 0x1F.
0323          */
0324         brl = ((total_ticks * 6) / 10);
0325         if (brl <= (0x1F + 3))
0326             break;
0327
0328         total_ticks /= 2;
0329         rate /= 2;
0330     }
0331
0332     if (brl > (0x1F + 3)) {
0333         dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
0334             (unsigned long)t->bus_freq_hz);
0335         ret = -EINVAL;
0336         goto out;
0337     }
0338
0339     brh = total_ticks - brl;
0340
0341     /* Remove automatic clock ticks for sync circuit and NF */
0342     if (cks == 0) {
0343         brl -= 4;
0344         brh -= 4;
0345     } else {
0346         brl -= 3;
0347         brh -= 3;
0348     }
0349
0350     /*
0351      * Remove clock ticks for rise and fall times. Convert ns to clock
0352      * ticks.
0353      */
0354     brl -= t->scl_fall_ns / (1000000000 / rate);
0355     brh -= t->scl_rise_ns / (1000000000 / rate);
0356
0357     /* Adjust for min register values for when SCLE=1 and NFE=1 */
0358     if (brl < 1)
0359         brl = 1;
0360     if (brh < 1)
0361         brh = 1;
0362
0363     pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
0364          rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
0365          t->scl_fall_ns / (1000000000 / rate),
0366          t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
0367
0368     /* Changing the order of accessing IICRST and ICE may break things! */
0369     writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
0370     riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
0371
0372     writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
0373     writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
0374     writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
0375
0376     writeb(0, riic->base + RIIC_ICSER);
0377     writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
0378
0379     riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
0380
0381 out:
0382     pm_runtime_put(riic->adapter.dev.parent);
0383     return ret;
0384 }
0385
0386 static struct riic_irq_desc riic_irqs[] = {
0387     { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
0388     { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
0389     { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
0390     { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
0391     { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
0392 };
0393
0394 static void riic_reset_control_assert(void *data)
0395 {
0396     reset_control_assert(data);
0397 }
0398
0399 static int riic_i2c_probe(struct platform_device *pdev)
0400 {
0401     struct riic_dev *riic;
0402     struct i2c_adapter *adap;
0403     struct resource *res;
0404     struct i2c_timings i2c_t;
0405     struct reset_control *rstc;
0406     int i, ret;
0407
0408     riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
0409     if (!riic)
0410         return -ENOMEM;
0411
0412     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0413     riic->base = devm_ioremap_resource(&pdev->dev, res);
0414     if (IS_ERR(riic->base))
0415         return PTR_ERR(riic->base);
0416
0417     riic->clk = devm_clk_get(&pdev->dev, NULL);
0418     if (IS_ERR(riic->clk)) {
0419         dev_err(&pdev->dev, "missing controller clock");
0420         return PTR_ERR(riic->clk);
0421     }
0422
0423     rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
0424     if (IS_ERR(rstc))
0425         return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
0426                      "Error: missing reset ctrl\n");
0427
0428     ret = reset_control_deassert(rstc);
0429     if (ret)
0430         return ret;
0431
0432     ret = devm_add_action_or_reset(&pdev->dev, riic_reset_control_assert, rstc);
0433     if (ret)
0434         return ret;
0435
0436     for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
0437         ret = platform_get_irq(pdev, riic_irqs[i].res_num);
0438         if (ret < 0)
0439             return ret;
0440
0441         ret = devm_request_irq(&pdev->dev, ret, riic_irqs[i].isr,
0442                        0, riic_irqs[i].name, riic);
0443         if (ret) {
0444             dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
0445             return ret;
0446         }
0447     }
0448
0449     adap = &riic->adapter;
0450     i2c_set_adapdata(adap, riic);
0451     strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
0452     adap->owner = THIS_MODULE;
0453     adap->algo = &riic_algo;
0454     adap->dev.parent = &pdev->dev;
0455     adap->dev.of_node = pdev->dev.of_node;
0456
0457     init_completion(&riic->msg_done);
0458
0459     i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
0460
0461     pm_runtime_enable(&pdev->dev);
0462
0463     ret = riic_init_hw(riic, &i2c_t);
0464     if (ret)
0465         goto out;
0466
0467     ret = i2c_add_adapter(adap);
0468     if (ret)
0469         goto out;
0470
0471     platform_set_drvdata(pdev, riic);
0472
0473     dev_info(&pdev->dev, "registered with %dHz bus speed\n",
0474          i2c_t.bus_freq_hz);
0475     return 0;
0476
0477 out:
0478     pm_runtime_disable(&pdev->dev);
0479     return ret;
0480 }
0481
0482 static int riic_i2c_remove(struct platform_device *pdev)
0483 {
0484     struct riic_dev *riic = platform_get_drvdata(pdev);
0485
0486     pm_runtime_get_sync(&pdev->dev);
0487     writeb(0, riic->base + RIIC_ICIER);
0488     pm_runtime_put(&pdev->dev);
0489     i2c_del_adapter(&riic->adapter);
0490     pm_runtime_disable(&pdev->dev);
0491
0492     return 0;
0493 }
0494
0495 static const struct of_device_id riic_i2c_dt_ids[] = {
0496     { .compatible = "renesas,riic-rz", },
0497     { /* Sentinel */ },
0498 };
0499
0500 static struct platform_driver riic_i2c_driver = {
0501     .probe      = riic_i2c_probe,
0502     .remove     = riic_i2c_remove,
0503     .driver     = {
0504         .name   = "i2c-riic",
0505         .of_match_table = riic_i2c_dt_ids,
0506     },
0507 };
0508
0509 module_platform_driver(riic_i2c_driver);
0510
0511 MODULE_DESCRIPTION("Renesas RIIC adapter");
0512 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
0513 MODULE_LICENSE("GPL v2");
0514 MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);