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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for the Renesas R-Car I2C unit
0004  *
0005  * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
0006  * Copyright (C) 2011-2019 Renesas Electronics Corporation
0007  *
0008  * Copyright (C) 2012-14 Renesas Solutions Corp.
0009  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
0010  *
0011  * This file is based on the drivers/i2c/busses/i2c-sh7760.c
0012  * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
0013  */
0014 #include <linux/bitops.h>
0015 #include <linux/clk.h>
0016 #include <linux/delay.h>
0017 #include <linux/dmaengine.h>
0018 #include <linux/dma-mapping.h>
0019 #include <linux/err.h>
0020 #include <linux/interrupt.h>
0021 #include <linux/io.h>
0022 #include <linux/iopoll.h>
0023 #include <linux/i2c.h>
0024 #include <linux/i2c-smbus.h>
0025 #include <linux/kernel.h>
0026 #include <linux/module.h>
0027 #include <linux/of_device.h>
0028 #include <linux/platform_device.h>
0029 #include <linux/pm_runtime.h>
0030 #include <linux/reset.h>
0031 #include <linux/slab.h>
0032 
0033 /* register offsets */
0034 #define ICSCR   0x00    /* slave ctrl */
0035 #define ICMCR   0x04    /* master ctrl */
0036 #define ICSSR   0x08    /* slave status */
0037 #define ICMSR   0x0C    /* master status */
0038 #define ICSIER  0x10    /* slave irq enable */
0039 #define ICMIER  0x14    /* master irq enable */
0040 #define ICCCR   0x18    /* clock dividers */
0041 #define ICSAR   0x1C    /* slave address */
0042 #define ICMAR   0x20    /* master address */
0043 #define ICRXTX  0x24    /* data port */
0044 #define ICFBSCR 0x38    /* first bit setup cycle (Gen3) */
0045 #define ICDMAER 0x3c    /* DMA enable (Gen3) */
0046 
0047 /* ICSCR */
0048 #define SDBS    BIT(3)  /* slave data buffer select */
0049 #define SIE BIT(2)  /* slave interface enable */
0050 #define GCAE    BIT(1)  /* general call address enable */
0051 #define FNA BIT(0)  /* forced non acknowledgment */
0052 
0053 /* ICMCR */
0054 #define MDBS    BIT(7)  /* non-fifo mode switch */
0055 #define FSCL    BIT(6)  /* override SCL pin */
0056 #define FSDA    BIT(5)  /* override SDA pin */
0057 #define OBPC    BIT(4)  /* override pins */
0058 #define MIE BIT(3)  /* master if enable */
0059 #define TSBE    BIT(2)
0060 #define FSB BIT(1)  /* force stop bit */
0061 #define ESG BIT(0)  /* enable start bit gen */
0062 
0063 /* ICSSR (also for ICSIER) */
0064 #define GCAR    BIT(6)  /* general call received */
0065 #define STM BIT(5)  /* slave transmit mode */
0066 #define SSR BIT(4)  /* stop received */
0067 #define SDE BIT(3)  /* slave data empty */
0068 #define SDT BIT(2)  /* slave data transmitted */
0069 #define SDR BIT(1)  /* slave data received */
0070 #define SAR BIT(0)  /* slave addr received */
0071 
0072 /* ICMSR (also for ICMIE) */
0073 #define MNR BIT(6)  /* nack received */
0074 #define MAL BIT(5)  /* arbitration lost */
0075 #define MST BIT(4)  /* sent a stop */
0076 #define MDE BIT(3)
0077 #define MDT BIT(2)
0078 #define MDR BIT(1)
0079 #define MAT BIT(0)  /* slave addr xfer done */
0080 
0081 /* ICDMAER */
0082 #define RSDMAE  BIT(3)  /* DMA Slave Received Enable */
0083 #define TSDMAE  BIT(2)  /* DMA Slave Transmitted Enable */
0084 #define RMDMAE  BIT(1)  /* DMA Master Received Enable */
0085 #define TMDMAE  BIT(0)  /* DMA Master Transmitted Enable */
0086 
0087 /* ICFBSCR */
0088 #define TCYC17  0x0f        /* 17*Tcyc delay 1st bit between SDA and SCL */
0089 
0090 #define RCAR_MIN_DMA_LEN    8
0091 
0092 #define RCAR_BUS_PHASE_START    (MDBS | MIE | ESG)
0093 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
0094 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
0095 
0096 #define RCAR_IRQ_SEND   (MNR | MAL | MST | MAT | MDE)
0097 #define RCAR_IRQ_RECV   (MNR | MAL | MST | MAT | MDR)
0098 #define RCAR_IRQ_STOP   (MST)
0099 
0100 #define ID_LAST_MSG     BIT(0)
0101 #define ID_REP_AFTER_RD     BIT(1)
0102 #define ID_DONE         BIT(2)
0103 #define ID_ARBLOST      BIT(3)
0104 #define ID_NACK         BIT(4)
0105 #define ID_EPROTO       BIT(5)
0106 /* persistent flags */
0107 #define ID_P_NOT_ATOMIC     BIT(28)
0108 #define ID_P_HOST_NOTIFY    BIT(29)
0109 #define ID_P_NO_RXDMA       BIT(30) /* HW forbids RXDMA sometimes */
0110 #define ID_P_PM_BLOCKED     BIT(31)
0111 #define ID_P_MASK       GENMASK(31, 28)
0112 
0113 enum rcar_i2c_type {
0114     I2C_RCAR_GEN1,
0115     I2C_RCAR_GEN2,
0116     I2C_RCAR_GEN3,
0117 };
0118 
0119 struct rcar_i2c_priv {
0120     u32 flags;
0121     void __iomem *io;
0122     struct i2c_adapter adap;
0123     struct i2c_msg *msg;
0124     int msgs_left;
0125     struct clk *clk;
0126 
0127     wait_queue_head_t wait;
0128 
0129     int pos;
0130     u32 icccr;
0131     u8 recovery_icmcr;  /* protected by adapter lock */
0132     enum rcar_i2c_type devtype;
0133     struct i2c_client *slave;
0134 
0135     struct resource *res;
0136     struct dma_chan *dma_tx;
0137     struct dma_chan *dma_rx;
0138     struct scatterlist sg;
0139     enum dma_data_direction dma_direction;
0140 
0141     struct reset_control *rstc;
0142     int irq;
0143 
0144     struct i2c_client *host_notify_client;
0145 };
0146 
0147 #define rcar_i2c_priv_to_dev(p)     ((p)->adap.dev.parent)
0148 #define rcar_i2c_is_recv(p)     ((p)->msg->flags & I2C_M_RD)
0149 
0150 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
0151 {
0152     writel(val, priv->io + reg);
0153 }
0154 
0155 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
0156 {
0157     return readl(priv->io + reg);
0158 }
0159 
0160 static void rcar_i2c_clear_irq(struct rcar_i2c_priv *priv, u32 val)
0161 {
0162     writel(~val & 0x7f, priv->io + ICMSR);
0163 }
0164 
0165 static int rcar_i2c_get_scl(struct i2c_adapter *adap)
0166 {
0167     struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
0168 
0169     return !!(rcar_i2c_read(priv, ICMCR) & FSCL);
0170 
0171 };
0172 
0173 static void rcar_i2c_set_scl(struct i2c_adapter *adap, int val)
0174 {
0175     struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
0176 
0177     if (val)
0178         priv->recovery_icmcr |= FSCL;
0179     else
0180         priv->recovery_icmcr &= ~FSCL;
0181 
0182     rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
0183 };
0184 
0185 static void rcar_i2c_set_sda(struct i2c_adapter *adap, int val)
0186 {
0187     struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
0188 
0189     if (val)
0190         priv->recovery_icmcr |= FSDA;
0191     else
0192         priv->recovery_icmcr &= ~FSDA;
0193 
0194     rcar_i2c_write(priv, ICMCR, priv->recovery_icmcr);
0195 };
0196 
0197 static int rcar_i2c_get_bus_free(struct i2c_adapter *adap)
0198 {
0199     struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
0200 
0201     return !(rcar_i2c_read(priv, ICMCR) & FSDA);
0202 
0203 };
0204 
0205 static struct i2c_bus_recovery_info rcar_i2c_bri = {
0206     .get_scl = rcar_i2c_get_scl,
0207     .set_scl = rcar_i2c_set_scl,
0208     .set_sda = rcar_i2c_set_sda,
0209     .get_bus_free = rcar_i2c_get_bus_free,
0210     .recover_bus = i2c_generic_scl_recovery,
0211 };
0212 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
0213 {
0214     /* reset master mode */
0215     rcar_i2c_write(priv, ICMIER, 0);
0216     rcar_i2c_write(priv, ICMCR, MDBS);
0217     rcar_i2c_write(priv, ICMSR, 0);
0218     /* start clock */
0219     rcar_i2c_write(priv, ICCCR, priv->icccr);
0220 
0221     if (priv->devtype == I2C_RCAR_GEN3)
0222         rcar_i2c_write(priv, ICFBSCR, TCYC17);
0223 
0224 }
0225 
0226 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
0227 {
0228     int ret;
0229     u32 val;
0230 
0231     ret = readl_poll_timeout(priv->io + ICMCR, val, !(val & FSDA), 10,
0232                  priv->adap.timeout);
0233     if (ret) {
0234         /* Waiting did not help, try to recover */
0235         priv->recovery_icmcr = MDBS | OBPC | FSDA | FSCL;
0236         ret = i2c_recover_bus(&priv->adap);
0237     }
0238 
0239     return ret;
0240 }
0241 
0242 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv)
0243 {
0244     u32 scgd, cdf, round, ick, sum, scl, cdf_width;
0245     unsigned long rate;
0246     struct device *dev = rcar_i2c_priv_to_dev(priv);
0247     struct i2c_timings t = {
0248         .bus_freq_hz        = I2C_MAX_STANDARD_MODE_FREQ,
0249         .scl_fall_ns        = 35,
0250         .scl_rise_ns        = 200,
0251         .scl_int_delay_ns   = 50,
0252     };
0253 
0254     /* Fall back to previously used values if not supplied */
0255     i2c_parse_fw_timings(dev, &t, false);
0256 
0257     switch (priv->devtype) {
0258     case I2C_RCAR_GEN1:
0259         cdf_width = 2;
0260         break;
0261     case I2C_RCAR_GEN2:
0262     case I2C_RCAR_GEN3:
0263         cdf_width = 3;
0264         break;
0265     default:
0266         dev_err(dev, "device type error\n");
0267         return -EIO;
0268     }
0269 
0270     /*
0271      * calculate SCL clock
0272      * see
0273      *  ICCCR
0274      *
0275      * ick  = clkp / (1 + CDF)
0276      * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
0277      *
0278      * ick  : I2C internal clock < 20 MHz
0279      * ticf : I2C SCL falling time
0280      * tr   : I2C SCL rising  time
0281      * intd : LSI internal delay
0282      * clkp : peripheral_clk
0283      * F[]  : integer up-valuation
0284      */
0285     rate = clk_get_rate(priv->clk);
0286     cdf = rate / 20000000;
0287     if (cdf >= 1U << cdf_width) {
0288         dev_err(dev, "Input clock %lu too high\n", rate);
0289         return -EIO;
0290     }
0291     ick = rate / (cdf + 1);
0292 
0293     /*
0294      * it is impossible to calculate large scale
0295      * number on u32. separate it
0296      *
0297      * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
0298      *  = F[sum * ick / 1000000000]
0299      *  = F[(ick / 1000000) * sum / 1000]
0300      */
0301     sum = t.scl_fall_ns + t.scl_rise_ns + t.scl_int_delay_ns;
0302     round = (ick + 500000) / 1000000 * sum;
0303     round = (round + 500) / 1000;
0304 
0305     /*
0306      * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
0307      *
0308      * Calculation result (= SCL) should be less than
0309      * bus_speed for hardware safety
0310      *
0311      * We could use something along the lines of
0312      *  div = ick / (bus_speed + 1) + 1;
0313      *  scgd = (div - 20 - round + 7) / 8;
0314      *  scl = ick / (20 + (scgd * 8) + round);
0315      * (not fully verified) but that would get pretty involved
0316      */
0317     for (scgd = 0; scgd < 0x40; scgd++) {
0318         scl = ick / (20 + (scgd * 8) + round);
0319         if (scl <= t.bus_freq_hz)
0320             goto scgd_find;
0321     }
0322     dev_err(dev, "it is impossible to calculate best SCL\n");
0323     return -EIO;
0324 
0325 scgd_find:
0326     dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
0327         scl, t.bus_freq_hz, rate, round, cdf, scgd);
0328 
0329     /* keep icccr value */
0330     priv->icccr = scgd << cdf_width | cdf;
0331 
0332     return 0;
0333 }
0334 
0335 /*
0336  * We don't have a test case but the HW engineers say that the write order of
0337  * ICMSR and ICMCR depends on whether we issue START or REP_START. So, ICMSR
0338  * handling is outside of this function. First messages clear ICMSR before this
0339  * function, interrupt handlers clear the relevant bits after this function.
0340  */
0341 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
0342 {
0343     int read = !!rcar_i2c_is_recv(priv);
0344     bool rep_start = !(priv->flags & ID_REP_AFTER_RD);
0345 
0346     priv->pos = 0;
0347     priv->flags &= ID_P_MASK;
0348 
0349     if (priv->msgs_left == 1)
0350         priv->flags |= ID_LAST_MSG;
0351 
0352     rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));
0353     if (priv->flags & ID_P_NOT_ATOMIC)
0354         rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
0355 
0356     if (rep_start)
0357         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
0358 }
0359 
0360 static void rcar_i2c_first_msg(struct rcar_i2c_priv *priv,
0361                    struct i2c_msg *msgs, int num)
0362 {
0363     priv->msg = msgs;
0364     priv->msgs_left = num;
0365     rcar_i2c_write(priv, ICMSR, 0); /* must be before preparing msg */
0366     rcar_i2c_prepare_msg(priv);
0367 }
0368 
0369 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
0370 {
0371     priv->msg++;
0372     priv->msgs_left--;
0373     rcar_i2c_prepare_msg(priv);
0374     /* ICMSR handling must come afterwards in the irq handler */
0375 }
0376 
0377 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv, bool terminate)
0378 {
0379     struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
0380         ? priv->dma_rx : priv->dma_tx;
0381 
0382     /* only allowed from thread context! */
0383     if (terminate)
0384         dmaengine_terminate_sync(chan);
0385 
0386     dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
0387              sg_dma_len(&priv->sg), priv->dma_direction);
0388 
0389     /* Gen3 can only do one RXDMA per transfer and we just completed it */
0390     if (priv->devtype == I2C_RCAR_GEN3 &&
0391         priv->dma_direction == DMA_FROM_DEVICE)
0392         priv->flags |= ID_P_NO_RXDMA;
0393 
0394     priv->dma_direction = DMA_NONE;
0395 
0396     /* Disable DMA Master Received/Transmitted, must be last! */
0397     rcar_i2c_write(priv, ICDMAER, 0);
0398 }
0399 
0400 static void rcar_i2c_dma_callback(void *data)
0401 {
0402     struct rcar_i2c_priv *priv = data;
0403 
0404     priv->pos += sg_dma_len(&priv->sg);
0405 
0406     rcar_i2c_cleanup_dma(priv, false);
0407 }
0408 
0409 static bool rcar_i2c_dma(struct rcar_i2c_priv *priv)
0410 {
0411     struct device *dev = rcar_i2c_priv_to_dev(priv);
0412     struct i2c_msg *msg = priv->msg;
0413     bool read = msg->flags & I2C_M_RD;
0414     enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
0415     struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
0416     struct dma_async_tx_descriptor *txdesc;
0417     dma_addr_t dma_addr;
0418     dma_cookie_t cookie;
0419     unsigned char *buf;
0420     int len;
0421 
0422     /* Do various checks to see if DMA is feasible at all */
0423     if (!(priv->flags & ID_P_NOT_ATOMIC) || IS_ERR(chan) || msg->len < RCAR_MIN_DMA_LEN ||
0424         !(msg->flags & I2C_M_DMA_SAFE) || (read && priv->flags & ID_P_NO_RXDMA))
0425         return false;
0426 
0427     if (read) {
0428         /*
0429          * The last two bytes needs to be fetched using PIO in
0430          * order for the STOP phase to work.
0431          */
0432         buf = priv->msg->buf;
0433         len = priv->msg->len - 2;
0434     } else {
0435         /*
0436          * First byte in message was sent using PIO.
0437          */
0438         buf = priv->msg->buf + 1;
0439         len = priv->msg->len - 1;
0440     }
0441 
0442     dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
0443     if (dma_mapping_error(chan->device->dev, dma_addr)) {
0444         dev_dbg(dev, "dma map failed, using PIO\n");
0445         return false;
0446     }
0447 
0448     sg_dma_len(&priv->sg) = len;
0449     sg_dma_address(&priv->sg) = dma_addr;
0450 
0451     priv->dma_direction = dir;
0452 
0453     txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
0454                      read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
0455                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0456     if (!txdesc) {
0457         dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
0458         rcar_i2c_cleanup_dma(priv, false);
0459         return false;
0460     }
0461 
0462     txdesc->callback = rcar_i2c_dma_callback;
0463     txdesc->callback_param = priv;
0464 
0465     cookie = dmaengine_submit(txdesc);
0466     if (dma_submit_error(cookie)) {
0467         dev_dbg(dev, "submitting dma failed, using PIO\n");
0468         rcar_i2c_cleanup_dma(priv, false);
0469         return false;
0470     }
0471 
0472     /* Enable DMA Master Received/Transmitted */
0473     if (read)
0474         rcar_i2c_write(priv, ICDMAER, RMDMAE);
0475     else
0476         rcar_i2c_write(priv, ICDMAER, TMDMAE);
0477 
0478     dma_async_issue_pending(chan);
0479     return true;
0480 }
0481 
0482 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
0483 {
0484     struct i2c_msg *msg = priv->msg;
0485     u32 irqs_to_clear = MDE;
0486 
0487     /* FIXME: sometimes, unknown interrupt happened. Do nothing */
0488     if (!(msr & MDE))
0489         return;
0490 
0491     if (msr & MAT)
0492         irqs_to_clear |= MAT;
0493 
0494     /* Check if DMA can be enabled and take over */
0495     if (priv->pos == 1 && rcar_i2c_dma(priv))
0496         return;
0497 
0498     if (priv->pos < msg->len) {
0499         /*
0500          * Prepare next data to ICRXTX register.
0501          * This data will go to _SHIFT_ register.
0502          *
0503          *    *
0504          * [ICRXTX] -> [SHIFT] -> [I2C bus]
0505          */
0506         rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
0507         priv->pos++;
0508     } else {
0509         /*
0510          * The last data was pushed to ICRXTX on _PREV_ empty irq.
0511          * It is on _SHIFT_ register, and will sent to I2C bus.
0512          *
0513          *        *
0514          * [ICRXTX] -> [SHIFT] -> [I2C bus]
0515          */
0516 
0517         if (priv->flags & ID_LAST_MSG)
0518             /*
0519              * If current msg is the _LAST_ msg,
0520              * prepare stop condition here.
0521              * ID_DONE will be set on STOP irq.
0522              */
0523             rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
0524         else
0525             rcar_i2c_next_msg(priv);
0526     }
0527 
0528     rcar_i2c_clear_irq(priv, irqs_to_clear);
0529 }
0530 
0531 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
0532 {
0533     struct i2c_msg *msg = priv->msg;
0534     bool recv_len_init = priv->pos == 0 && msg->flags & I2C_M_RECV_LEN;
0535     u32 irqs_to_clear = MDR;
0536 
0537     /* FIXME: sometimes, unknown interrupt happened. Do nothing */
0538     if (!(msr & MDR))
0539         return;
0540 
0541     if (msr & MAT) {
0542         irqs_to_clear |= MAT;
0543         /*
0544          * Address transfer phase finished, but no data at this point.
0545          * Try to use DMA to receive data.
0546          */
0547         rcar_i2c_dma(priv);
0548     } else if (priv->pos < msg->len) {
0549         /* get received data */
0550         u8 data = rcar_i2c_read(priv, ICRXTX);
0551 
0552         msg->buf[priv->pos] = data;
0553         if (recv_len_init) {
0554             if (data == 0 || data > I2C_SMBUS_BLOCK_MAX) {
0555                 priv->flags |= ID_DONE | ID_EPROTO;
0556                 return;
0557             }
0558             msg->len += msg->buf[0];
0559             /* Enough data for DMA? */
0560             if (rcar_i2c_dma(priv))
0561                 return;
0562             /* new length after RECV_LEN now properly initialized */
0563             recv_len_init = false;
0564         }
0565         priv->pos++;
0566     }
0567 
0568     /*
0569      * If next received data is the _LAST_ and we are not waiting for a new
0570      * length because of RECV_LEN, then go to a new phase.
0571      */
0572     if (priv->pos + 1 == msg->len && !recv_len_init) {
0573         if (priv->flags & ID_LAST_MSG) {
0574             rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
0575         } else {
0576             rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
0577             priv->flags |= ID_REP_AFTER_RD;
0578         }
0579     }
0580 
0581     if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
0582         rcar_i2c_next_msg(priv);
0583 
0584     rcar_i2c_clear_irq(priv, irqs_to_clear);
0585 }
0586 
0587 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
0588 {
0589     u32 ssr_raw, ssr_filtered;
0590     u8 value;
0591 
0592     ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
0593     ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
0594 
0595     if (!ssr_filtered)
0596         return false;
0597 
0598     /* address detected */
0599     if (ssr_filtered & SAR) {
0600         /* read or write request */
0601         if (ssr_raw & STM) {
0602             i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
0603             rcar_i2c_write(priv, ICRXTX, value);
0604             rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
0605         } else {
0606             i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
0607             rcar_i2c_read(priv, ICRXTX);    /* dummy read */
0608             rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
0609         }
0610 
0611         /* Clear SSR, too, because of old STOPs to other clients than us */
0612         rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
0613     }
0614 
0615     /* master sent stop */
0616     if (ssr_filtered & SSR) {
0617         i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
0618         rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
0619         rcar_i2c_write(priv, ICSIER, SAR);
0620         rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
0621     }
0622 
0623     /* master wants to write to us */
0624     if (ssr_filtered & SDR) {
0625         int ret;
0626 
0627         value = rcar_i2c_read(priv, ICRXTX);
0628         ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
0629         /* Send NACK in case of error */
0630         rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
0631         rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
0632     }
0633 
0634     /* master wants to read from us */
0635     if (ssr_filtered & SDE) {
0636         i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
0637         rcar_i2c_write(priv, ICRXTX, value);
0638         rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
0639     }
0640 
0641     return true;
0642 }
0643 
0644 /*
0645  * This driver has a lock-free design because there are IP cores (at least
0646  * R-Car Gen2) which have an inherent race condition in their hardware design.
0647  * There, we need to switch to RCAR_BUS_PHASE_DATA as soon as possible after
0648  * the interrupt was generated, otherwise an unwanted repeated message gets
0649  * generated. It turned out that taking a spinlock at the beginning of the ISR
0650  * was already causing repeated messages. Thus, this driver was converted to
0651  * the now lockless behaviour. Please keep this in mind when hacking the driver.
0652  * R-Car Gen3 seems to have this fixed but earlier versions than R-Car Gen2 are
0653  * likely affected. Therefore, we have different interrupt handler entries.
0654  */
0655 static irqreturn_t rcar_i2c_irq(int irq, struct rcar_i2c_priv *priv, u32 msr)
0656 {
0657     if (!msr) {
0658         if (rcar_i2c_slave_irq(priv))
0659             return IRQ_HANDLED;
0660 
0661         return IRQ_NONE;
0662     }
0663 
0664     /* Arbitration lost */
0665     if (msr & MAL) {
0666         priv->flags |= ID_DONE | ID_ARBLOST;
0667         goto out;
0668     }
0669 
0670     /* Nack */
0671     if (msr & MNR) {
0672         /* HW automatically sends STOP after received NACK */
0673         if (priv->flags & ID_P_NOT_ATOMIC)
0674             rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
0675         priv->flags |= ID_NACK;
0676         goto out;
0677     }
0678 
0679     /* Stop */
0680     if (msr & MST) {
0681         priv->msgs_left--; /* The last message also made it */
0682         priv->flags |= ID_DONE;
0683         goto out;
0684     }
0685 
0686     if (rcar_i2c_is_recv(priv))
0687         rcar_i2c_irq_recv(priv, msr);
0688     else
0689         rcar_i2c_irq_send(priv, msr);
0690 
0691 out:
0692     if (priv->flags & ID_DONE) {
0693         rcar_i2c_write(priv, ICMIER, 0);
0694         rcar_i2c_write(priv, ICMSR, 0);
0695         if (priv->flags & ID_P_NOT_ATOMIC)
0696             wake_up(&priv->wait);
0697     }
0698 
0699     return IRQ_HANDLED;
0700 }
0701 
0702 static irqreturn_t rcar_i2c_gen2_irq(int irq, void *ptr)
0703 {
0704     struct rcar_i2c_priv *priv = ptr;
0705     u32 msr;
0706 
0707     /* Clear START or STOP immediately, except for REPSTART after read */
0708     if (likely(!(priv->flags & ID_REP_AFTER_RD)))
0709         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
0710 
0711     /* Only handle interrupts that are currently enabled */
0712     msr = rcar_i2c_read(priv, ICMSR);
0713     if (priv->flags & ID_P_NOT_ATOMIC)
0714         msr &= rcar_i2c_read(priv, ICMIER);
0715 
0716     return rcar_i2c_irq(irq, priv, msr);
0717 }
0718 
0719 static irqreturn_t rcar_i2c_gen3_irq(int irq, void *ptr)
0720 {
0721     struct rcar_i2c_priv *priv = ptr;
0722     u32 msr;
0723 
0724     /* Only handle interrupts that are currently enabled */
0725     msr = rcar_i2c_read(priv, ICMSR);
0726     if (priv->flags & ID_P_NOT_ATOMIC)
0727         msr &= rcar_i2c_read(priv, ICMIER);
0728 
0729     /*
0730      * Clear START or STOP immediately, except for REPSTART after read or
0731      * if a spurious interrupt was detected.
0732      */
0733     if (likely(!(priv->flags & ID_REP_AFTER_RD) && msr))
0734         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
0735 
0736     return rcar_i2c_irq(irq, priv, msr);
0737 }
0738 
0739 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
0740                     enum dma_transfer_direction dir,
0741                     dma_addr_t port_addr)
0742 {
0743     struct dma_chan *chan;
0744     struct dma_slave_config cfg;
0745     char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
0746     int ret;
0747 
0748     chan = dma_request_chan(dev, chan_name);
0749     if (IS_ERR(chan)) {
0750         dev_dbg(dev, "request_channel failed for %s (%ld)\n",
0751             chan_name, PTR_ERR(chan));
0752         return chan;
0753     }
0754 
0755     memset(&cfg, 0, sizeof(cfg));
0756     cfg.direction = dir;
0757     if (dir == DMA_MEM_TO_DEV) {
0758         cfg.dst_addr = port_addr;
0759         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
0760     } else {
0761         cfg.src_addr = port_addr;
0762         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
0763     }
0764 
0765     ret = dmaengine_slave_config(chan, &cfg);
0766     if (ret) {
0767         dev_dbg(dev, "slave_config failed for %s (%d)\n",
0768             chan_name, ret);
0769         dma_release_channel(chan);
0770         return ERR_PTR(ret);
0771     }
0772 
0773     dev_dbg(dev, "got DMA channel for %s\n", chan_name);
0774     return chan;
0775 }
0776 
0777 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
0778                  struct i2c_msg *msg)
0779 {
0780     struct device *dev = rcar_i2c_priv_to_dev(priv);
0781     bool read;
0782     struct dma_chan *chan;
0783     enum dma_transfer_direction dir;
0784 
0785     read = msg->flags & I2C_M_RD;
0786 
0787     chan = read ? priv->dma_rx : priv->dma_tx;
0788     if (PTR_ERR(chan) != -EPROBE_DEFER)
0789         return;
0790 
0791     dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
0792     chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
0793 
0794     if (read)
0795         priv->dma_rx = chan;
0796     else
0797         priv->dma_tx = chan;
0798 }
0799 
0800 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
0801 {
0802     if (!IS_ERR(priv->dma_tx)) {
0803         dma_release_channel(priv->dma_tx);
0804         priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
0805     }
0806 
0807     if (!IS_ERR(priv->dma_rx)) {
0808         dma_release_channel(priv->dma_rx);
0809         priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
0810     }
0811 }
0812 
0813 /* I2C is a special case, we need to poll the status of a reset */
0814 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
0815 {
0816     int ret;
0817 
0818     ret = reset_control_reset(priv->rstc);
0819     if (ret)
0820         return ret;
0821 
0822     return read_poll_timeout_atomic(reset_control_status, ret, ret == 0, 1,
0823                     100, false, priv->rstc);
0824 }
0825 
0826 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
0827                 struct i2c_msg *msgs,
0828                 int num)
0829 {
0830     struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
0831     struct device *dev = rcar_i2c_priv_to_dev(priv);
0832     int i, ret;
0833     long time_left;
0834 
0835     priv->flags |= ID_P_NOT_ATOMIC;
0836 
0837     pm_runtime_get_sync(dev);
0838 
0839     /* Check bus state before init otherwise bus busy info will be lost */
0840     ret = rcar_i2c_bus_barrier(priv);
0841     if (ret < 0)
0842         goto out;
0843 
0844     /* Gen3 needs a reset before allowing RXDMA once */
0845     if (priv->devtype == I2C_RCAR_GEN3) {
0846         priv->flags |= ID_P_NO_RXDMA;
0847         if (!IS_ERR(priv->rstc)) {
0848             ret = rcar_i2c_do_reset(priv);
0849             if (ret == 0)
0850                 priv->flags &= ~ID_P_NO_RXDMA;
0851         }
0852     }
0853 
0854     rcar_i2c_init(priv);
0855 
0856     for (i = 0; i < num; i++)
0857         rcar_i2c_request_dma(priv, msgs + i);
0858 
0859     rcar_i2c_first_msg(priv, msgs, num);
0860 
0861     time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
0862                      num * adap->timeout);
0863 
0864     /* cleanup DMA if it couldn't complete properly due to an error */
0865     if (priv->dma_direction != DMA_NONE)
0866         rcar_i2c_cleanup_dma(priv, true);
0867 
0868     if (!time_left) {
0869         rcar_i2c_init(priv);
0870         ret = -ETIMEDOUT;
0871     } else if (priv->flags & ID_NACK) {
0872         ret = -ENXIO;
0873     } else if (priv->flags & ID_ARBLOST) {
0874         ret = -EAGAIN;
0875     } else if (priv->flags & ID_EPROTO) {
0876         ret = -EPROTO;
0877     } else {
0878         ret = num - priv->msgs_left; /* The number of transfer */
0879     }
0880 out:
0881     pm_runtime_put(dev);
0882 
0883     if (ret < 0 && ret != -ENXIO)
0884         dev_err(dev, "error %d : %x\n", ret, priv->flags);
0885 
0886     return ret;
0887 }
0888 
0889 static int rcar_i2c_master_xfer_atomic(struct i2c_adapter *adap,
0890                 struct i2c_msg *msgs,
0891                 int num)
0892 {
0893     struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
0894     struct device *dev = rcar_i2c_priv_to_dev(priv);
0895     unsigned long j;
0896     bool time_left;
0897     int ret;
0898 
0899     priv->flags &= ~ID_P_NOT_ATOMIC;
0900 
0901     pm_runtime_get_sync(dev);
0902 
0903     /* Check bus state before init otherwise bus busy info will be lost */
0904     ret = rcar_i2c_bus_barrier(priv);
0905     if (ret < 0)
0906         goto out;
0907 
0908     rcar_i2c_init(priv);
0909     rcar_i2c_first_msg(priv, msgs, num);
0910 
0911     j = jiffies + num * adap->timeout;
0912     do {
0913         u32 msr = rcar_i2c_read(priv, ICMSR);
0914 
0915         msr &= (rcar_i2c_is_recv(priv) ? RCAR_IRQ_RECV : RCAR_IRQ_SEND) | RCAR_IRQ_STOP;
0916 
0917         if (msr) {
0918             if (priv->devtype < I2C_RCAR_GEN3)
0919                 rcar_i2c_gen2_irq(0, priv);
0920             else
0921                 rcar_i2c_gen3_irq(0, priv);
0922         }
0923 
0924         time_left = time_before_eq(jiffies, j);
0925     } while (!(priv->flags & ID_DONE) && time_left);
0926 
0927     if (!time_left) {
0928         rcar_i2c_init(priv);
0929         ret = -ETIMEDOUT;
0930     } else if (priv->flags & ID_NACK) {
0931         ret = -ENXIO;
0932     } else if (priv->flags & ID_ARBLOST) {
0933         ret = -EAGAIN;
0934     } else if (priv->flags & ID_EPROTO) {
0935         ret = -EPROTO;
0936     } else {
0937         ret = num - priv->msgs_left; /* The number of transfer */
0938     }
0939 out:
0940     pm_runtime_put(dev);
0941 
0942     if (ret < 0 && ret != -ENXIO)
0943         dev_err(dev, "error %d : %x\n", ret, priv->flags);
0944 
0945     return ret;
0946 }
0947 
0948 static int rcar_reg_slave(struct i2c_client *slave)
0949 {
0950     struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
0951 
0952     if (priv->slave)
0953         return -EBUSY;
0954 
0955     if (slave->flags & I2C_CLIENT_TEN)
0956         return -EAFNOSUPPORT;
0957 
0958     /* Keep device active for slave address detection logic */
0959     pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
0960 
0961     priv->slave = slave;
0962     rcar_i2c_write(priv, ICSAR, slave->addr);
0963     rcar_i2c_write(priv, ICSSR, 0);
0964     rcar_i2c_write(priv, ICSIER, SAR);
0965     rcar_i2c_write(priv, ICSCR, SIE | SDBS);
0966 
0967     return 0;
0968 }
0969 
0970 static int rcar_unreg_slave(struct i2c_client *slave)
0971 {
0972     struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
0973 
0974     WARN_ON(!priv->slave);
0975 
0976     /* ensure no irq is running before clearing ptr */
0977     disable_irq(priv->irq);
0978     rcar_i2c_write(priv, ICSIER, 0);
0979     rcar_i2c_write(priv, ICSSR, 0);
0980     enable_irq(priv->irq);
0981     rcar_i2c_write(priv, ICSCR, SDBS);
0982     rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
0983 
0984     priv->slave = NULL;
0985 
0986     pm_runtime_put(rcar_i2c_priv_to_dev(priv));
0987 
0988     return 0;
0989 }
0990 
0991 static u32 rcar_i2c_func(struct i2c_adapter *adap)
0992 {
0993     struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
0994 
0995     /*
0996      * This HW can't do:
0997      * I2C_SMBUS_QUICK (setting FSB during START didn't work)
0998      * I2C_M_NOSTART (automatically sends address after START)
0999      * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
1000      */
1001     u32 func = I2C_FUNC_I2C | I2C_FUNC_SLAVE |
1002            (I2C_FUNC_SMBUS_EMUL_ALL & ~I2C_FUNC_SMBUS_QUICK);
1003 
1004     if (priv->flags & ID_P_HOST_NOTIFY)
1005         func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
1006 
1007     return func;
1008 }
1009 
1010 static const struct i2c_algorithm rcar_i2c_algo = {
1011     .master_xfer    = rcar_i2c_master_xfer,
1012     .master_xfer_atomic = rcar_i2c_master_xfer_atomic,
1013     .functionality  = rcar_i2c_func,
1014     .reg_slave  = rcar_reg_slave,
1015     .unreg_slave    = rcar_unreg_slave,
1016 };
1017 
1018 static const struct i2c_adapter_quirks rcar_i2c_quirks = {
1019     .flags = I2C_AQ_NO_ZERO_LEN,
1020 };
1021 
1022 static const struct of_device_id rcar_i2c_dt_ids[] = {
1023     { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
1024     { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
1025     { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
1026     { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
1027     { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
1028     { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
1029     { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
1030     { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
1031     { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
1032     { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
1033     { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
1034     { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
1035     { .compatible = "renesas,rcar-gen4-i2c", .data = (void *)I2C_RCAR_GEN3 },
1036     {},
1037 };
1038 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
1039 
1040 static int rcar_i2c_probe(struct platform_device *pdev)
1041 {
1042     struct rcar_i2c_priv *priv;
1043     struct i2c_adapter *adap;
1044     struct device *dev = &pdev->dev;
1045     unsigned long irqflags = 0;
1046     irqreturn_t (*irqhandler)(int irq, void *ptr) = rcar_i2c_gen3_irq;
1047     int ret;
1048 
1049     /* Otherwise logic will break because some bytes must always use PIO */
1050     BUILD_BUG_ON_MSG(RCAR_MIN_DMA_LEN < 3, "Invalid min DMA length");
1051 
1052     priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
1053     if (!priv)
1054         return -ENOMEM;
1055 
1056     priv->clk = devm_clk_get(dev, NULL);
1057     if (IS_ERR(priv->clk)) {
1058         dev_err(dev, "cannot get clock\n");
1059         return PTR_ERR(priv->clk);
1060     }
1061 
1062     priv->io = devm_platform_get_and_ioremap_resource(pdev, 0, &priv->res);
1063     if (IS_ERR(priv->io))
1064         return PTR_ERR(priv->io);
1065 
1066     priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
1067     init_waitqueue_head(&priv->wait);
1068 
1069     adap = &priv->adap;
1070     adap->nr = pdev->id;
1071     adap->algo = &rcar_i2c_algo;
1072     adap->class = I2C_CLASS_DEPRECATED;
1073     adap->retries = 3;
1074     adap->dev.parent = dev;
1075     adap->dev.of_node = dev->of_node;
1076     adap->bus_recovery_info = &rcar_i2c_bri;
1077     adap->quirks = &rcar_i2c_quirks;
1078     i2c_set_adapdata(adap, priv);
1079     strscpy(adap->name, pdev->name, sizeof(adap->name));
1080 
1081     /* Init DMA */
1082     sg_init_table(&priv->sg, 1);
1083     priv->dma_direction = DMA_NONE;
1084     priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
1085 
1086     /* Activate device for clock calculation */
1087     pm_runtime_enable(dev);
1088     pm_runtime_get_sync(dev);
1089     ret = rcar_i2c_clock_calculate(priv);
1090     if (ret < 0) {
1091         pm_runtime_put(dev);
1092         goto out_pm_disable;
1093     }
1094 
1095     rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
1096 
1097     if (priv->devtype < I2C_RCAR_GEN3) {
1098         irqflags |= IRQF_NO_THREAD;
1099         irqhandler = rcar_i2c_gen2_irq;
1100     }
1101 
1102     if (priv->devtype == I2C_RCAR_GEN3) {
1103         priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1104         if (!IS_ERR(priv->rstc)) {
1105             ret = reset_control_status(priv->rstc);
1106             if (ret < 0)
1107                 priv->rstc = ERR_PTR(-ENOTSUPP);
1108         }
1109     }
1110 
1111     /* Stay always active when multi-master to keep arbitration working */
1112     if (of_property_read_bool(dev->of_node, "multi-master"))
1113         priv->flags |= ID_P_PM_BLOCKED;
1114     else
1115         pm_runtime_put(dev);
1116 
1117     if (of_property_read_bool(dev->of_node, "smbus"))
1118         priv->flags |= ID_P_HOST_NOTIFY;
1119 
1120     ret = platform_get_irq(pdev, 0);
1121     if (ret < 0)
1122         goto out_pm_put;
1123     priv->irq = ret;
1124     ret = devm_request_irq(dev, priv->irq, irqhandler, irqflags, dev_name(dev), priv);
1125     if (ret < 0) {
1126         dev_err(dev, "cannot get irq %d\n", priv->irq);
1127         goto out_pm_put;
1128     }
1129 
1130     platform_set_drvdata(pdev, priv);
1131 
1132     ret = i2c_add_numbered_adapter(adap);
1133     if (ret < 0)
1134         goto out_pm_put;
1135 
1136     if (priv->flags & ID_P_HOST_NOTIFY) {
1137         priv->host_notify_client = i2c_new_slave_host_notify_device(adap);
1138         if (IS_ERR(priv->host_notify_client)) {
1139             ret = PTR_ERR(priv->host_notify_client);
1140             goto out_del_device;
1141         }
1142     }
1143 
1144     dev_info(dev, "probed\n");
1145 
1146     return 0;
1147 
1148  out_del_device:
1149     i2c_del_adapter(&priv->adap);
1150  out_pm_put:
1151     if (priv->flags & ID_P_PM_BLOCKED)
1152         pm_runtime_put(dev);
1153  out_pm_disable:
1154     pm_runtime_disable(dev);
1155     return ret;
1156 }
1157 
1158 static int rcar_i2c_remove(struct platform_device *pdev)
1159 {
1160     struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
1161     struct device *dev = &pdev->dev;
1162 
1163     if (priv->host_notify_client)
1164         i2c_free_slave_host_notify_device(priv->host_notify_client);
1165     i2c_del_adapter(&priv->adap);
1166     rcar_i2c_release_dma(priv);
1167     if (priv->flags & ID_P_PM_BLOCKED)
1168         pm_runtime_put(dev);
1169     pm_runtime_disable(dev);
1170 
1171     return 0;
1172 }
1173 
1174 #ifdef CONFIG_PM_SLEEP
1175 static int rcar_i2c_suspend(struct device *dev)
1176 {
1177     struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1178 
1179     i2c_mark_adapter_suspended(&priv->adap);
1180     return 0;
1181 }
1182 
1183 static int rcar_i2c_resume(struct device *dev)
1184 {
1185     struct rcar_i2c_priv *priv = dev_get_drvdata(dev);
1186 
1187     i2c_mark_adapter_resumed(&priv->adap);
1188     return 0;
1189 }
1190 
1191 static const struct dev_pm_ops rcar_i2c_pm_ops = {
1192     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rcar_i2c_suspend, rcar_i2c_resume)
1193 };
1194 
1195 #define DEV_PM_OPS (&rcar_i2c_pm_ops)
1196 #else
1197 #define DEV_PM_OPS NULL
1198 #endif /* CONFIG_PM_SLEEP */
1199 
1200 static struct platform_driver rcar_i2c_driver = {
1201     .driver = {
1202         .name   = "i2c-rcar",
1203         .of_match_table = rcar_i2c_dt_ids,
1204         .pm = DEV_PM_OPS,
1205     },
1206     .probe      = rcar_i2c_probe,
1207     .remove     = rcar_i2c_remove,
1208 };
1209 
1210 module_platform_driver(rcar_i2c_driver);
1211 
1212 MODULE_LICENSE("GPL v2");
1213 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
1214 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
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