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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
0003 
0004 #include <linux/acpi.h>
0005 #include <linux/clk.h>
0006 #include <linux/dmaengine.h>
0007 #include <linux/dma-mapping.h>
0008 #include <linux/dma/qcom-gpi-dma.h>
0009 #include <linux/err.h>
0010 #include <linux/i2c.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/io.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/qcom-geni-se.h>
0018 #include <linux/spinlock.h>
0019 
0020 #define SE_I2C_TX_TRANS_LEN     0x26c
0021 #define SE_I2C_RX_TRANS_LEN     0x270
0022 #define SE_I2C_SCL_COUNTERS     0x278
0023 
0024 #define SE_I2C_ERR  (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
0025             M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
0026 #define SE_I2C_ABORT        BIT(1)
0027 
0028 /* M_CMD OP codes for I2C */
0029 #define I2C_WRITE       0x1
0030 #define I2C_READ        0x2
0031 #define I2C_WRITE_READ      0x3
0032 #define I2C_ADDR_ONLY       0x4
0033 #define I2C_BUS_CLEAR       0x6
0034 #define I2C_STOP_ON_BUS     0x7
0035 /* M_CMD params for I2C */
0036 #define PRE_CMD_DELAY       BIT(0)
0037 #define TIMESTAMP_BEFORE    BIT(1)
0038 #define STOP_STRETCH        BIT(2)
0039 #define TIMESTAMP_AFTER     BIT(3)
0040 #define POST_COMMAND_DELAY  BIT(4)
0041 #define IGNORE_ADD_NACK     BIT(6)
0042 #define READ_FINISHED_WITH_ACK  BIT(7)
0043 #define BYPASS_ADDR_PHASE   BIT(8)
0044 #define SLV_ADDR_MSK        GENMASK(15, 9)
0045 #define SLV_ADDR_SHFT       9
0046 /* I2C SCL COUNTER fields */
0047 #define HIGH_COUNTER_MSK    GENMASK(29, 20)
0048 #define HIGH_COUNTER_SHFT   20
0049 #define LOW_COUNTER_MSK     GENMASK(19, 10)
0050 #define LOW_COUNTER_SHFT    10
0051 #define CYCLE_COUNTER_MSK   GENMASK(9, 0)
0052 
0053 #define I2C_PACK_TX     BIT(0)
0054 #define I2C_PACK_RX     BIT(1)
0055 
0056 enum geni_i2c_err_code {
0057     GP_IRQ0,
0058     NACK,
0059     GP_IRQ2,
0060     BUS_PROTO,
0061     ARB_LOST,
0062     GP_IRQ5,
0063     GENI_OVERRUN,
0064     GENI_ILLEGAL_CMD,
0065     GENI_ABORT_DONE,
0066     GENI_TIMEOUT,
0067 };
0068 
0069 #define DM_I2C_CB_ERR       ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
0070                                     << 5)
0071 
0072 #define I2C_AUTO_SUSPEND_DELAY  250
0073 #define KHZ(freq)       (1000 * freq)
0074 #define PACKING_BYTES_PW    4
0075 
0076 #define ABORT_TIMEOUT       HZ
0077 #define XFER_TIMEOUT        HZ
0078 #define RST_TIMEOUT     HZ
0079 
0080 struct geni_i2c_dev {
0081     struct geni_se se;
0082     u32 tx_wm;
0083     int irq;
0084     int err;
0085     struct i2c_adapter adap;
0086     struct completion done;
0087     struct i2c_msg *cur;
0088     int cur_wr;
0089     int cur_rd;
0090     spinlock_t lock;
0091     u32 clk_freq_out;
0092     const struct geni_i2c_clk_fld *clk_fld;
0093     int suspended;
0094     void *dma_buf;
0095     size_t xfer_len;
0096     dma_addr_t dma_addr;
0097     struct dma_chan *tx_c;
0098     struct dma_chan *rx_c;
0099     bool gpi_mode;
0100     bool abort_done;
0101 };
0102 
0103 struct geni_i2c_err_log {
0104     int err;
0105     const char *msg;
0106 };
0107 
0108 static const struct geni_i2c_err_log gi2c_log[] = {
0109     [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
0110     [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
0111     [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
0112     [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"},
0113     [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
0114     [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
0115     [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
0116     [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
0117     [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
0118     [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
0119 };
0120 
0121 struct geni_i2c_clk_fld {
0122     u32 clk_freq_out;
0123     u8  clk_div;
0124     u8  t_high_cnt;
0125     u8  t_low_cnt;
0126     u8  t_cycle_cnt;
0127 };
0128 
0129 /*
0130  * Hardware uses the underlying formula to calculate time periods of
0131  * SCL clock cycle. Firmware uses some additional cycles excluded from the
0132  * below formula and it is confirmed that the time periods are within
0133  * specification limits.
0134  *
0135  * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
0136  * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
0137  * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
0138  * clk_freq_out = t / t_cycle
0139  * source_clock = 19.2 MHz
0140  */
0141 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
0142     {KHZ(100), 7, 10, 11, 26},
0143     {KHZ(400), 2,  5, 12, 24},
0144     {KHZ(1000), 1, 3,  9, 18},
0145 };
0146 
0147 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
0148 {
0149     int i;
0150     const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
0151 
0152     for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
0153         if (itr->clk_freq_out == gi2c->clk_freq_out) {
0154             gi2c->clk_fld = itr;
0155             return 0;
0156         }
0157     }
0158     return -EINVAL;
0159 }
0160 
0161 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
0162 {
0163     const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
0164     u32 val;
0165 
0166     writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
0167 
0168     val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
0169     writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
0170 
0171     val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
0172     val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
0173     val |= itr->t_cycle_cnt;
0174     writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
0175 }
0176 
0177 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
0178 {
0179     u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
0180     u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
0181     u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
0182     u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
0183     u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
0184     u32 rx_st, tx_st;
0185 
0186     if (dma) {
0187         rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
0188         tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
0189     } else {
0190         rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
0191         tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
0192     }
0193     dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
0194         dma, tx_st, rx_st, m_stat);
0195     dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
0196         m_cmd, geni_s, geni_ios);
0197 }
0198 
0199 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
0200 {
0201     if (!gi2c->err)
0202         gi2c->err = gi2c_log[err].err;
0203     if (gi2c->cur)
0204         dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
0205             gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
0206 
0207     switch (err) {
0208     case GENI_ABORT_DONE:
0209         gi2c->abort_done = true;
0210         break;
0211     case NACK:
0212     case GENI_TIMEOUT:
0213         dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
0214         break;
0215     default:
0216         dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
0217         geni_i2c_err_misc(gi2c);
0218         break;
0219     }
0220 }
0221 
0222 static irqreturn_t geni_i2c_irq(int irq, void *dev)
0223 {
0224     struct geni_i2c_dev *gi2c = dev;
0225     void __iomem *base = gi2c->se.base;
0226     int j, p;
0227     u32 m_stat;
0228     u32 rx_st;
0229     u32 dm_tx_st;
0230     u32 dm_rx_st;
0231     u32 dma;
0232     u32 val;
0233     struct i2c_msg *cur;
0234 
0235     spin_lock(&gi2c->lock);
0236     m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
0237     rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
0238     dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
0239     dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
0240     dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
0241     cur = gi2c->cur;
0242 
0243     if (!cur ||
0244         m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
0245         dm_rx_st & (DM_I2C_CB_ERR)) {
0246         if (m_stat & M_GP_IRQ_1_EN)
0247             geni_i2c_err(gi2c, NACK);
0248         if (m_stat & M_GP_IRQ_3_EN)
0249             geni_i2c_err(gi2c, BUS_PROTO);
0250         if (m_stat & M_GP_IRQ_4_EN)
0251             geni_i2c_err(gi2c, ARB_LOST);
0252         if (m_stat & M_CMD_OVERRUN_EN)
0253             geni_i2c_err(gi2c, GENI_OVERRUN);
0254         if (m_stat & M_ILLEGAL_CMD_EN)
0255             geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
0256         if (m_stat & M_CMD_ABORT_EN)
0257             geni_i2c_err(gi2c, GENI_ABORT_DONE);
0258         if (m_stat & M_GP_IRQ_0_EN)
0259             geni_i2c_err(gi2c, GP_IRQ0);
0260 
0261         /* Disable the TX Watermark interrupt to stop TX */
0262         if (!dma)
0263             writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
0264     } else if (dma) {
0265         dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
0266             dm_tx_st, dm_rx_st);
0267     } else if (cur->flags & I2C_M_RD &&
0268            m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
0269         u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
0270 
0271         for (j = 0; j < rxcnt; j++) {
0272             p = 0;
0273             val = readl_relaxed(base + SE_GENI_RX_FIFOn);
0274             while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
0275                 cur->buf[gi2c->cur_rd++] = val & 0xff;
0276                 val >>= 8;
0277                 p++;
0278             }
0279             if (gi2c->cur_rd == cur->len)
0280                 break;
0281         }
0282     } else if (!(cur->flags & I2C_M_RD) &&
0283            m_stat & M_TX_FIFO_WATERMARK_EN) {
0284         for (j = 0; j < gi2c->tx_wm; j++) {
0285             u32 temp;
0286 
0287             val = 0;
0288             p = 0;
0289             while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
0290                 temp = cur->buf[gi2c->cur_wr++];
0291                 val |= temp << (p * 8);
0292                 p++;
0293             }
0294             writel_relaxed(val, base + SE_GENI_TX_FIFOn);
0295             /* TX Complete, Disable the TX Watermark interrupt */
0296             if (gi2c->cur_wr == cur->len) {
0297                 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
0298                 break;
0299             }
0300         }
0301     }
0302 
0303     if (m_stat)
0304         writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
0305 
0306     if (dma && dm_tx_st)
0307         writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
0308     if (dma && dm_rx_st)
0309         writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
0310 
0311     /* if this is err with done-bit not set, handle that through timeout. */
0312     if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
0313         dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
0314         dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
0315         complete(&gi2c->done);
0316 
0317     spin_unlock(&gi2c->lock);
0318 
0319     return IRQ_HANDLED;
0320 }
0321 
0322 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
0323 {
0324     unsigned long time_left = ABORT_TIMEOUT;
0325     unsigned long flags;
0326 
0327     spin_lock_irqsave(&gi2c->lock, flags);
0328     geni_i2c_err(gi2c, GENI_TIMEOUT);
0329     gi2c->cur = NULL;
0330     gi2c->abort_done = false;
0331     geni_se_abort_m_cmd(&gi2c->se);
0332     spin_unlock_irqrestore(&gi2c->lock, flags);
0333 
0334     do {
0335         time_left = wait_for_completion_timeout(&gi2c->done, time_left);
0336     } while (!gi2c->abort_done && time_left);
0337 
0338     if (!time_left)
0339         dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
0340 }
0341 
0342 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
0343 {
0344     u32 val;
0345     unsigned long time_left = RST_TIMEOUT;
0346 
0347     writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
0348     do {
0349         time_left = wait_for_completion_timeout(&gi2c->done, time_left);
0350         val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
0351     } while (!(val & RX_RESET_DONE) && time_left);
0352 
0353     if (!(val & RX_RESET_DONE))
0354         dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
0355 }
0356 
0357 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
0358 {
0359     u32 val;
0360     unsigned long time_left = RST_TIMEOUT;
0361 
0362     writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
0363     do {
0364         time_left = wait_for_completion_timeout(&gi2c->done, time_left);
0365         val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
0366     } while (!(val & TX_RESET_DONE) && time_left);
0367 
0368     if (!(val & TX_RESET_DONE))
0369         dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
0370 }
0371 
0372 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
0373                      struct i2c_msg *cur)
0374 {
0375     gi2c->cur_rd = 0;
0376     if (gi2c->dma_buf) {
0377         if (gi2c->err)
0378             geni_i2c_rx_fsm_rst(gi2c);
0379         geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
0380         i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
0381     }
0382 }
0383 
0384 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
0385                      struct i2c_msg *cur)
0386 {
0387     gi2c->cur_wr = 0;
0388     if (gi2c->dma_buf) {
0389         if (gi2c->err)
0390             geni_i2c_tx_fsm_rst(gi2c);
0391         geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
0392         i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
0393     }
0394 }
0395 
0396 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
0397                 u32 m_param)
0398 {
0399     dma_addr_t rx_dma = 0;
0400     unsigned long time_left;
0401     void *dma_buf;
0402     struct geni_se *se = &gi2c->se;
0403     size_t len = msg->len;
0404     struct i2c_msg *cur;
0405 
0406     dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
0407     if (dma_buf)
0408         geni_se_select_mode(se, GENI_SE_DMA);
0409     else
0410         geni_se_select_mode(se, GENI_SE_FIFO);
0411 
0412     writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
0413     geni_se_setup_m_cmd(se, I2C_READ, m_param);
0414 
0415     if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
0416         geni_se_select_mode(se, GENI_SE_FIFO);
0417         i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
0418         dma_buf = NULL;
0419     } else {
0420         gi2c->xfer_len = len;
0421         gi2c->dma_addr = rx_dma;
0422         gi2c->dma_buf = dma_buf;
0423     }
0424 
0425     cur = gi2c->cur;
0426     time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
0427     if (!time_left)
0428         geni_i2c_abort_xfer(gi2c);
0429 
0430     geni_i2c_rx_msg_cleanup(gi2c, cur);
0431 
0432     return gi2c->err;
0433 }
0434 
0435 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
0436                 u32 m_param)
0437 {
0438     dma_addr_t tx_dma = 0;
0439     unsigned long time_left;
0440     void *dma_buf;
0441     struct geni_se *se = &gi2c->se;
0442     size_t len = msg->len;
0443     struct i2c_msg *cur;
0444 
0445     dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
0446     if (dma_buf)
0447         geni_se_select_mode(se, GENI_SE_DMA);
0448     else
0449         geni_se_select_mode(se, GENI_SE_FIFO);
0450 
0451     writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
0452     geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
0453 
0454     if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
0455         geni_se_select_mode(se, GENI_SE_FIFO);
0456         i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
0457         dma_buf = NULL;
0458     } else {
0459         gi2c->xfer_len = len;
0460         gi2c->dma_addr = tx_dma;
0461         gi2c->dma_buf = dma_buf;
0462     }
0463 
0464     if (!dma_buf) /* Get FIFO IRQ */
0465         writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
0466 
0467     cur = gi2c->cur;
0468     time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
0469     if (!time_left)
0470         geni_i2c_abort_xfer(gi2c);
0471 
0472     geni_i2c_tx_msg_cleanup(gi2c, cur);
0473 
0474     return gi2c->err;
0475 }
0476 
0477 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result)
0478 {
0479     struct geni_i2c_dev *gi2c = cb;
0480 
0481     if (result->result != DMA_TRANS_NOERROR) {
0482         dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result);
0483         gi2c->err = -EIO;
0484     } else if (result->residue) {
0485         dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue);
0486     }
0487 
0488     complete(&gi2c->done);
0489 }
0490 
0491 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
0492                    void *tx_buf, dma_addr_t tx_addr,
0493                    void *rx_buf, dma_addr_t rx_addr)
0494 {
0495     if (tx_buf) {
0496         dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE);
0497         i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err);
0498     }
0499 
0500     if (rx_buf) {
0501         dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE);
0502         i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err);
0503     }
0504 }
0505 
0506 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
0507             struct dma_slave_config *config, dma_addr_t *dma_addr_p,
0508             void **buf, unsigned int op, struct dma_chan *dma_chan)
0509 {
0510     struct gpi_i2c_config *peripheral;
0511     unsigned int flags;
0512     void *dma_buf;
0513     dma_addr_t addr;
0514     enum dma_data_direction map_dirn;
0515     enum dma_transfer_direction dma_dirn;
0516     struct dma_async_tx_descriptor *desc;
0517     int ret;
0518 
0519     peripheral = config->peripheral_config;
0520 
0521     dma_buf = i2c_get_dma_safe_msg_buf(msg, 1);
0522     if (!dma_buf)
0523         return -ENOMEM;
0524 
0525     if (op == I2C_WRITE)
0526         map_dirn = DMA_TO_DEVICE;
0527     else
0528         map_dirn = DMA_FROM_DEVICE;
0529 
0530     addr = dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn);
0531     if (dma_mapping_error(gi2c->se.dev->parent, addr)) {
0532         i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
0533         return -ENOMEM;
0534     }
0535 
0536     /* set the length as message for rx txn */
0537     peripheral->rx_len = msg->len;
0538     peripheral->op = op;
0539 
0540     ret = dmaengine_slave_config(dma_chan, config);
0541     if (ret) {
0542         dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op);
0543         goto err_config;
0544     }
0545 
0546     peripheral->set_config = 0;
0547     peripheral->multi_msg = true;
0548     flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
0549 
0550     if (op == I2C_WRITE)
0551         dma_dirn = DMA_MEM_TO_DEV;
0552     else
0553         dma_dirn = DMA_DEV_TO_MEM;
0554 
0555     desc = dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, flags);
0556     if (!desc) {
0557         dev_err(gi2c->se.dev, "prep_slave_sg failed\n");
0558         ret = -EIO;
0559         goto err_config;
0560     }
0561 
0562     desc->callback_result = i2c_gpi_cb_result;
0563     desc->callback_param = gi2c;
0564 
0565     dmaengine_submit(desc);
0566     *buf = dma_buf;
0567     *dma_addr_p = addr;
0568 
0569     return 0;
0570 
0571 err_config:
0572     dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn);
0573     i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
0574     return ret;
0575 }
0576 
0577 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num)
0578 {
0579     struct dma_slave_config config = {};
0580     struct gpi_i2c_config peripheral = {};
0581     int i, ret = 0, timeout;
0582     dma_addr_t tx_addr, rx_addr;
0583     void *tx_buf = NULL, *rx_buf = NULL;
0584     const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
0585 
0586     config.peripheral_config = &peripheral;
0587     config.peripheral_size = sizeof(peripheral);
0588 
0589     peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX;
0590     peripheral.cycle_count = itr->t_cycle_cnt;
0591     peripheral.high_count = itr->t_high_cnt;
0592     peripheral.low_count = itr->t_low_cnt;
0593     peripheral.clk_div = itr->clk_div;
0594     peripheral.set_config = 1;
0595     peripheral.multi_msg = false;
0596 
0597     for (i = 0; i < num; i++) {
0598         gi2c->cur = &msgs[i];
0599         gi2c->err = 0;
0600         dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len);
0601 
0602         peripheral.stretch = 0;
0603         if (i < num - 1)
0604             peripheral.stretch = 1;
0605 
0606         peripheral.addr = msgs[i].addr;
0607 
0608         if (msgs[i].flags & I2C_M_RD) {
0609             ret =  geni_i2c_gpi(gi2c, &msgs[i], &config,
0610                         &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c);
0611             if (ret)
0612                 goto err;
0613         }
0614 
0615         ret =  geni_i2c_gpi(gi2c, &msgs[i], &config,
0616                     &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c);
0617         if (ret)
0618             goto err;
0619 
0620         if (msgs[i].flags & I2C_M_RD)
0621             dma_async_issue_pending(gi2c->rx_c);
0622         dma_async_issue_pending(gi2c->tx_c);
0623 
0624         timeout = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
0625         if (!timeout) {
0626             dev_err(gi2c->se.dev, "I2C timeout gpi flags:%d addr:0x%x\n",
0627                 gi2c->cur->flags, gi2c->cur->addr);
0628             gi2c->err = -ETIMEDOUT;
0629             goto err;
0630         }
0631 
0632         if (gi2c->err) {
0633             ret = gi2c->err;
0634             goto err;
0635         }
0636 
0637         geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
0638     }
0639 
0640     return num;
0641 
0642 err:
0643     dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret);
0644     dmaengine_terminate_sync(gi2c->rx_c);
0645     dmaengine_terminate_sync(gi2c->tx_c);
0646     geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
0647     return ret;
0648 }
0649 
0650 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c,
0651                   struct i2c_msg msgs[], int num)
0652 {
0653     int i, ret = 0;
0654 
0655     for (i = 0; i < num; i++) {
0656         u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
0657 
0658         m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
0659 
0660         gi2c->cur = &msgs[i];
0661         if (msgs[i].flags & I2C_M_RD)
0662             ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
0663         else
0664             ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
0665 
0666         if (ret)
0667             return ret;
0668     }
0669 
0670     return num;
0671 }
0672 
0673 static int geni_i2c_xfer(struct i2c_adapter *adap,
0674              struct i2c_msg msgs[],
0675              int num)
0676 {
0677     struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
0678     int ret;
0679 
0680     gi2c->err = 0;
0681     reinit_completion(&gi2c->done);
0682     ret = pm_runtime_get_sync(gi2c->se.dev);
0683     if (ret < 0) {
0684         dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
0685         pm_runtime_put_noidle(gi2c->se.dev);
0686         /* Set device in suspended since resume failed */
0687         pm_runtime_set_suspended(gi2c->se.dev);
0688         return ret;
0689     }
0690 
0691     qcom_geni_i2c_conf(gi2c);
0692 
0693     if (gi2c->gpi_mode)
0694         ret = geni_i2c_gpi_xfer(gi2c, msgs, num);
0695     else
0696         ret = geni_i2c_fifo_xfer(gi2c, msgs, num);
0697 
0698     pm_runtime_mark_last_busy(gi2c->se.dev);
0699     pm_runtime_put_autosuspend(gi2c->se.dev);
0700     gi2c->cur = NULL;
0701     gi2c->err = 0;
0702     return ret;
0703 }
0704 
0705 static u32 geni_i2c_func(struct i2c_adapter *adap)
0706 {
0707     return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
0708 }
0709 
0710 static const struct i2c_algorithm geni_i2c_algo = {
0711     .master_xfer    = geni_i2c_xfer,
0712     .functionality  = geni_i2c_func,
0713 };
0714 
0715 #ifdef CONFIG_ACPI
0716 static const struct acpi_device_id geni_i2c_acpi_match[] = {
0717     { "QCOM0220"},
0718     { },
0719 };
0720 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
0721 #endif
0722 
0723 static void release_gpi_dma(struct geni_i2c_dev *gi2c)
0724 {
0725     if (gi2c->rx_c)
0726         dma_release_channel(gi2c->rx_c);
0727 
0728     if (gi2c->tx_c)
0729         dma_release_channel(gi2c->tx_c);
0730 }
0731 
0732 static int setup_gpi_dma(struct geni_i2c_dev *gi2c)
0733 {
0734     int ret;
0735 
0736     geni_se_select_mode(&gi2c->se, GENI_GPI_DMA);
0737     gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx");
0738     if (IS_ERR(gi2c->tx_c)) {
0739         ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c),
0740                     "Failed to get tx DMA ch\n");
0741         goto err_tx;
0742     }
0743 
0744     gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx");
0745     if (IS_ERR(gi2c->rx_c)) {
0746         ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c),
0747                     "Failed to get rx DMA ch\n");
0748         goto err_rx;
0749     }
0750 
0751     dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n");
0752     return 0;
0753 
0754 err_rx:
0755     dma_release_channel(gi2c->tx_c);
0756 err_tx:
0757     return ret;
0758 }
0759 
0760 static int geni_i2c_probe(struct platform_device *pdev)
0761 {
0762     struct geni_i2c_dev *gi2c;
0763     struct resource *res;
0764     u32 proto, tx_depth, fifo_disable;
0765     int ret;
0766     struct device *dev = &pdev->dev;
0767 
0768     gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
0769     if (!gi2c)
0770         return -ENOMEM;
0771 
0772     gi2c->se.dev = dev;
0773     gi2c->se.wrapper = dev_get_drvdata(dev->parent);
0774     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0775     gi2c->se.base = devm_ioremap_resource(dev, res);
0776     if (IS_ERR(gi2c->se.base))
0777         return PTR_ERR(gi2c->se.base);
0778 
0779     gi2c->se.clk = devm_clk_get(dev, "se");
0780     if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
0781         return PTR_ERR(gi2c->se.clk);
0782 
0783     ret = device_property_read_u32(dev, "clock-frequency",
0784                        &gi2c->clk_freq_out);
0785     if (ret) {
0786         dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
0787         gi2c->clk_freq_out = KHZ(100);
0788     }
0789 
0790     if (has_acpi_companion(dev))
0791         ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
0792 
0793     gi2c->irq = platform_get_irq(pdev, 0);
0794     if (gi2c->irq < 0)
0795         return gi2c->irq;
0796 
0797     ret = geni_i2c_clk_map_idx(gi2c);
0798     if (ret) {
0799         dev_err(dev, "Invalid clk frequency %d Hz: %d\n",
0800             gi2c->clk_freq_out, ret);
0801         return ret;
0802     }
0803 
0804     gi2c->adap.algo = &geni_i2c_algo;
0805     init_completion(&gi2c->done);
0806     spin_lock_init(&gi2c->lock);
0807     platform_set_drvdata(pdev, gi2c);
0808     ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0,
0809                    dev_name(dev), gi2c);
0810     if (ret) {
0811         dev_err(dev, "Request_irq failed:%d: err:%d\n",
0812             gi2c->irq, ret);
0813         return ret;
0814     }
0815     /* Disable the interrupt so that the system can enter low-power mode */
0816     disable_irq(gi2c->irq);
0817     i2c_set_adapdata(&gi2c->adap, gi2c);
0818     gi2c->adap.dev.parent = dev;
0819     gi2c->adap.dev.of_node = dev->of_node;
0820     strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
0821 
0822     ret = geni_icc_get(&gi2c->se, "qup-memory");
0823     if (ret)
0824         return ret;
0825     /*
0826      * Set the bus quota for core and cpu to a reasonable value for
0827      * register access.
0828      * Set quota for DDR based on bus speed.
0829      */
0830     gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
0831     gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
0832     gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
0833 
0834     ret = geni_icc_set_bw(&gi2c->se);
0835     if (ret)
0836         return ret;
0837 
0838     ret = geni_se_resources_on(&gi2c->se);
0839     if (ret) {
0840         dev_err(dev, "Error turning on resources %d\n", ret);
0841         return ret;
0842     }
0843     proto = geni_se_read_proto(&gi2c->se);
0844     if (proto != GENI_SE_I2C) {
0845         dev_err(dev, "Invalid proto %d\n", proto);
0846         geni_se_resources_off(&gi2c->se);
0847         return -ENXIO;
0848     }
0849 
0850     fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
0851     if (fifo_disable) {
0852         /* FIFO is disabled, so we can only use GPI DMA */
0853         gi2c->gpi_mode = true;
0854         ret = setup_gpi_dma(gi2c);
0855         if (ret)
0856             return dev_err_probe(dev, ret, "Failed to setup GPI DMA mode\n");
0857 
0858         dev_dbg(dev, "Using GPI DMA mode for I2C\n");
0859     } else {
0860         gi2c->gpi_mode = false;
0861         tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
0862         gi2c->tx_wm = tx_depth - 1;
0863         geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
0864         geni_se_config_packing(&gi2c->se, BITS_PER_BYTE,
0865                        PACKING_BYTES_PW, true, true, true);
0866 
0867         dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
0868     }
0869 
0870     ret = geni_se_resources_off(&gi2c->se);
0871     if (ret) {
0872         dev_err(dev, "Error turning off resources %d\n", ret);
0873         goto err_dma;
0874     }
0875 
0876     ret = geni_icc_disable(&gi2c->se);
0877     if (ret)
0878         goto err_dma;
0879 
0880     gi2c->suspended = 1;
0881     pm_runtime_set_suspended(gi2c->se.dev);
0882     pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
0883     pm_runtime_use_autosuspend(gi2c->se.dev);
0884     pm_runtime_enable(gi2c->se.dev);
0885 
0886     ret = i2c_add_adapter(&gi2c->adap);
0887     if (ret) {
0888         dev_err(dev, "Error adding i2c adapter %d\n", ret);
0889         pm_runtime_disable(gi2c->se.dev);
0890         goto err_dma;
0891     }
0892 
0893     dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
0894 
0895     return 0;
0896 
0897 err_dma:
0898     release_gpi_dma(gi2c);
0899     return ret;
0900 }
0901 
0902 static int geni_i2c_remove(struct platform_device *pdev)
0903 {
0904     struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
0905 
0906     i2c_del_adapter(&gi2c->adap);
0907     release_gpi_dma(gi2c);
0908     pm_runtime_disable(gi2c->se.dev);
0909     return 0;
0910 }
0911 
0912 static void geni_i2c_shutdown(struct platform_device *pdev)
0913 {
0914     struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
0915 
0916     /* Make client i2c transfers start failing */
0917     i2c_mark_adapter_suspended(&gi2c->adap);
0918 }
0919 
0920 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
0921 {
0922     int ret;
0923     struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
0924 
0925     disable_irq(gi2c->irq);
0926     ret = geni_se_resources_off(&gi2c->se);
0927     if (ret) {
0928         enable_irq(gi2c->irq);
0929         return ret;
0930 
0931     } else {
0932         gi2c->suspended = 1;
0933     }
0934 
0935     return geni_icc_disable(&gi2c->se);
0936 }
0937 
0938 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
0939 {
0940     int ret;
0941     struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
0942 
0943     ret = geni_icc_enable(&gi2c->se);
0944     if (ret)
0945         return ret;
0946 
0947     ret = geni_se_resources_on(&gi2c->se);
0948     if (ret)
0949         return ret;
0950 
0951     enable_irq(gi2c->irq);
0952     gi2c->suspended = 0;
0953     return 0;
0954 }
0955 
0956 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
0957 {
0958     struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
0959 
0960     i2c_mark_adapter_suspended(&gi2c->adap);
0961 
0962     if (!gi2c->suspended) {
0963         geni_i2c_runtime_suspend(dev);
0964         pm_runtime_disable(dev);
0965         pm_runtime_set_suspended(dev);
0966         pm_runtime_enable(dev);
0967     }
0968     return 0;
0969 }
0970 
0971 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
0972 {
0973     struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
0974 
0975     i2c_mark_adapter_resumed(&gi2c->adap);
0976     return 0;
0977 }
0978 
0979 static const struct dev_pm_ops geni_i2c_pm_ops = {
0980     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
0981     SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
0982                                     NULL)
0983 };
0984 
0985 static const struct of_device_id geni_i2c_dt_match[] = {
0986     { .compatible = "qcom,geni-i2c" },
0987     {}
0988 };
0989 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
0990 
0991 static struct platform_driver geni_i2c_driver = {
0992     .probe  = geni_i2c_probe,
0993     .remove = geni_i2c_remove,
0994     .shutdown = geni_i2c_shutdown,
0995     .driver = {
0996         .name = "geni_i2c",
0997         .pm = &geni_i2c_pm_ops,
0998         .of_match_table = geni_i2c_dt_match,
0999         .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
1000     },
1001 };
1002 
1003 module_platform_driver(geni_i2c_driver);
1004 
1005 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
1006 MODULE_LICENSE("GPL v2");
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