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0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
0003 // Copyright (c) 2017-2022 Linaro Limited.
0004 
0005 #include <linux/clk.h>
0006 #include <linux/completion.h>
0007 #include <linux/i2c.h>
0008 #include <linux/io.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/pm_runtime.h>
0014 
0015 #define CCI_HW_VERSION              0x0
0016 #define CCI_RESET_CMD               0x004
0017 #define CCI_RESET_CMD_MASK          0x0f73f3f7
0018 #define CCI_RESET_CMD_M0_MASK           0x000003f1
0019 #define CCI_RESET_CMD_M1_MASK           0x0003f001
0020 #define CCI_QUEUE_START             0x008
0021 #define CCI_HALT_REQ                0x034
0022 #define CCI_HALT_REQ_I2C_M0_Q0Q1        BIT(0)
0023 #define CCI_HALT_REQ_I2C_M1_Q0Q1        BIT(1)
0024 
0025 #define CCI_I2C_Mm_SCL_CTL(m)           (0x100 + 0x100 * (m))
0026 #define CCI_I2C_Mm_SDA_CTL_0(m)         (0x104 + 0x100 * (m))
0027 #define CCI_I2C_Mm_SDA_CTL_1(m)         (0x108 + 0x100 * (m))
0028 #define CCI_I2C_Mm_SDA_CTL_2(m)         (0x10c + 0x100 * (m))
0029 #define CCI_I2C_Mm_MISC_CTL(m)          (0x110 + 0x100 * (m))
0030 
0031 #define CCI_I2C_Mm_READ_DATA(m)         (0x118 + 0x100 * (m))
0032 #define CCI_I2C_Mm_READ_BUF_LEVEL(m)        (0x11c + 0x100 * (m))
0033 #define CCI_I2C_Mm_Qn_EXEC_WORD_CNT(m, n)   (0x300 + 0x200 * (m) + 0x100 * (n))
0034 #define CCI_I2C_Mm_Qn_CUR_WORD_CNT(m, n)    (0x304 + 0x200 * (m) + 0x100 * (n))
0035 #define CCI_I2C_Mm_Qn_CUR_CMD(m, n)     (0x308 + 0x200 * (m) + 0x100 * (n))
0036 #define CCI_I2C_Mm_Qn_REPORT_STATUS(m, n)   (0x30c + 0x200 * (m) + 0x100 * (n))
0037 #define CCI_I2C_Mm_Qn_LOAD_DATA(m, n)       (0x310 + 0x200 * (m) + 0x100 * (n))
0038 
0039 #define CCI_IRQ_GLOBAL_CLEAR_CMD        0xc00
0040 #define CCI_IRQ_MASK_0              0xc04
0041 #define CCI_IRQ_MASK_0_I2C_M0_RD_DONE       BIT(0)
0042 #define CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT     BIT(4)
0043 #define CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT     BIT(8)
0044 #define CCI_IRQ_MASK_0_I2C_M1_RD_DONE       BIT(12)
0045 #define CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT     BIT(16)
0046 #define CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT     BIT(20)
0047 #define CCI_IRQ_MASK_0_RST_DONE_ACK     BIT(24)
0048 #define CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK BIT(25)
0049 #define CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK BIT(26)
0050 #define CCI_IRQ_MASK_0_I2C_M0_ERROR     0x18000ee6
0051 #define CCI_IRQ_MASK_0_I2C_M1_ERROR     0x60ee6000
0052 #define CCI_IRQ_CLEAR_0             0xc08
0053 #define CCI_IRQ_STATUS_0            0xc0c
0054 #define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE     BIT(0)
0055 #define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT   BIT(4)
0056 #define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT   BIT(8)
0057 #define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE     BIT(12)
0058 #define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT   BIT(16)
0059 #define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT   BIT(20)
0060 #define CCI_IRQ_STATUS_0_RST_DONE_ACK       BIT(24)
0061 #define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK   BIT(25)
0062 #define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK   BIT(26)
0063 #define CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR BIT(27)
0064 #define CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR BIT(28)
0065 #define CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR BIT(29)
0066 #define CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR BIT(30)
0067 #define CCI_IRQ_STATUS_0_I2C_M0_ERROR       0x18000ee6
0068 #define CCI_IRQ_STATUS_0_I2C_M1_ERROR       0x60ee6000
0069 
0070 #define CCI_TIMEOUT (msecs_to_jiffies(100))
0071 #define NUM_MASTERS 2
0072 #define NUM_QUEUES  2
0073 
0074 /* Max number of resources + 1 for a NULL terminator */
0075 #define CCI_RES_MAX 6
0076 
0077 #define CCI_I2C_SET_PARAM   1
0078 #define CCI_I2C_REPORT      8
0079 #define CCI_I2C_WRITE       9
0080 #define CCI_I2C_READ        10
0081 
0082 #define CCI_I2C_REPORT_IRQ_EN   BIT(8)
0083 
0084 enum {
0085     I2C_MODE_STANDARD,
0086     I2C_MODE_FAST,
0087     I2C_MODE_FAST_PLUS,
0088 };
0089 
0090 enum cci_i2c_queue_t {
0091     QUEUE_0,
0092     QUEUE_1
0093 };
0094 
0095 struct hw_params {
0096     u16 thigh; /* HIGH period of the SCL clock in clock ticks */
0097     u16 tlow; /* LOW period of the SCL clock */
0098     u16 tsu_sto; /* set-up time for STOP condition */
0099     u16 tsu_sta; /* set-up time for a repeated START condition */
0100     u16 thd_dat; /* data hold time */
0101     u16 thd_sta; /* hold time (repeated) START condition */
0102     u16 tbuf; /* bus free time between a STOP and START condition */
0103     u8 scl_stretch_en;
0104     u16 trdhld;
0105     u16 tsp; /* pulse width of spikes suppressed by the input filter */
0106 };
0107 
0108 struct cci;
0109 
0110 struct cci_master {
0111     struct i2c_adapter adap;
0112     u16 master;
0113     u8 mode;
0114     int status;
0115     struct completion irq_complete;
0116     struct cci *cci;
0117 };
0118 
0119 struct cci_data {
0120     unsigned int num_masters;
0121     struct i2c_adapter_quirks quirks;
0122     u16 queue_size[NUM_QUEUES];
0123     unsigned long cci_clk_rate;
0124     struct hw_params params[3];
0125 };
0126 
0127 struct cci {
0128     struct device *dev;
0129     void __iomem *base;
0130     unsigned int irq;
0131     const struct cci_data *data;
0132     struct clk_bulk_data *clocks;
0133     int nclocks;
0134     struct cci_master master[NUM_MASTERS];
0135 };
0136 
0137 static irqreturn_t cci_isr(int irq, void *dev)
0138 {
0139     struct cci *cci = dev;
0140     u32 val, reset = 0;
0141     int ret = IRQ_NONE;
0142 
0143     val = readl(cci->base + CCI_IRQ_STATUS_0);
0144     writel(val, cci->base + CCI_IRQ_CLEAR_0);
0145     writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD);
0146 
0147     if (val & CCI_IRQ_STATUS_0_RST_DONE_ACK) {
0148         complete(&cci->master[0].irq_complete);
0149         if (cci->master[1].master)
0150             complete(&cci->master[1].irq_complete);
0151         ret = IRQ_HANDLED;
0152     }
0153 
0154     if (val & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE ||
0155             val & CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT ||
0156             val & CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT) {
0157         cci->master[0].status = 0;
0158         complete(&cci->master[0].irq_complete);
0159         ret = IRQ_HANDLED;
0160     }
0161 
0162     if (val & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE ||
0163             val & CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT ||
0164             val & CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT) {
0165         cci->master[1].status = 0;
0166         complete(&cci->master[1].irq_complete);
0167         ret = IRQ_HANDLED;
0168     }
0169 
0170     if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK)) {
0171         reset = CCI_RESET_CMD_M0_MASK;
0172         ret = IRQ_HANDLED;
0173     }
0174 
0175     if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK)) {
0176         reset = CCI_RESET_CMD_M1_MASK;
0177         ret = IRQ_HANDLED;
0178     }
0179 
0180     if (unlikely(reset))
0181         writel(reset, cci->base + CCI_RESET_CMD);
0182 
0183     if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) {
0184         if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR ||
0185             val & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR)
0186             cci->master[0].status = -ENXIO;
0187         else
0188             cci->master[0].status = -EIO;
0189 
0190         writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ);
0191         ret = IRQ_HANDLED;
0192     }
0193 
0194     if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) {
0195         if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR ||
0196             val & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR)
0197             cci->master[1].status = -ENXIO;
0198         else
0199             cci->master[1].status = -EIO;
0200 
0201         writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ);
0202         ret = IRQ_HANDLED;
0203     }
0204 
0205     return ret;
0206 }
0207 
0208 static int cci_halt(struct cci *cci, u8 master_num)
0209 {
0210     struct cci_master *master;
0211     u32 val;
0212 
0213     if (master_num >= cci->data->num_masters) {
0214         dev_err(cci->dev, "Unsupported master idx (%u)\n", master_num);
0215         return -EINVAL;
0216     }
0217 
0218     val = BIT(master_num);
0219     master = &cci->master[master_num];
0220 
0221     reinit_completion(&master->irq_complete);
0222     writel(val, cci->base + CCI_HALT_REQ);
0223 
0224     if (!wait_for_completion_timeout(&master->irq_complete, CCI_TIMEOUT)) {
0225         dev_err(cci->dev, "CCI halt timeout\n");
0226         return -ETIMEDOUT;
0227     }
0228 
0229     return 0;
0230 }
0231 
0232 static int cci_reset(struct cci *cci)
0233 {
0234     /*
0235      * we reset the whole controller, here and for implicity use
0236      * master[0].xxx for waiting on it.
0237      */
0238     reinit_completion(&cci->master[0].irq_complete);
0239     writel(CCI_RESET_CMD_MASK, cci->base + CCI_RESET_CMD);
0240 
0241     if (!wait_for_completion_timeout(&cci->master[0].irq_complete,
0242                      CCI_TIMEOUT)) {
0243         dev_err(cci->dev, "CCI reset timeout\n");
0244         return -ETIMEDOUT;
0245     }
0246 
0247     return 0;
0248 }
0249 
0250 static int cci_init(struct cci *cci)
0251 {
0252     u32 val = CCI_IRQ_MASK_0_I2C_M0_RD_DONE |
0253             CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT |
0254             CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT |
0255             CCI_IRQ_MASK_0_I2C_M1_RD_DONE |
0256             CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT |
0257             CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT |
0258             CCI_IRQ_MASK_0_RST_DONE_ACK |
0259             CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK |
0260             CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK |
0261             CCI_IRQ_MASK_0_I2C_M0_ERROR |
0262             CCI_IRQ_MASK_0_I2C_M1_ERROR;
0263     int i;
0264 
0265     writel(val, cci->base + CCI_IRQ_MASK_0);
0266 
0267     for (i = 0; i < cci->data->num_masters; i++) {
0268         int mode = cci->master[i].mode;
0269         const struct hw_params *hw;
0270 
0271         if (!cci->master[i].cci)
0272             continue;
0273 
0274         hw = &cci->data->params[mode];
0275 
0276         val = hw->thigh << 16 | hw->tlow;
0277         writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));
0278 
0279         val = hw->tsu_sto << 16 | hw->tsu_sta;
0280         writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i));
0281 
0282         val = hw->thd_dat << 16 | hw->thd_sta;
0283         writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_1(i));
0284 
0285         val = hw->tbuf;
0286         writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i));
0287 
0288         val = hw->scl_stretch_en << 8 | hw->trdhld << 4 | hw->tsp;
0289         writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i));
0290     }
0291 
0292     return 0;
0293 }
0294 
0295 static int cci_run_queue(struct cci *cci, u8 master, u8 queue)
0296 {
0297     u32 val;
0298 
0299     val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
0300     writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue));
0301 
0302     reinit_completion(&cci->master[master].irq_complete);
0303     val = BIT(master * 2 + queue);
0304     writel(val, cci->base + CCI_QUEUE_START);
0305 
0306     if (!wait_for_completion_timeout(&cci->master[master].irq_complete,
0307                      CCI_TIMEOUT)) {
0308         dev_err(cci->dev, "master %d queue %d timeout\n",
0309             master, queue);
0310         cci_reset(cci);
0311         cci_init(cci);
0312         return -ETIMEDOUT;
0313     }
0314 
0315     return cci->master[master].status;
0316 }
0317 
0318 static int cci_validate_queue(struct cci *cci, u8 master, u8 queue)
0319 {
0320     u32 val;
0321 
0322     val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
0323     if (val == cci->data->queue_size[queue])
0324         return -EINVAL;
0325 
0326     if (!val)
0327         return 0;
0328 
0329     val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN;
0330     writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
0331 
0332     return cci_run_queue(cci, master, queue);
0333 }
0334 
0335 static int cci_i2c_read(struct cci *cci, u16 master,
0336             u16 addr, u8 *buf, u16 len)
0337 {
0338     u32 val, words_read, words_exp;
0339     u8 queue = QUEUE_1;
0340     int i, index = 0, ret;
0341     bool first = true;
0342 
0343     /*
0344      * Call validate queue to make sure queue is empty before starting.
0345      * This is to avoid overflow / underflow of queue.
0346      */
0347     ret = cci_validate_queue(cci, master, queue);
0348     if (ret < 0)
0349         return ret;
0350 
0351     val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4;
0352     writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
0353 
0354     val = CCI_I2C_READ | len << 4;
0355     writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
0356 
0357     ret = cci_run_queue(cci, master, queue);
0358     if (ret < 0)
0359         return ret;
0360 
0361     words_read = readl(cci->base + CCI_I2C_Mm_READ_BUF_LEVEL(master));
0362     words_exp = len / 4 + 1;
0363     if (words_read != words_exp) {
0364         dev_err(cci->dev, "words read = %d, words expected = %d\n",
0365             words_read, words_exp);
0366         return -EIO;
0367     }
0368 
0369     do {
0370         val = readl(cci->base + CCI_I2C_Mm_READ_DATA(master));
0371 
0372         for (i = 0; i < 4 && index < len; i++) {
0373             if (first) {
0374                 /* The LS byte of this register represents the
0375                  * first byte read from the slave during a read
0376                  * access.
0377                  */
0378                 first = false;
0379                 continue;
0380             }
0381             buf[index++] = (val >> (i * 8)) & 0xff;
0382         }
0383     } while (--words_read);
0384 
0385     return 0;
0386 }
0387 
0388 static int cci_i2c_write(struct cci *cci, u16 master,
0389              u16 addr, u8 *buf, u16 len)
0390 {
0391     u8 queue = QUEUE_0;
0392     u8 load[12] = { 0 };
0393     int i = 0, j, ret;
0394     u32 val;
0395 
0396     /*
0397      * Call validate queue to make sure queue is empty before starting.
0398      * This is to avoid overflow / underflow of queue.
0399      */
0400     ret = cci_validate_queue(cci, master, queue);
0401     if (ret < 0)
0402         return ret;
0403 
0404     val = CCI_I2C_SET_PARAM | (addr & 0x7f) << 4;
0405     writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
0406 
0407     load[i++] = CCI_I2C_WRITE | len << 4;
0408 
0409     for (j = 0; j < len; j++)
0410         load[i++] = buf[j];
0411 
0412     for (j = 0; j < i; j += 4) {
0413         val = load[j];
0414         val |= load[j + 1] << 8;
0415         val |= load[j + 2] << 16;
0416         val |= load[j + 3] << 24;
0417         writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
0418     }
0419 
0420     val = CCI_I2C_REPORT | CCI_I2C_REPORT_IRQ_EN;
0421     writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
0422 
0423     return cci_run_queue(cci, master, queue);
0424 }
0425 
0426 static int cci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
0427 {
0428     struct cci_master *cci_master = i2c_get_adapdata(adap);
0429     struct cci *cci = cci_master->cci;
0430     int i, ret;
0431 
0432     ret = pm_runtime_get_sync(cci->dev);
0433     if (ret < 0)
0434         goto err;
0435 
0436     for (i = 0; i < num; i++) {
0437         if (msgs[i].flags & I2C_M_RD)
0438             ret = cci_i2c_read(cci, cci_master->master,
0439                        msgs[i].addr, msgs[i].buf,
0440                        msgs[i].len);
0441         else
0442             ret = cci_i2c_write(cci, cci_master->master,
0443                         msgs[i].addr, msgs[i].buf,
0444                         msgs[i].len);
0445 
0446         if (ret < 0)
0447             break;
0448     }
0449 
0450     if (!ret)
0451         ret = num;
0452 
0453 err:
0454     pm_runtime_mark_last_busy(cci->dev);
0455     pm_runtime_put_autosuspend(cci->dev);
0456 
0457     return ret;
0458 }
0459 
0460 static u32 cci_func(struct i2c_adapter *adap)
0461 {
0462     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0463 }
0464 
0465 static const struct i2c_algorithm cci_algo = {
0466     .master_xfer    = cci_xfer,
0467     .functionality  = cci_func,
0468 };
0469 
0470 static int cci_enable_clocks(struct cci *cci)
0471 {
0472     return clk_bulk_prepare_enable(cci->nclocks, cci->clocks);
0473 }
0474 
0475 static void cci_disable_clocks(struct cci *cci)
0476 {
0477     clk_bulk_disable_unprepare(cci->nclocks, cci->clocks);
0478 }
0479 
0480 static int __maybe_unused cci_suspend_runtime(struct device *dev)
0481 {
0482     struct cci *cci = dev_get_drvdata(dev);
0483 
0484     cci_disable_clocks(cci);
0485     return 0;
0486 }
0487 
0488 static int __maybe_unused cci_resume_runtime(struct device *dev)
0489 {
0490     struct cci *cci = dev_get_drvdata(dev);
0491     int ret;
0492 
0493     ret = cci_enable_clocks(cci);
0494     if (ret)
0495         return ret;
0496 
0497     cci_init(cci);
0498     return 0;
0499 }
0500 
0501 static int __maybe_unused cci_suspend(struct device *dev)
0502 {
0503     if (!pm_runtime_suspended(dev))
0504         return cci_suspend_runtime(dev);
0505 
0506     return 0;
0507 }
0508 
0509 static int __maybe_unused cci_resume(struct device *dev)
0510 {
0511     cci_resume_runtime(dev);
0512     pm_runtime_mark_last_busy(dev);
0513     pm_request_autosuspend(dev);
0514 
0515     return 0;
0516 }
0517 
0518 static const struct dev_pm_ops qcom_cci_pm = {
0519     SET_SYSTEM_SLEEP_PM_OPS(cci_suspend, cci_resume)
0520     SET_RUNTIME_PM_OPS(cci_suspend_runtime, cci_resume_runtime, NULL)
0521 };
0522 
0523 static int cci_probe(struct platform_device *pdev)
0524 {
0525     struct device *dev = &pdev->dev;
0526     unsigned long cci_clk_rate = 0;
0527     struct device_node *child;
0528     struct resource *r;
0529     struct cci *cci;
0530     int ret, i;
0531     u32 val;
0532 
0533     cci = devm_kzalloc(dev, sizeof(*cci), GFP_KERNEL);
0534     if (!cci)
0535         return -ENOMEM;
0536 
0537     cci->dev = dev;
0538     platform_set_drvdata(pdev, cci);
0539     cci->data = device_get_match_data(dev);
0540     if (!cci->data)
0541         return -ENOENT;
0542 
0543     for_each_available_child_of_node(dev->of_node, child) {
0544         struct cci_master *master;
0545         u32 idx;
0546 
0547         ret = of_property_read_u32(child, "reg", &idx);
0548         if (ret) {
0549             dev_err(dev, "%pOF invalid 'reg' property", child);
0550             continue;
0551         }
0552 
0553         if (idx >= cci->data->num_masters) {
0554             dev_err(dev, "%pOF invalid 'reg' value: %u (max is %u)",
0555                 child, idx, cci->data->num_masters - 1);
0556             continue;
0557         }
0558 
0559         master = &cci->master[idx];
0560         master->adap.quirks = &cci->data->quirks;
0561         master->adap.algo = &cci_algo;
0562         master->adap.dev.parent = dev;
0563         master->adap.dev.of_node = of_node_get(child);
0564         master->master = idx;
0565         master->cci = cci;
0566 
0567         i2c_set_adapdata(&master->adap, master);
0568         snprintf(master->adap.name, sizeof(master->adap.name), "Qualcomm-CCI");
0569 
0570         master->mode = I2C_MODE_STANDARD;
0571         ret = of_property_read_u32(child, "clock-frequency", &val);
0572         if (!ret) {
0573             if (val == I2C_MAX_FAST_MODE_FREQ)
0574                 master->mode = I2C_MODE_FAST;
0575             else if (val == I2C_MAX_FAST_MODE_PLUS_FREQ)
0576                 master->mode = I2C_MODE_FAST_PLUS;
0577         }
0578 
0579         init_completion(&master->irq_complete);
0580     }
0581 
0582     /* Memory */
0583 
0584     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0585     cci->base = devm_ioremap_resource(dev, r);
0586     if (IS_ERR(cci->base))
0587         return PTR_ERR(cci->base);
0588 
0589     /* Clocks */
0590 
0591     ret = devm_clk_bulk_get_all(dev, &cci->clocks);
0592     if (ret < 1) {
0593         dev_err(dev, "failed to get clocks %d\n", ret);
0594         return ret;
0595     }
0596     cci->nclocks = ret;
0597 
0598     /* Retrieve CCI clock rate */
0599     for (i = 0; i < cci->nclocks; i++) {
0600         if (!strcmp(cci->clocks[i].id, "cci")) {
0601             cci_clk_rate = clk_get_rate(cci->clocks[i].clk);
0602             break;
0603         }
0604     }
0605 
0606     if (cci_clk_rate != cci->data->cci_clk_rate) {
0607         /* cci clock set by the bootloader or via assigned clock rate
0608          * in DT.
0609          */
0610         dev_warn(dev, "Found %lu cci clk rate while %lu was expected\n",
0611              cci_clk_rate, cci->data->cci_clk_rate);
0612     }
0613 
0614     ret = cci_enable_clocks(cci);
0615     if (ret < 0)
0616         return ret;
0617 
0618     /* Interrupt */
0619 
0620     ret = platform_get_irq(pdev, 0);
0621     if (ret < 0)
0622         goto disable_clocks;
0623     cci->irq = ret;
0624 
0625     ret = devm_request_irq(dev, cci->irq, cci_isr, 0, dev_name(dev), cci);
0626     if (ret < 0) {
0627         dev_err(dev, "request_irq failed, ret: %d\n", ret);
0628         goto disable_clocks;
0629     }
0630 
0631     val = readl(cci->base + CCI_HW_VERSION);
0632     dev_dbg(dev, "CCI HW version = 0x%08x", val);
0633 
0634     ret = cci_reset(cci);
0635     if (ret < 0)
0636         goto error;
0637 
0638     ret = cci_init(cci);
0639     if (ret < 0)
0640         goto error;
0641 
0642     for (i = 0; i < cci->data->num_masters; i++) {
0643         if (!cci->master[i].cci)
0644             continue;
0645 
0646         ret = i2c_add_adapter(&cci->master[i].adap);
0647         if (ret < 0) {
0648             of_node_put(cci->master[i].adap.dev.of_node);
0649             goto error_i2c;
0650         }
0651     }
0652 
0653     pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
0654     pm_runtime_use_autosuspend(dev);
0655     pm_runtime_set_active(dev);
0656     pm_runtime_enable(dev);
0657 
0658     return 0;
0659 
0660 error_i2c:
0661     for (--i ; i >= 0; i--) {
0662         if (cci->master[i].cci) {
0663             i2c_del_adapter(&cci->master[i].adap);
0664             of_node_put(cci->master[i].adap.dev.of_node);
0665         }
0666     }
0667 error:
0668     disable_irq(cci->irq);
0669 disable_clocks:
0670     cci_disable_clocks(cci);
0671 
0672     return ret;
0673 }
0674 
0675 static int cci_remove(struct platform_device *pdev)
0676 {
0677     struct cci *cci = platform_get_drvdata(pdev);
0678     int i;
0679 
0680     for (i = 0; i < cci->data->num_masters; i++) {
0681         if (cci->master[i].cci) {
0682             i2c_del_adapter(&cci->master[i].adap);
0683             of_node_put(cci->master[i].adap.dev.of_node);
0684         }
0685         cci_halt(cci, i);
0686     }
0687 
0688     disable_irq(cci->irq);
0689     pm_runtime_disable(&pdev->dev);
0690     pm_runtime_set_suspended(&pdev->dev);
0691 
0692     return 0;
0693 }
0694 
0695 static const struct cci_data cci_v1_data = {
0696     .num_masters = 1,
0697     .queue_size = { 64, 16 },
0698     .quirks = {
0699         .max_write_len = 10,
0700         .max_read_len = 12,
0701     },
0702     .cci_clk_rate =  19200000,
0703     .params[I2C_MODE_STANDARD] = {
0704         .thigh = 78,
0705         .tlow = 114,
0706         .tsu_sto = 28,
0707         .tsu_sta = 28,
0708         .thd_dat = 10,
0709         .thd_sta = 77,
0710         .tbuf = 118,
0711         .scl_stretch_en = 0,
0712         .trdhld = 6,
0713         .tsp = 1
0714     },
0715     .params[I2C_MODE_FAST] = {
0716         .thigh = 20,
0717         .tlow = 28,
0718         .tsu_sto = 21,
0719         .tsu_sta = 21,
0720         .thd_dat = 13,
0721         .thd_sta = 18,
0722         .tbuf = 32,
0723         .scl_stretch_en = 0,
0724         .trdhld = 6,
0725         .tsp = 3
0726     },
0727 };
0728 
0729 static const struct cci_data cci_v1_5_data = {
0730     .num_masters = 2,
0731     .queue_size = { 64, 16 },
0732     .quirks = {
0733         .max_write_len = 10,
0734         .max_read_len = 12,
0735     },
0736     .cci_clk_rate =  19200000,
0737     .params[I2C_MODE_STANDARD] = {
0738         .thigh = 78,
0739         .tlow = 114,
0740         .tsu_sto = 28,
0741         .tsu_sta = 28,
0742         .thd_dat = 10,
0743         .thd_sta = 77,
0744         .tbuf = 118,
0745         .scl_stretch_en = 0,
0746         .trdhld = 6,
0747         .tsp = 1
0748     },
0749     .params[I2C_MODE_FAST] = {
0750         .thigh = 20,
0751         .tlow = 28,
0752         .tsu_sto = 21,
0753         .tsu_sta = 21,
0754         .thd_dat = 13,
0755         .thd_sta = 18,
0756         .tbuf = 32,
0757         .scl_stretch_en = 0,
0758         .trdhld = 6,
0759         .tsp = 3
0760     },
0761 };
0762 
0763 static const struct cci_data cci_v2_data = {
0764     .num_masters = 2,
0765     .queue_size = { 64, 16 },
0766     .quirks = {
0767         .max_write_len = 11,
0768         .max_read_len = 12,
0769     },
0770     .cci_clk_rate =  37500000,
0771     .params[I2C_MODE_STANDARD] = {
0772         .thigh = 201,
0773         .tlow = 174,
0774         .tsu_sto = 204,
0775         .tsu_sta = 231,
0776         .thd_dat = 22,
0777         .thd_sta = 162,
0778         .tbuf = 227,
0779         .scl_stretch_en = 0,
0780         .trdhld = 6,
0781         .tsp = 3
0782     },
0783     .params[I2C_MODE_FAST] = {
0784         .thigh = 38,
0785         .tlow = 56,
0786         .tsu_sto = 40,
0787         .tsu_sta = 40,
0788         .thd_dat = 22,
0789         .thd_sta = 35,
0790         .tbuf = 62,
0791         .scl_stretch_en = 0,
0792         .trdhld = 6,
0793         .tsp = 3
0794     },
0795     .params[I2C_MODE_FAST_PLUS] = {
0796         .thigh = 16,
0797         .tlow = 22,
0798         .tsu_sto = 17,
0799         .tsu_sta = 18,
0800         .thd_dat = 16,
0801         .thd_sta = 15,
0802         .tbuf = 24,
0803         .scl_stretch_en = 0,
0804         .trdhld = 3,
0805         .tsp = 3
0806     },
0807 };
0808 
0809 static const struct of_device_id cci_dt_match[] = {
0810     { .compatible = "qcom,msm8916-cci", .data = &cci_v1_data},
0811     { .compatible = "qcom,msm8974-cci", .data = &cci_v1_5_data},
0812     { .compatible = "qcom,msm8996-cci", .data = &cci_v2_data},
0813     { .compatible = "qcom,sdm845-cci", .data = &cci_v2_data},
0814     { .compatible = "qcom,sm8250-cci", .data = &cci_v2_data},
0815     { .compatible = "qcom,sm8450-cci", .data = &cci_v2_data},
0816     {}
0817 };
0818 MODULE_DEVICE_TABLE(of, cci_dt_match);
0819 
0820 static struct platform_driver qcom_cci_driver = {
0821     .probe  = cci_probe,
0822     .remove = cci_remove,
0823     .driver = {
0824         .name = "i2c-qcom-cci",
0825         .of_match_table = cci_dt_match,
0826         .pm = &qcom_cci_pm,
0827     },
0828 };
0829 
0830 module_platform_driver(qcom_cci_driver);
0831 
0832 MODULE_DESCRIPTION("Qualcomm Camera Control Interface driver");
0833 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
0834 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>");
0835 MODULE_LICENSE("GPL v2");
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