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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  i2c_adap_pxa.c
0004  *
0005  *  I2C adapter for the PXA I2C bus access.
0006  *
0007  *  Copyright (C) 2002 Intrinsyc Software Inc.
0008  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
0009  *
0010  *  History:
0011  *    Apr 2002: Initial version [CS]
0012  *    Jun 2002: Properly separated algo/adap [FB]
0013  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
0014  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
0015  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
0016  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
0017  *    Feb 2005: Rework slave mode handling [RMK]
0018  */
0019 #include <linux/clk.h>
0020 #include <linux/delay.h>
0021 #include <linux/err.h>
0022 #include <linux/errno.h>
0023 #include <linux/gpio/consumer.h>
0024 #include <linux/i2c.h>
0025 #include <linux/init.h>
0026 #include <linux/interrupt.h>
0027 #include <linux/io.h>
0028 #include <linux/kernel.h>
0029 #include <linux/module.h>
0030 #include <linux/of.h>
0031 #include <linux/of_device.h>
0032 #include <linux/pinctrl/consumer.h>
0033 #include <linux/platform_device.h>
0034 #include <linux/platform_data/i2c-pxa.h>
0035 #include <linux/slab.h>
0036 
0037 /* I2C register field definitions */
0038 #define IBMR_SDAS   (1 << 0)
0039 #define IBMR_SCLS   (1 << 1)
0040 
0041 #define ICR_START   (1 << 0)       /* start bit */
0042 #define ICR_STOP    (1 << 1)       /* stop bit */
0043 #define ICR_ACKNAK  (1 << 2)       /* send ACK(0) or NAK(1) */
0044 #define ICR_TB      (1 << 3)       /* transfer byte bit */
0045 #define ICR_MA      (1 << 4)       /* master abort */
0046 #define ICR_SCLE    (1 << 5)       /* master clock enable */
0047 #define ICR_IUE     (1 << 6)       /* unit enable */
0048 #define ICR_GCD     (1 << 7)       /* general call disable */
0049 #define ICR_ITEIE   (1 << 8)       /* enable tx interrupts */
0050 #define ICR_IRFIE   (1 << 9)       /* enable rx interrupts */
0051 #define ICR_BEIE    (1 << 10)      /* enable bus error ints */
0052 #define ICR_SSDIE   (1 << 11)      /* slave STOP detected int enable */
0053 #define ICR_ALDIE   (1 << 12)      /* enable arbitration interrupt */
0054 #define ICR_SADIE   (1 << 13)      /* slave address detected int enable */
0055 #define ICR_UR      (1 << 14)      /* unit reset */
0056 #define ICR_FM      (1 << 15)      /* fast mode */
0057 #define ICR_HS      (1 << 16)      /* High Speed mode */
0058 #define ICR_A3700_FM    (1 << 16)      /* fast mode for armada-3700 */
0059 #define ICR_A3700_HS    (1 << 17)      /* high speed mode for armada-3700 */
0060 #define ICR_GPIOEN  (1 << 19)      /* enable GPIO mode for SCL in HS */
0061 
0062 #define ISR_RWM     (1 << 0)       /* read/write mode */
0063 #define ISR_ACKNAK  (1 << 1)       /* ack/nak status */
0064 #define ISR_UB      (1 << 2)       /* unit busy */
0065 #define ISR_IBB     (1 << 3)       /* bus busy */
0066 #define ISR_SSD     (1 << 4)       /* slave stop detected */
0067 #define ISR_ALD     (1 << 5)       /* arbitration loss detected */
0068 #define ISR_ITE     (1 << 6)       /* tx buffer empty */
0069 #define ISR_IRF     (1 << 7)       /* rx buffer full */
0070 #define ISR_GCAD    (1 << 8)       /* general call address detected */
0071 #define ISR_SAD     (1 << 9)       /* slave address detected */
0072 #define ISR_BED     (1 << 10)      /* bus error no ACK/NAK */
0073 
0074 #define ILCR_SLV_SHIFT      0
0075 #define ILCR_SLV_MASK       (0x1FF << ILCR_SLV_SHIFT)
0076 #define ILCR_FLV_SHIFT      9
0077 #define ILCR_FLV_MASK       (0x1FF << ILCR_FLV_SHIFT)
0078 #define ILCR_HLVL_SHIFT     18
0079 #define ILCR_HLVL_MASK      (0x1FF << ILCR_HLVL_SHIFT)
0080 #define ILCR_HLVH_SHIFT     27
0081 #define ILCR_HLVH_MASK      (0x1F << ILCR_HLVH_SHIFT)
0082 
0083 #define IWCR_CNT_SHIFT      0
0084 #define IWCR_CNT_MASK       (0x1F << IWCR_CNT_SHIFT)
0085 #define IWCR_HS_CNT1_SHIFT  5
0086 #define IWCR_HS_CNT1_MASK   (0x1F << IWCR_HS_CNT1_SHIFT)
0087 #define IWCR_HS_CNT2_SHIFT  10
0088 #define IWCR_HS_CNT2_MASK   (0x1F << IWCR_HS_CNT2_SHIFT)
0089 
0090 /* need a longer timeout if we're dealing with the fact we may well be
0091  * looking at a multi-master environment
0092  */
0093 #define DEF_TIMEOUT             32
0094 
0095 #define NO_SLAVE        (-ENXIO)
0096 #define BUS_ERROR               (-EREMOTEIO)
0097 #define XFER_NAKED              (-ECONNREFUSED)
0098 #define I2C_RETRY               (-2000) /* an error has occurred retry transmit */
0099 
0100 /* ICR initialize bit values
0101  *
0102  * 15 FM     0 (100 kHz operation)
0103  * 14 UR     0 (No unit reset)
0104  * 13 SADIE  0 (Disables the unit from interrupting on slave addresses
0105  *              matching its slave address)
0106  * 12 ALDIE  0 (Disables the unit from interrupt when it loses arbitration
0107  *              in master mode)
0108  * 11 SSDIE  0 (Disables interrupts from a slave stop detected, in slave mode)
0109  * 10 BEIE   1 (Enable interrupts from detected bus errors, no ACK sent)
0110  *  9 IRFIE  1 (Enable interrupts from full buffer received)
0111  *  8 ITEIE  1 (Enables the I2C unit to interrupt when transmit buffer empty)
0112  *  7 GCD    1 (Disables i2c unit response to general call messages as a slave)
0113  *  6 IUE    0 (Disable unit until we change settings)
0114  *  5 SCLE   1 (Enables the i2c clock output for master mode (drives SCL)
0115  *  4 MA     0 (Only send stop with the ICR stop bit)
0116  *  3 TB     0 (We are not transmitting a byte initially)
0117  *  2 ACKNAK 0 (Send an ACK after the unit receives a byte)
0118  *  1 STOP   0 (Do not send a STOP)
0119  *  0 START  0 (Do not send a START)
0120  */
0121 #define I2C_ICR_INIT    (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
0122 
0123 /* I2C status register init values
0124  *
0125  * 10 BED    1 (Clear bus error detected)
0126  *  9 SAD    1 (Clear slave address detected)
0127  *  7 IRF    1 (Clear IDBR Receive Full)
0128  *  6 ITE    1 (Clear IDBR Transmit Empty)
0129  *  5 ALD    1 (Clear Arbitration Loss Detected)
0130  *  4 SSD    1 (Clear Slave Stop Detected)
0131  */
0132 #define I2C_ISR_INIT    0x7FF  /* status register init */
0133 
0134 struct pxa_reg_layout {
0135     u32 ibmr;
0136     u32 idbr;
0137     u32 icr;
0138     u32 isr;
0139     u32 isar;
0140     u32 ilcr;
0141     u32 iwcr;
0142     u32 fm;
0143     u32 hs;
0144 };
0145 
0146 enum pxa_i2c_types {
0147     REGS_PXA2XX,
0148     REGS_PXA3XX,
0149     REGS_CE4100,
0150     REGS_PXA910,
0151     REGS_A3700,
0152 };
0153 
0154 /* I2C register layout definitions */
0155 static struct pxa_reg_layout pxa_reg_layout[] = {
0156     [REGS_PXA2XX] = {
0157         .ibmr = 0x00,
0158         .idbr = 0x08,
0159         .icr =  0x10,
0160         .isr =  0x18,
0161         .isar = 0x20,
0162         .fm = ICR_FM,
0163         .hs = ICR_HS,
0164     },
0165     [REGS_PXA3XX] = {
0166         .ibmr = 0x00,
0167         .idbr = 0x04,
0168         .icr =  0x08,
0169         .isr =  0x0c,
0170         .isar = 0x10,
0171         .fm = ICR_FM,
0172         .hs = ICR_HS,
0173     },
0174     [REGS_CE4100] = {
0175         .ibmr = 0x14,
0176         .idbr = 0x0c,
0177         .icr =  0x00,
0178         .isr =  0x04,
0179         /* no isar register */
0180         .fm = ICR_FM,
0181         .hs = ICR_HS,
0182     },
0183     [REGS_PXA910] = {
0184         .ibmr = 0x00,
0185         .idbr = 0x08,
0186         .icr =  0x10,
0187         .isr =  0x18,
0188         .isar = 0x20,
0189         .ilcr = 0x28,
0190         .iwcr = 0x30,
0191         .fm = ICR_FM,
0192         .hs = ICR_HS,
0193     },
0194     [REGS_A3700] = {
0195         .ibmr = 0x00,
0196         .idbr = 0x04,
0197         .icr =  0x08,
0198         .isr =  0x0c,
0199         .isar = 0x10,
0200         .fm = ICR_A3700_FM,
0201         .hs = ICR_A3700_HS,
0202     },
0203 };
0204 
0205 static const struct of_device_id i2c_pxa_dt_ids[] = {
0206     { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
0207     { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
0208     { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
0209     { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
0210     {}
0211 };
0212 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
0213 
0214 static const struct platform_device_id i2c_pxa_id_table[] = {
0215     { "pxa2xx-i2c",     REGS_PXA2XX },
0216     { "pxa3xx-pwri2c",  REGS_PXA3XX },
0217     { "ce4100-i2c",     REGS_CE4100 },
0218     { "pxa910-i2c",     REGS_PXA910 },
0219     { "armada-3700-i2c",    REGS_A3700  },
0220     { },
0221 };
0222 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
0223 
0224 struct pxa_i2c {
0225     spinlock_t      lock;
0226     wait_queue_head_t   wait;
0227     struct i2c_msg      *msg;
0228     unsigned int        msg_num;
0229     unsigned int        msg_idx;
0230     unsigned int        msg_ptr;
0231     unsigned int        slave_addr;
0232     unsigned int        req_slave_addr;
0233 
0234     struct i2c_adapter  adap;
0235     struct clk      *clk;
0236 #ifdef CONFIG_I2C_PXA_SLAVE
0237     struct i2c_client   *slave;
0238 #endif
0239 
0240     unsigned int        irqlogidx;
0241     u32         isrlog[32];
0242     u32         icrlog[32];
0243 
0244     void __iomem        *reg_base;
0245     void __iomem        *reg_ibmr;
0246     void __iomem        *reg_idbr;
0247     void __iomem        *reg_icr;
0248     void __iomem        *reg_isr;
0249     void __iomem        *reg_isar;
0250     void __iomem        *reg_ilcr;
0251     void __iomem        *reg_iwcr;
0252 
0253     unsigned long       iobase;
0254     unsigned long       iosize;
0255 
0256     int         irq;
0257     unsigned int        use_pio :1;
0258     unsigned int        fast_mode :1;
0259     unsigned int        high_mode:1;
0260     unsigned char       master_code;
0261     unsigned long       rate;
0262     bool            highmode_enter;
0263     u32         fm_mask;
0264     u32         hs_mask;
0265 
0266     struct i2c_bus_recovery_info recovery;
0267 };
0268 
0269 #define _IBMR(i2c)  ((i2c)->reg_ibmr)
0270 #define _IDBR(i2c)  ((i2c)->reg_idbr)
0271 #define _ICR(i2c)   ((i2c)->reg_icr)
0272 #define _ISR(i2c)   ((i2c)->reg_isr)
0273 #define _ISAR(i2c)  ((i2c)->reg_isar)
0274 #define _ILCR(i2c)  ((i2c)->reg_ilcr)
0275 #define _IWCR(i2c)  ((i2c)->reg_iwcr)
0276 
0277 /*
0278  * I2C Slave mode address
0279  */
0280 #define I2C_PXA_SLAVE_ADDR      0x1
0281 
0282 #ifdef DEBUG
0283 
0284 struct bits {
0285     u32 mask;
0286     const char *set;
0287     const char *unset;
0288 };
0289 #define PXA_BIT(m, s, u)    { .mask = m, .set = s, .unset = u }
0290 
0291 static inline void
0292 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
0293 {
0294     printk("%s %08x:", prefix, val);
0295     while (num--) {
0296         const char *str = val & bits->mask ? bits->set : bits->unset;
0297         if (str)
0298             pr_cont(" %s", str);
0299         bits++;
0300     }
0301     pr_cont("\n");
0302 }
0303 
0304 static const struct bits isr_bits[] = {
0305     PXA_BIT(ISR_RWM,    "RX",       "TX"),
0306     PXA_BIT(ISR_ACKNAK, "NAK",      "ACK"),
0307     PXA_BIT(ISR_UB,     "Bsy",      "Rdy"),
0308     PXA_BIT(ISR_IBB,    "BusBsy",   "BusRdy"),
0309     PXA_BIT(ISR_SSD,    "SlaveStop",    NULL),
0310     PXA_BIT(ISR_ALD,    "ALD",      NULL),
0311     PXA_BIT(ISR_ITE,    "TxEmpty",  NULL),
0312     PXA_BIT(ISR_IRF,    "RxFull",   NULL),
0313     PXA_BIT(ISR_GCAD,   "GenCall",  NULL),
0314     PXA_BIT(ISR_SAD,    "SlaveAddr",    NULL),
0315     PXA_BIT(ISR_BED,    "BusErr",   NULL),
0316 };
0317 
0318 static void decode_ISR(unsigned int val)
0319 {
0320     decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
0321 }
0322 
0323 static const struct bits icr_bits[] = {
0324     PXA_BIT(ICR_START,  "START",    NULL),
0325     PXA_BIT(ICR_STOP,   "STOP", NULL),
0326     PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
0327     PXA_BIT(ICR_TB,     "TB",   NULL),
0328     PXA_BIT(ICR_MA,     "MA",   NULL),
0329     PXA_BIT(ICR_SCLE,   "SCLE", "scle"),
0330     PXA_BIT(ICR_IUE,    "IUE",  "iue"),
0331     PXA_BIT(ICR_GCD,    "GCD",  NULL),
0332     PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
0333     PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
0334     PXA_BIT(ICR_BEIE,   "BEIE", NULL),
0335     PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
0336     PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
0337     PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
0338     PXA_BIT(ICR_UR,     "UR",       "ur"),
0339 };
0340 
0341 #ifdef CONFIG_I2C_PXA_SLAVE
0342 static void decode_ICR(unsigned int val)
0343 {
0344     decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
0345 }
0346 #endif
0347 
0348 static unsigned int i2c_debug = DEBUG;
0349 
0350 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
0351 {
0352     dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
0353         readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
0354 }
0355 
0356 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
0357 
0358 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
0359 {
0360     unsigned int i;
0361     struct device *dev = &i2c->adap.dev;
0362 
0363     dev_err(dev, "slave_0x%x error: %s\n",
0364         i2c->req_slave_addr >> 1, why);
0365     dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
0366         i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
0367     dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
0368         readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
0369         readl(_ISR(i2c)));
0370     dev_err(dev, "log:");
0371     for (i = 0; i < i2c->irqlogidx; i++)
0372         pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
0373     pr_cont("\n");
0374 }
0375 
0376 #else /* ifdef DEBUG */
0377 
0378 #define i2c_debug   0
0379 
0380 #define show_state(i2c) do { } while (0)
0381 #define decode_ISR(val) do { } while (0)
0382 #define decode_ICR(val) do { } while (0)
0383 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
0384 
0385 #endif /* ifdef DEBUG / else */
0386 
0387 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
0388 
0389 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
0390 {
0391     return !(readl(_ICR(i2c)) & ICR_SCLE);
0392 }
0393 
0394 static void i2c_pxa_abort(struct pxa_i2c *i2c)
0395 {
0396     int i = 250;
0397 
0398     if (i2c_pxa_is_slavemode(i2c)) {
0399         dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
0400         return;
0401     }
0402 
0403     while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
0404         unsigned long icr = readl(_ICR(i2c));
0405 
0406         icr &= ~ICR_START;
0407         icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
0408 
0409         writel(icr, _ICR(i2c));
0410 
0411         show_state(i2c);
0412 
0413         mdelay(1);
0414         i --;
0415     }
0416 
0417     writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
0418            _ICR(i2c));
0419 }
0420 
0421 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
0422 {
0423     int timeout = DEF_TIMEOUT;
0424     u32 isr;
0425 
0426     while (1) {
0427         isr = readl(_ISR(i2c));
0428         if (!(isr & (ISR_IBB | ISR_UB)))
0429             return 0;
0430 
0431         if (isr & ISR_SAD)
0432             timeout += 4;
0433 
0434         if (!timeout--)
0435             break;
0436 
0437         msleep(2);
0438         show_state(i2c);
0439     }
0440 
0441     show_state(i2c);
0442 
0443     return I2C_RETRY;
0444 }
0445 
0446 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
0447 {
0448     unsigned long timeout = jiffies + HZ*4;
0449 
0450     while (time_before(jiffies, timeout)) {
0451         if (i2c_debug > 1)
0452             dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
0453                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
0454 
0455         if (readl(_ISR(i2c)) & ISR_SAD) {
0456             if (i2c_debug > 0)
0457                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
0458             goto out;
0459         }
0460 
0461         /* wait for unit and bus being not busy, and we also do a
0462          * quick check of the i2c lines themselves to ensure they've
0463          * gone high...
0464          */
0465         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
0466             readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
0467             if (i2c_debug > 0)
0468                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
0469             return 1;
0470         }
0471 
0472         msleep(1);
0473     }
0474 
0475     if (i2c_debug > 0)
0476         dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
0477  out:
0478     return 0;
0479 }
0480 
0481 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
0482 {
0483     if (i2c_debug)
0484         dev_dbg(&i2c->adap.dev, "setting to bus master\n");
0485 
0486     if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
0487         dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
0488         if (!i2c_pxa_wait_master(i2c)) {
0489             dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
0490             return I2C_RETRY;
0491         }
0492     }
0493 
0494     writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
0495     return 0;
0496 }
0497 
0498 #ifdef CONFIG_I2C_PXA_SLAVE
0499 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
0500 {
0501     unsigned long timeout = jiffies + HZ*1;
0502 
0503     /* wait for stop */
0504 
0505     show_state(i2c);
0506 
0507     while (time_before(jiffies, timeout)) {
0508         if (i2c_debug > 1)
0509             dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
0510                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
0511 
0512         if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
0513             (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
0514             (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
0515             if (i2c_debug > 1)
0516                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
0517             return 1;
0518         }
0519 
0520         msleep(1);
0521     }
0522 
0523     if (i2c_debug > 0)
0524         dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
0525     return 0;
0526 }
0527 
0528 /*
0529  * clear the hold on the bus, and take of anything else
0530  * that has been configured
0531  */
0532 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
0533 {
0534     show_state(i2c);
0535 
0536     if (errcode < 0) {
0537         udelay(100);   /* simple delay */
0538     } else {
0539         /* we need to wait for the stop condition to end */
0540 
0541         /* if we where in stop, then clear... */
0542         if (readl(_ICR(i2c)) & ICR_STOP) {
0543             udelay(100);
0544             writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
0545         }
0546 
0547         if (!i2c_pxa_wait_slave(i2c)) {
0548             dev_err(&i2c->adap.dev, "%s: wait timedout\n",
0549                 __func__);
0550             return;
0551         }
0552     }
0553 
0554     writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
0555     writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
0556 
0557     if (i2c_debug) {
0558         dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
0559         decode_ICR(readl(_ICR(i2c)));
0560     }
0561 }
0562 #else
0563 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
0564 #endif
0565 
0566 static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
0567 {
0568     /* reset according to 9.8 */
0569     writel(ICR_UR, _ICR(i2c));
0570     writel(I2C_ISR_INIT, _ISR(i2c));
0571     writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
0572 
0573     if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
0574         writel(i2c->slave_addr, _ISAR(i2c));
0575 
0576     /* set control register values */
0577     writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
0578     writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
0579 
0580 #ifdef CONFIG_I2C_PXA_SLAVE
0581     dev_info(&i2c->adap.dev, "Enabling slave mode\n");
0582     writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
0583 #endif
0584 
0585     i2c_pxa_set_slave(i2c, 0);
0586 }
0587 
0588 static void i2c_pxa_enable(struct pxa_i2c *i2c)
0589 {
0590     /* enable unit */
0591     writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
0592     udelay(100);
0593 }
0594 
0595 static void i2c_pxa_reset(struct pxa_i2c *i2c)
0596 {
0597     pr_debug("Resetting I2C Controller Unit\n");
0598 
0599     /* abort any transfer currently under way */
0600     i2c_pxa_abort(i2c);
0601     i2c_pxa_do_reset(i2c);
0602     i2c_pxa_enable(i2c);
0603 }
0604 
0605 
0606 #ifdef CONFIG_I2C_PXA_SLAVE
0607 /*
0608  * PXA I2C Slave mode
0609  */
0610 
0611 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
0612 {
0613     if (isr & ISR_BED) {
0614         /* what should we do here? */
0615     } else {
0616         u8 byte = 0;
0617 
0618         if (i2c->slave != NULL)
0619             i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED,
0620                     &byte);
0621 
0622         writel(byte, _IDBR(i2c));
0623         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
0624     }
0625 }
0626 
0627 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
0628 {
0629     u8 byte = readl(_IDBR(i2c));
0630 
0631     if (i2c->slave != NULL)
0632         i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte);
0633 
0634     writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
0635 }
0636 
0637 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
0638 {
0639     int timeout;
0640 
0641     if (i2c_debug > 0)
0642         dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
0643                (isr & ISR_RWM) ? 'r' : 't');
0644 
0645     if (i2c->slave != NULL) {
0646         if (isr & ISR_RWM) {
0647             u8 byte = 0;
0648 
0649             i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED,
0650                     &byte);
0651             writel(byte, _IDBR(i2c));
0652         } else {
0653             i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED,
0654                     NULL);
0655         }
0656     }
0657 
0658     /*
0659      * slave could interrupt in the middle of us generating a
0660      * start condition... if this happens, we'd better back off
0661      * and stop holding the poor thing up
0662      */
0663     writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
0664     writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
0665 
0666     timeout = 0x10000;
0667 
0668     while (1) {
0669         if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
0670             break;
0671 
0672         timeout--;
0673 
0674         if (timeout <= 0) {
0675             dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
0676             break;
0677         }
0678     }
0679 
0680     writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
0681 }
0682 
0683 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
0684 {
0685     if (i2c_debug > 2)
0686         dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
0687 
0688     if (i2c->slave != NULL)
0689         i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL);
0690 
0691     if (i2c_debug > 2)
0692         dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
0693 
0694     /*
0695      * If we have a master-mode message waiting,
0696      * kick it off now that the slave has completed.
0697      */
0698     if (i2c->msg)
0699         i2c_pxa_master_complete(i2c, I2C_RETRY);
0700 }
0701 
0702 static int i2c_pxa_slave_reg(struct i2c_client *slave)
0703 {
0704     struct pxa_i2c *i2c = slave->adapter->algo_data;
0705 
0706     if (i2c->slave)
0707         return -EBUSY;
0708 
0709     if (!i2c->reg_isar)
0710         return -EAFNOSUPPORT;
0711 
0712     i2c->slave = slave;
0713     i2c->slave_addr = slave->addr;
0714 
0715     writel(i2c->slave_addr, _ISAR(i2c));
0716 
0717     return 0;
0718 }
0719 
0720 static int i2c_pxa_slave_unreg(struct i2c_client *slave)
0721 {
0722     struct pxa_i2c *i2c = slave->adapter->algo_data;
0723 
0724     WARN_ON(!i2c->slave);
0725 
0726     i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
0727     writel(i2c->slave_addr, _ISAR(i2c));
0728 
0729     i2c->slave = NULL;
0730 
0731     return 0;
0732 }
0733 #else
0734 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
0735 {
0736     if (isr & ISR_BED) {
0737         /* what should we do here? */
0738     } else {
0739         writel(0, _IDBR(i2c));
0740         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
0741     }
0742 }
0743 
0744 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
0745 {
0746     writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
0747 }
0748 
0749 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
0750 {
0751     int timeout;
0752 
0753     /*
0754      * slave could interrupt in the middle of us generating a
0755      * start condition... if this happens, we'd better back off
0756      * and stop holding the poor thing up
0757      */
0758     writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
0759     writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
0760 
0761     timeout = 0x10000;
0762 
0763     while (1) {
0764         if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
0765             break;
0766 
0767         timeout--;
0768 
0769         if (timeout <= 0) {
0770             dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
0771             break;
0772         }
0773     }
0774 
0775     writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
0776 }
0777 
0778 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
0779 {
0780     if (i2c->msg)
0781         i2c_pxa_master_complete(i2c, I2C_RETRY);
0782 }
0783 #endif
0784 
0785 /*
0786  * PXA I2C Master mode
0787  */
0788 
0789 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
0790 {
0791     u32 icr;
0792 
0793     /*
0794      * Step 1: target slave address into IDBR
0795      */
0796     i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
0797     writel(i2c->req_slave_addr, _IDBR(i2c));
0798 
0799     /*
0800      * Step 2: initiate the write.
0801      */
0802     icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
0803     writel(icr | ICR_START | ICR_TB, _ICR(i2c));
0804 }
0805 
0806 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
0807 {
0808     u32 icr;
0809 
0810     /* Clear the START, STOP, ACK, TB and MA flags */
0811     icr = readl(_ICR(i2c));
0812     icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
0813     writel(icr, _ICR(i2c));
0814 }
0815 
0816 /*
0817  * PXA I2C send master code
0818  * 1. Load master code to IDBR and send it.
0819  *    Note for HS mode, set ICR [GPIOEN].
0820  * 2. Wait until win arbitration.
0821  */
0822 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
0823 {
0824     u32 icr;
0825     long timeout;
0826 
0827     spin_lock_irq(&i2c->lock);
0828     i2c->highmode_enter = true;
0829     writel(i2c->master_code, _IDBR(i2c));
0830 
0831     icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
0832     icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
0833     writel(icr, _ICR(i2c));
0834 
0835     spin_unlock_irq(&i2c->lock);
0836     timeout = wait_event_timeout(i2c->wait,
0837             i2c->highmode_enter == false, HZ * 1);
0838 
0839     i2c->highmode_enter = false;
0840 
0841     return (timeout == 0) ? I2C_RETRY : 0;
0842 }
0843 
0844 /*
0845  * i2c_pxa_master_complete - complete the message and wake up.
0846  */
0847 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
0848 {
0849     i2c->msg_ptr = 0;
0850     i2c->msg = NULL;
0851     i2c->msg_idx ++;
0852     i2c->msg_num = 0;
0853     if (ret)
0854         i2c->msg_idx = ret;
0855     if (!i2c->use_pio)
0856         wake_up(&i2c->wait);
0857 }
0858 
0859 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
0860 {
0861     u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
0862 
0863  again:
0864     /*
0865      * If ISR_ALD is set, we lost arbitration.
0866      */
0867     if (isr & ISR_ALD) {
0868         /*
0869          * Do we need to do anything here?  The PXA docs
0870          * are vague about what happens.
0871          */
0872         i2c_pxa_scream_blue_murder(i2c, "ALD set");
0873 
0874         /*
0875          * We ignore this error.  We seem to see spurious ALDs
0876          * for seemingly no reason.  If we handle them as I think
0877          * they should, we end up causing an I2C error, which
0878          * is painful for some systems.
0879          */
0880         return; /* ignore */
0881     }
0882 
0883     if ((isr & ISR_BED) &&
0884         (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
0885             (isr & ISR_ACKNAK)))) {
0886         int ret = BUS_ERROR;
0887 
0888         /*
0889          * I2C bus error - either the device NAK'd us, or
0890          * something more serious happened.  If we were NAK'd
0891          * on the initial address phase, we can retry.
0892          */
0893         if (isr & ISR_ACKNAK) {
0894             if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
0895                 ret = NO_SLAVE;
0896             else
0897                 ret = XFER_NAKED;
0898         }
0899         i2c_pxa_master_complete(i2c, ret);
0900     } else if (isr & ISR_RWM) {
0901         /*
0902          * Read mode.  We have just sent the address byte, and
0903          * now we must initiate the transfer.
0904          */
0905         if (i2c->msg_ptr == i2c->msg->len - 1 &&
0906             i2c->msg_idx == i2c->msg_num - 1)
0907             icr |= ICR_STOP | ICR_ACKNAK;
0908 
0909         icr |= ICR_ALDIE | ICR_TB;
0910     } else if (i2c->msg_ptr < i2c->msg->len) {
0911         /*
0912          * Write mode.  Write the next data byte.
0913          */
0914         writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
0915 
0916         icr |= ICR_ALDIE | ICR_TB;
0917 
0918         /*
0919          * If this is the last byte of the last message or last byte
0920          * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
0921          */
0922         if ((i2c->msg_ptr == i2c->msg->len) &&
0923             ((i2c->msg->flags & I2C_M_STOP) ||
0924             (i2c->msg_idx == i2c->msg_num - 1)))
0925                 icr |= ICR_STOP;
0926 
0927     } else if (i2c->msg_idx < i2c->msg_num - 1) {
0928         /*
0929          * Next segment of the message.
0930          */
0931         i2c->msg_ptr = 0;
0932         i2c->msg_idx ++;
0933         i2c->msg++;
0934 
0935         /*
0936          * If we aren't doing a repeated start and address,
0937          * go back and try to send the next byte.  Note that
0938          * we do not support switching the R/W direction here.
0939          */
0940         if (i2c->msg->flags & I2C_M_NOSTART)
0941             goto again;
0942 
0943         /*
0944          * Write the next address.
0945          */
0946         i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
0947         writel(i2c->req_slave_addr, _IDBR(i2c));
0948 
0949         /*
0950          * And trigger a repeated start, and send the byte.
0951          */
0952         icr &= ~ICR_ALDIE;
0953         icr |= ICR_START | ICR_TB;
0954     } else {
0955         if (i2c->msg->len == 0)
0956             icr |= ICR_MA;
0957         i2c_pxa_master_complete(i2c, 0);
0958     }
0959 
0960     i2c->icrlog[i2c->irqlogidx-1] = icr;
0961 
0962     writel(icr, _ICR(i2c));
0963     show_state(i2c);
0964 }
0965 
0966 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
0967 {
0968     u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
0969 
0970     /*
0971      * Read the byte.
0972      */
0973     i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
0974 
0975     if (i2c->msg_ptr < i2c->msg->len) {
0976         /*
0977          * If this is the last byte of the last
0978          * message, send a STOP.
0979          */
0980         if (i2c->msg_ptr == i2c->msg->len - 1)
0981             icr |= ICR_STOP | ICR_ACKNAK;
0982 
0983         icr |= ICR_ALDIE | ICR_TB;
0984     } else {
0985         i2c_pxa_master_complete(i2c, 0);
0986     }
0987 
0988     i2c->icrlog[i2c->irqlogidx-1] = icr;
0989 
0990     writel(icr, _ICR(i2c));
0991 }
0992 
0993 #define VALID_INT_SOURCE    (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
0994                 ISR_SAD | ISR_BED)
0995 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
0996 {
0997     struct pxa_i2c *i2c = dev_id;
0998     u32 isr = readl(_ISR(i2c));
0999 
1000     if (!(isr & VALID_INT_SOURCE))
1001         return IRQ_NONE;
1002 
1003     if (i2c_debug > 2 && 0) {
1004         dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1005             __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1006         decode_ISR(isr);
1007     }
1008 
1009     if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1010         i2c->isrlog[i2c->irqlogidx++] = isr;
1011 
1012     show_state(i2c);
1013 
1014     /*
1015      * Always clear all pending IRQs.
1016      */
1017     writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1018 
1019     if (isr & ISR_SAD)
1020         i2c_pxa_slave_start(i2c, isr);
1021     if (isr & ISR_SSD)
1022         i2c_pxa_slave_stop(i2c);
1023 
1024     if (i2c_pxa_is_slavemode(i2c)) {
1025         if (isr & ISR_ITE)
1026             i2c_pxa_slave_txempty(i2c, isr);
1027         if (isr & ISR_IRF)
1028             i2c_pxa_slave_rxfull(i2c, isr);
1029     } else if (i2c->msg && (!i2c->highmode_enter)) {
1030         if (isr & ISR_ITE)
1031             i2c_pxa_irq_txempty(i2c, isr);
1032         if (isr & ISR_IRF)
1033             i2c_pxa_irq_rxfull(i2c, isr);
1034     } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1035         i2c->highmode_enter = false;
1036         wake_up(&i2c->wait);
1037     } else {
1038         i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1039     }
1040 
1041     return IRQ_HANDLED;
1042 }
1043 
1044 /*
1045  * We are protected by the adapter bus mutex.
1046  */
1047 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
1048 {
1049     long timeout;
1050     int ret;
1051 
1052     /*
1053      * Wait for the bus to become free.
1054      */
1055     ret = i2c_pxa_wait_bus_not_busy(i2c);
1056     if (ret) {
1057         dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
1058         i2c_recover_bus(&i2c->adap);
1059         goto out;
1060     }
1061 
1062     /*
1063      * Set master mode.
1064      */
1065     ret = i2c_pxa_set_master(i2c);
1066     if (ret) {
1067         dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
1068         goto out;
1069     }
1070 
1071     if (i2c->high_mode) {
1072         ret = i2c_pxa_send_mastercode(i2c);
1073         if (ret) {
1074             dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
1075             goto out;
1076             }
1077     }
1078 
1079     spin_lock_irq(&i2c->lock);
1080 
1081     i2c->msg = msg;
1082     i2c->msg_num = num;
1083     i2c->msg_idx = 0;
1084     i2c->msg_ptr = 0;
1085     i2c->irqlogidx = 0;
1086 
1087     i2c_pxa_start_message(i2c);
1088 
1089     spin_unlock_irq(&i2c->lock);
1090 
1091     /*
1092      * The rest of the processing occurs in the interrupt handler.
1093      */
1094     timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
1095     i2c_pxa_stop_message(i2c);
1096 
1097     /*
1098      * We place the return code in i2c->msg_idx.
1099      */
1100     ret = i2c->msg_idx;
1101 
1102     if (!timeout && i2c->msg_num) {
1103         i2c_pxa_scream_blue_murder(i2c, "timeout with active message");
1104         i2c_recover_bus(&i2c->adap);
1105         ret = I2C_RETRY;
1106     }
1107 
1108  out:
1109     return ret;
1110 }
1111 
1112 static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
1113                  struct i2c_msg *msgs, int num,
1114                  int (*xfer)(struct pxa_i2c *,
1115                          struct i2c_msg *, int num))
1116 {
1117     int ret, i;
1118 
1119     for (i = 0; ; ) {
1120         ret = xfer(i2c, msgs, num);
1121         if (ret != I2C_RETRY && ret != NO_SLAVE)
1122             goto out;
1123         if (++i >= i2c->adap.retries)
1124             break;
1125 
1126         if (i2c_debug)
1127             dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
1128         udelay(100);
1129     }
1130     if (ret != NO_SLAVE)
1131         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1132     ret = -EREMOTEIO;
1133  out:
1134     i2c_pxa_set_slave(i2c, ret);
1135     return ret;
1136 }
1137 
1138 static int i2c_pxa_xfer(struct i2c_adapter *adap,
1139             struct i2c_msg msgs[], int num)
1140 {
1141     struct pxa_i2c *i2c = adap->algo_data;
1142 
1143     return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_xfer);
1144 }
1145 
1146 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1147 {
1148     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1149         I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1150 }
1151 
1152 static const struct i2c_algorithm i2c_pxa_algorithm = {
1153     .master_xfer    = i2c_pxa_xfer,
1154     .functionality  = i2c_pxa_functionality,
1155 #ifdef CONFIG_I2C_PXA_SLAVE
1156     .reg_slave  = i2c_pxa_slave_reg,
1157     .unreg_slave    = i2c_pxa_slave_unreg,
1158 #endif
1159 };
1160 
1161 /* Non-interrupt mode support */
1162 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
1163 {
1164     /* make timeout the same as for interrupt based functions */
1165     long timeout = 2 * DEF_TIMEOUT;
1166 
1167     /*
1168      * Wait for the bus to become free.
1169      */
1170     while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB))
1171         udelay(1000);
1172 
1173     if (timeout < 0) {
1174         show_state(i2c);
1175         dev_err(&i2c->adap.dev,
1176             "i2c_pxa: timeout waiting for bus free (set_master)\n");
1177         return I2C_RETRY;
1178     }
1179 
1180     /*
1181      * Set master mode.
1182      */
1183     writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
1184 
1185     return 0;
1186 }
1187 
1188 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
1189                    struct i2c_msg *msg, int num)
1190 {
1191     unsigned long timeout = 500000; /* 5 seconds */
1192     int ret = 0;
1193 
1194     ret = i2c_pxa_pio_set_master(i2c);
1195     if (ret)
1196         goto out;
1197 
1198     i2c->msg = msg;
1199     i2c->msg_num = num;
1200     i2c->msg_idx = 0;
1201     i2c->msg_ptr = 0;
1202     i2c->irqlogidx = 0;
1203 
1204     i2c_pxa_start_message(i2c);
1205 
1206     while (i2c->msg_num > 0 && --timeout) {
1207         i2c_pxa_handler(0, i2c);
1208         udelay(10);
1209     }
1210 
1211     i2c_pxa_stop_message(i2c);
1212 
1213     /*
1214      * We place the return code in i2c->msg_idx.
1215      */
1216     ret = i2c->msg_idx;
1217 
1218 out:
1219     if (timeout == 0) {
1220         i2c_pxa_scream_blue_murder(i2c, "timeout (do_pio_xfer)");
1221         ret = I2C_RETRY;
1222     }
1223 
1224     return ret;
1225 }
1226 
1227 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
1228                 struct i2c_msg msgs[], int num)
1229 {
1230     struct pxa_i2c *i2c = adap->algo_data;
1231 
1232     /* If the I2C controller is disabled we need to reset it
1233       (probably due to a suspend/resume destroying state). We do
1234       this here as we can then avoid worrying about resuming the
1235       controller before its users. */
1236     if (!(readl(_ICR(i2c)) & ICR_IUE))
1237         i2c_pxa_reset(i2c);
1238 
1239     return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_pio_xfer);
1240 }
1241 
1242 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1243     .master_xfer    = i2c_pxa_pio_xfer,
1244     .functionality  = i2c_pxa_functionality,
1245 #ifdef CONFIG_I2C_PXA_SLAVE
1246     .reg_slave  = i2c_pxa_slave_reg,
1247     .unreg_slave    = i2c_pxa_slave_unreg,
1248 #endif
1249 };
1250 
1251 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1252                 enum pxa_i2c_types *i2c_types)
1253 {
1254     struct device_node *np = pdev->dev.of_node;
1255     const struct of_device_id *of_id =
1256             of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1257 
1258     if (!of_id)
1259         return 1;
1260 
1261     /* For device tree we always use the dynamic or alias-assigned ID */
1262     i2c->adap.nr = -1;
1263 
1264     if (of_get_property(np, "mrvl,i2c-polling", NULL))
1265         i2c->use_pio = 1;
1266     if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1267         i2c->fast_mode = 1;
1268 
1269     *i2c_types = (enum pxa_i2c_types)(of_id->data);
1270 
1271     return 0;
1272 }
1273 
1274 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1275                    struct pxa_i2c *i2c,
1276                    enum pxa_i2c_types *i2c_types)
1277 {
1278     struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1279     const struct platform_device_id *id = platform_get_device_id(pdev);
1280 
1281     *i2c_types = id->driver_data;
1282     if (plat) {
1283         i2c->use_pio = plat->use_pio;
1284         i2c->fast_mode = plat->fast_mode;
1285         i2c->high_mode = plat->high_mode;
1286         i2c->master_code = plat->master_code;
1287         if (!i2c->master_code)
1288             i2c->master_code = 0xe;
1289         i2c->rate = plat->rate;
1290     }
1291     return 0;
1292 }
1293 
1294 static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap)
1295 {
1296     struct pxa_i2c *i2c = adap->algo_data;
1297     u32 ibmr = readl(_IBMR(i2c));
1298 
1299     /*
1300      * Program the GPIOs to reflect the current I2C bus state while
1301      * we transition to recovery; this avoids glitching the bus.
1302      */
1303     gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS);
1304     gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS);
1305 }
1306 
1307 static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
1308 {
1309     struct pxa_i2c *i2c = adap->algo_data;
1310     struct i2c_bus_recovery_info *bri = adap->bus_recovery_info;
1311     u32 isr;
1312 
1313     /*
1314      * The bus should now be free. Clear up the I2C controller before
1315      * handing control of the bus back to avoid the bus changing state.
1316      */
1317     isr = readl(_ISR(i2c));
1318     if (isr & (ISR_UB | ISR_IBB)) {
1319         dev_dbg(&i2c->adap.dev,
1320             "recovery: resetting controller, ISR=0x%08x\n", isr);
1321         i2c_pxa_do_reset(i2c);
1322     }
1323 
1324     WARN_ON(pinctrl_select_state(bri->pinctrl, bri->pins_default));
1325 
1326     dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
1327             readl(_IBMR(i2c)), readl(_ISR(i2c)));
1328 
1329     i2c_pxa_enable(i2c);
1330 }
1331 
1332 static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
1333 {
1334     struct i2c_bus_recovery_info *bri = &i2c->recovery;
1335     struct device *dev = i2c->adap.dev.parent;
1336 
1337     /*
1338      * When slave mode is enabled, we are not the only master on the bus.
1339      * Bus recovery can only be performed when we are the master, which
1340      * we can't be certain of. Therefore, when slave mode is enabled, do
1341      * not configure bus recovery.
1342      */
1343     if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
1344         return 0;
1345 
1346     bri->pinctrl = devm_pinctrl_get(dev);
1347     if (PTR_ERR(bri->pinctrl) == -ENODEV) {
1348         bri->pinctrl = NULL;
1349         return 0;
1350     }
1351     if (IS_ERR(bri->pinctrl))
1352         return PTR_ERR(bri->pinctrl);
1353 
1354     bri->prepare_recovery = i2c_pxa_prepare_recovery;
1355     bri->unprepare_recovery = i2c_pxa_unprepare_recovery;
1356 
1357     i2c->adap.bus_recovery_info = bri;
1358 
1359     return 0;
1360 }
1361 
1362 static int i2c_pxa_probe(struct platform_device *dev)
1363 {
1364     struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1365     enum pxa_i2c_types i2c_type;
1366     struct pxa_i2c *i2c;
1367     struct resource *res = NULL;
1368     int ret, irq;
1369 
1370     i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1371     if (!i2c)
1372         return -ENOMEM;
1373 
1374     /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1375     i2c->adap.nr = dev->id;
1376     i2c->adap.owner   = THIS_MODULE;
1377     i2c->adap.retries = 5;
1378     i2c->adap.algo_data = i2c;
1379     i2c->adap.dev.parent = &dev->dev;
1380 #ifdef CONFIG_OF
1381     i2c->adap.dev.of_node = dev->dev.of_node;
1382 #endif
1383 
1384     res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1385     i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1386     if (IS_ERR(i2c->reg_base))
1387         return PTR_ERR(i2c->reg_base);
1388 
1389     irq = platform_get_irq(dev, 0);
1390     if (irq < 0)
1391         return irq;
1392 
1393     ret = i2c_pxa_init_recovery(i2c);
1394     if (ret)
1395         return ret;
1396 
1397     ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1398     if (ret > 0)
1399         ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1400     if (ret < 0)
1401         return ret;
1402 
1403     spin_lock_init(&i2c->lock);
1404     init_waitqueue_head(&i2c->wait);
1405 
1406     strscpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1407 
1408     i2c->clk = devm_clk_get(&dev->dev, NULL);
1409     if (IS_ERR(i2c->clk)) {
1410         dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1411         return PTR_ERR(i2c->clk);
1412     }
1413 
1414     i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1415     i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1416     i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1417     i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1418     i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
1419     i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1420 
1421     if (i2c_type != REGS_CE4100)
1422         i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1423 
1424     if (i2c_type == REGS_PXA910) {
1425         i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1426         i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1427     }
1428 
1429     i2c->iobase = res->start;
1430     i2c->iosize = resource_size(res);
1431 
1432     i2c->irq = irq;
1433 
1434     i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1435     i2c->highmode_enter = false;
1436 
1437     if (plat) {
1438         i2c->adap.class = plat->class;
1439     }
1440 
1441     if (i2c->high_mode) {
1442         if (i2c->rate) {
1443             clk_set_rate(i2c->clk, i2c->rate);
1444             pr_info("i2c: <%s> set rate to %ld\n",
1445                 i2c->adap.name, clk_get_rate(i2c->clk));
1446         } else
1447             pr_warn("i2c: <%s> clock rate not set\n",
1448                 i2c->adap.name);
1449     }
1450 
1451     clk_prepare_enable(i2c->clk);
1452 
1453     if (i2c->use_pio) {
1454         i2c->adap.algo = &i2c_pxa_pio_algorithm;
1455     } else {
1456         i2c->adap.algo = &i2c_pxa_algorithm;
1457         ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1458                 IRQF_SHARED | IRQF_NO_SUSPEND,
1459                 dev_name(&dev->dev), i2c);
1460         if (ret) {
1461             dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1462             goto ereqirq;
1463         }
1464     }
1465 
1466     i2c_pxa_reset(i2c);
1467 
1468     ret = i2c_add_numbered_adapter(&i2c->adap);
1469     if (ret < 0)
1470         goto ereqirq;
1471 
1472     platform_set_drvdata(dev, i2c);
1473 
1474 #ifdef CONFIG_I2C_PXA_SLAVE
1475     dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1476         i2c->slave_addr);
1477 #else
1478     dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1479 #endif
1480     return 0;
1481 
1482 ereqirq:
1483     clk_disable_unprepare(i2c->clk);
1484     return ret;
1485 }
1486 
1487 static int i2c_pxa_remove(struct platform_device *dev)
1488 {
1489     struct pxa_i2c *i2c = platform_get_drvdata(dev);
1490 
1491     i2c_del_adapter(&i2c->adap);
1492 
1493     clk_disable_unprepare(i2c->clk);
1494 
1495     return 0;
1496 }
1497 
1498 #ifdef CONFIG_PM
1499 static int i2c_pxa_suspend_noirq(struct device *dev)
1500 {
1501     struct pxa_i2c *i2c = dev_get_drvdata(dev);
1502 
1503     clk_disable(i2c->clk);
1504 
1505     return 0;
1506 }
1507 
1508 static int i2c_pxa_resume_noirq(struct device *dev)
1509 {
1510     struct pxa_i2c *i2c = dev_get_drvdata(dev);
1511 
1512     clk_enable(i2c->clk);
1513     i2c_pxa_reset(i2c);
1514 
1515     return 0;
1516 }
1517 
1518 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1519     .suspend_noirq = i2c_pxa_suspend_noirq,
1520     .resume_noirq = i2c_pxa_resume_noirq,
1521 };
1522 
1523 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1524 #else
1525 #define I2C_PXA_DEV_PM_OPS NULL
1526 #endif
1527 
1528 static struct platform_driver i2c_pxa_driver = {
1529     .probe      = i2c_pxa_probe,
1530     .remove     = i2c_pxa_remove,
1531     .driver     = {
1532         .name   = "pxa2xx-i2c",
1533         .pm = I2C_PXA_DEV_PM_OPS,
1534         .of_match_table = i2c_pxa_dt_ids,
1535     },
1536     .id_table   = i2c_pxa_id_table,
1537 };
1538 
1539 static int __init i2c_adap_pxa_init(void)
1540 {
1541     return platform_driver_register(&i2c_pxa_driver);
1542 }
1543 
1544 static void __exit i2c_adap_pxa_exit(void)
1545 {
1546     platform_driver_unregister(&i2c_pxa_driver);
1547 }
1548 
1549 MODULE_LICENSE("GPL");
1550 
1551 subsys_initcall(i2c_adap_pxa_init);
1552 module_exit(i2c_adap_pxa_exit);
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