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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
0004     Philip Edelbrock <phil@netroedge.com>
0005 
0006 */
0007 
0008 /*
0009    Supports:
0010     Intel PIIX4, 440MX
0011     Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
0012     ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
0013     AMD Hudson-2, ML, CZ
0014     Hygon CZ
0015     SMSC Victory66
0016 
0017    Note: we assume there can only be one device, with one or more
0018    SMBus interfaces.
0019    The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
0020    For devices supporting multiple ports the i2c_adapter should provide
0021    an i2c_algorithm to access them.
0022 */
0023 
0024 #include <linux/module.h>
0025 #include <linux/moduleparam.h>
0026 #include <linux/pci.h>
0027 #include <linux/kernel.h>
0028 #include <linux/delay.h>
0029 #include <linux/stddef.h>
0030 #include <linux/ioport.h>
0031 #include <linux/i2c.h>
0032 #include <linux/slab.h>
0033 #include <linux/dmi.h>
0034 #include <linux/acpi.h>
0035 #include <linux/io.h>
0036 
0037 
0038 /* PIIX4 SMBus address offsets */
0039 #define SMBHSTSTS   (0 + piix4_smba)
0040 #define SMBHSLVSTS  (1 + piix4_smba)
0041 #define SMBHSTCNT   (2 + piix4_smba)
0042 #define SMBHSTCMD   (3 + piix4_smba)
0043 #define SMBHSTADD   (4 + piix4_smba)
0044 #define SMBHSTDAT0  (5 + piix4_smba)
0045 #define SMBHSTDAT1  (6 + piix4_smba)
0046 #define SMBBLKDAT   (7 + piix4_smba)
0047 #define SMBSLVCNT   (8 + piix4_smba)
0048 #define SMBSHDWCMD  (9 + piix4_smba)
0049 #define SMBSLVEVT   (0xA + piix4_smba)
0050 #define SMBSLVDAT   (0xC + piix4_smba)
0051 
0052 /* count for request_region */
0053 #define SMBIOSIZE   9
0054 
0055 /* PCI Address Constants */
0056 #define SMBBA       0x090
0057 #define SMBHSTCFG   0x0D2
0058 #define SMBSLVC     0x0D3
0059 #define SMBSHDW1    0x0D4
0060 #define SMBSHDW2    0x0D5
0061 #define SMBREV      0x0D6
0062 
0063 /* Other settings */
0064 #define MAX_TIMEOUT 500
0065 #define  ENABLE_INT9    0
0066 
0067 /* PIIX4 constants */
0068 #define PIIX4_QUICK     0x00
0069 #define PIIX4_BYTE      0x04
0070 #define PIIX4_BYTE_DATA     0x08
0071 #define PIIX4_WORD_DATA     0x0C
0072 #define PIIX4_BLOCK_DATA    0x14
0073 
0074 /* Multi-port constants */
0075 #define PIIX4_MAX_ADAPTERS  4
0076 #define HUDSON2_MAIN_PORTS  2 /* HUDSON2, KERNCZ reserves ports 3, 4 */
0077 
0078 /* SB800 constants */
0079 #define SB800_PIIX4_SMB_IDX     0xcd6
0080 #define SB800_PIIX4_SMB_MAP_SIZE    2
0081 
0082 #define KERNCZ_IMC_IDX          0x3e
0083 #define KERNCZ_IMC_DATA         0x3f
0084 
0085 /*
0086  * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
0087  * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
0088  * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
0089  */
0090 #define SB800_PIIX4_PORT_IDX        0x2c
0091 #define SB800_PIIX4_PORT_IDX_ALT    0x2e
0092 #define SB800_PIIX4_PORT_IDX_SEL    0x2f
0093 #define SB800_PIIX4_PORT_IDX_MASK   0x06
0094 #define SB800_PIIX4_PORT_IDX_SHIFT  1
0095 
0096 /* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
0097 #define SB800_PIIX4_PORT_IDX_KERNCZ     0x02
0098 #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ    0x18
0099 #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ   3
0100 
0101 #define SB800_PIIX4_FCH_PM_ADDR         0xFED80300
0102 #define SB800_PIIX4_FCH_PM_SIZE         8
0103 
0104 /* insmod parameters */
0105 
0106 /* If force is set to anything different from 0, we forcibly enable the
0107    PIIX4. DANGEROUS! */
0108 static int force;
0109 module_param (force, int, 0);
0110 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
0111 
0112 /* If force_addr is set to anything different from 0, we forcibly enable
0113    the PIIX4 at the given address. VERY DANGEROUS! */
0114 static int force_addr;
0115 module_param_hw(force_addr, int, ioport, 0);
0116 MODULE_PARM_DESC(force_addr,
0117          "Forcibly enable the PIIX4 at the given address. "
0118          "EXTREMELY DANGEROUS!");
0119 
0120 static int srvrworks_csb5_delay;
0121 static struct pci_driver piix4_driver;
0122 
0123 static const struct dmi_system_id piix4_dmi_blacklist[] = {
0124     {
0125         .ident = "Sapphire AM2RD790",
0126         .matches = {
0127             DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
0128             DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
0129         },
0130     },
0131     {
0132         .ident = "DFI Lanparty UT 790FX",
0133         .matches = {
0134             DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
0135             DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
0136         },
0137     },
0138     { }
0139 };
0140 
0141 /* The IBM entry is in a separate table because we only check it
0142    on Intel-based systems */
0143 static const struct dmi_system_id piix4_dmi_ibm[] = {
0144     {
0145         .ident = "IBM",
0146         .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
0147     },
0148     { },
0149 };
0150 
0151 /*
0152  * SB800 globals
0153  */
0154 static u8 piix4_port_sel_sb800;
0155 static u8 piix4_port_mask_sb800;
0156 static u8 piix4_port_shift_sb800;
0157 static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
0158     " port 0", " port 2", " port 3", " port 4"
0159 };
0160 static const char *piix4_aux_port_name_sb800 = " port 1";
0161 
0162 struct sb800_mmio_cfg {
0163     void __iomem *addr;
0164     bool use_mmio;
0165 };
0166 
0167 struct i2c_piix4_adapdata {
0168     unsigned short smba;
0169 
0170     /* SB800 */
0171     bool sb800_main;
0172     bool notify_imc;
0173     u8 port;        /* Port number, shifted */
0174     struct sb800_mmio_cfg mmio_cfg;
0175 };
0176 
0177 static int piix4_sb800_region_request(struct device *dev,
0178                       struct sb800_mmio_cfg *mmio_cfg)
0179 {
0180     if (mmio_cfg->use_mmio) {
0181         void __iomem *addr;
0182 
0183         if (!request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR,
0184                           SB800_PIIX4_FCH_PM_SIZE,
0185                           "sb800_piix4_smb")) {
0186             dev_err(dev,
0187                 "SMBus base address memory region 0x%x already in use.\n",
0188                 SB800_PIIX4_FCH_PM_ADDR);
0189             return -EBUSY;
0190         }
0191 
0192         addr = ioremap(SB800_PIIX4_FCH_PM_ADDR,
0193                    SB800_PIIX4_FCH_PM_SIZE);
0194         if (!addr) {
0195             release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
0196                        SB800_PIIX4_FCH_PM_SIZE);
0197             dev_err(dev, "SMBus base address mapping failed.\n");
0198             return -ENOMEM;
0199         }
0200 
0201         mmio_cfg->addr = addr;
0202 
0203         return 0;
0204     }
0205 
0206     if (!request_muxed_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE,
0207                   "sb800_piix4_smb")) {
0208         dev_err(dev,
0209             "SMBus base address index region 0x%x already in use.\n",
0210             SB800_PIIX4_SMB_IDX);
0211         return -EBUSY;
0212     }
0213 
0214     return 0;
0215 }
0216 
0217 static void piix4_sb800_region_release(struct device *dev,
0218                        struct sb800_mmio_cfg *mmio_cfg)
0219 {
0220     if (mmio_cfg->use_mmio) {
0221         iounmap(mmio_cfg->addr);
0222         release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
0223                    SB800_PIIX4_FCH_PM_SIZE);
0224         return;
0225     }
0226 
0227     release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE);
0228 }
0229 
0230 static bool piix4_sb800_use_mmio(struct pci_dev *PIIX4_dev)
0231 {
0232     /*
0233      * cd6h/cd7h port I/O accesses can be disabled on AMD processors
0234      * w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on
0235      * the same processors and is the recommended access method.
0236      */
0237     return (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
0238         PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
0239         PIIX4_dev->revision >= 0x51);
0240 }
0241 
0242 static int piix4_setup(struct pci_dev *PIIX4_dev,
0243                const struct pci_device_id *id)
0244 {
0245     unsigned char temp;
0246     unsigned short piix4_smba;
0247 
0248     if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
0249         (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
0250         srvrworks_csb5_delay = 1;
0251 
0252     /* On some motherboards, it was reported that accessing the SMBus
0253        caused severe hardware problems */
0254     if (dmi_check_system(piix4_dmi_blacklist)) {
0255         dev_err(&PIIX4_dev->dev,
0256             "Accessing the SMBus on this system is unsafe!\n");
0257         return -EPERM;
0258     }
0259 
0260     /* Don't access SMBus on IBM systems which get corrupted eeproms */
0261     if (dmi_check_system(piix4_dmi_ibm) &&
0262             PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
0263         dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
0264             "may corrupt your serial eeprom! Refusing to load "
0265             "module!\n");
0266         return -EPERM;
0267     }
0268 
0269     /* Determine the address of the SMBus areas */
0270     if (force_addr) {
0271         piix4_smba = force_addr & 0xfff0;
0272         force = 0;
0273     } else {
0274         pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
0275         piix4_smba &= 0xfff0;
0276         if(piix4_smba == 0) {
0277             dev_err(&PIIX4_dev->dev, "SMBus base address "
0278                 "uninitialized - upgrade BIOS or use "
0279                 "force_addr=0xaddr\n");
0280             return -ENODEV;
0281         }
0282     }
0283 
0284     if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
0285         return -ENODEV;
0286 
0287     if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
0288         dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
0289             piix4_smba);
0290         return -EBUSY;
0291     }
0292 
0293     pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
0294 
0295     /* If force_addr is set, we program the new address here. Just to make
0296        sure, we disable the PIIX4 first. */
0297     if (force_addr) {
0298         pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
0299         pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
0300         pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
0301         dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
0302             "new address %04x!\n", piix4_smba);
0303     } else if ((temp & 1) == 0) {
0304         if (force) {
0305             /* This should never need to be done, but has been
0306              * noted that many Dell machines have the SMBus
0307              * interface on the PIIX4 disabled!? NOTE: This assumes
0308              * I/O space and other allocations WERE done by the
0309              * Bios!  Don't complain if your hardware does weird
0310              * things after enabling this. :') Check for Bios
0311              * updates before resorting to this.
0312              */
0313             pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
0314                           temp | 1);
0315             dev_notice(&PIIX4_dev->dev,
0316                    "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
0317         } else {
0318             dev_err(&PIIX4_dev->dev,
0319                 "SMBus Host Controller not enabled!\n");
0320             release_region(piix4_smba, SMBIOSIZE);
0321             return -ENODEV;
0322         }
0323     }
0324 
0325     if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
0326         dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
0327     else if ((temp & 0x0E) == 0)
0328         dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
0329     else
0330         dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
0331             "(or code out of date)!\n");
0332 
0333     pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
0334     dev_info(&PIIX4_dev->dev,
0335          "SMBus Host Controller at 0x%x, revision %d\n",
0336          piix4_smba, temp);
0337 
0338     return piix4_smba;
0339 }
0340 
0341 static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev,
0342                   u8 smb_en,
0343                   u8 aux,
0344                   u8 *smb_en_status,
0345                   unsigned short *piix4_smba)
0346 {
0347     struct sb800_mmio_cfg mmio_cfg;
0348     u8 smba_en_lo;
0349     u8 smba_en_hi;
0350     int retval;
0351 
0352     mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
0353     retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
0354     if (retval)
0355         return retval;
0356 
0357     if (mmio_cfg.use_mmio) {
0358         smba_en_lo = ioread8(mmio_cfg.addr);
0359         smba_en_hi = ioread8(mmio_cfg.addr + 1);
0360     } else {
0361         outb_p(smb_en, SB800_PIIX4_SMB_IDX);
0362         smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
0363         outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
0364         smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
0365     }
0366 
0367     piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg);
0368 
0369     if (!smb_en) {
0370         *smb_en_status = smba_en_lo & 0x10;
0371         *piix4_smba = smba_en_hi << 8;
0372         if (aux)
0373             *piix4_smba |= 0x20;
0374     } else {
0375         *smb_en_status = smba_en_lo & 0x01;
0376         *piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
0377     }
0378 
0379     if (!*smb_en_status) {
0380         dev_err(&PIIX4_dev->dev,
0381             "SMBus Host Controller not enabled!\n");
0382         return -ENODEV;
0383     }
0384 
0385     return 0;
0386 }
0387 
0388 static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
0389                  const struct pci_device_id *id, u8 aux)
0390 {
0391     unsigned short piix4_smba;
0392     u8 smb_en, smb_en_status, port_sel;
0393     u8 i2ccfg, i2ccfg_offset = 0x10;
0394     struct sb800_mmio_cfg mmio_cfg;
0395     int retval;
0396 
0397     /* SB800 and later SMBus does not support forcing address */
0398     if (force || force_addr) {
0399         dev_err(&PIIX4_dev->dev, "SMBus does not support "
0400             "forcing address!\n");
0401         return -EINVAL;
0402     }
0403 
0404     /* Determine the address of the SMBus areas */
0405     if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
0406          PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
0407          PIIX4_dev->revision >= 0x41) ||
0408         (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
0409          PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
0410          PIIX4_dev->revision >= 0x49) ||
0411         (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
0412          PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
0413         smb_en = 0x00;
0414     else
0415         smb_en = (aux) ? 0x28 : 0x2c;
0416 
0417     retval = piix4_setup_sb800_smba(PIIX4_dev, smb_en, aux, &smb_en_status,
0418                     &piix4_smba);
0419 
0420     if (retval)
0421         return retval;
0422 
0423     if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
0424         return -ENODEV;
0425 
0426     if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
0427         dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
0428             piix4_smba);
0429         return -EBUSY;
0430     }
0431 
0432     /* Aux SMBus does not support IRQ information */
0433     if (aux) {
0434         dev_info(&PIIX4_dev->dev,
0435              "Auxiliary SMBus Host Controller at 0x%x\n",
0436              piix4_smba);
0437         return piix4_smba;
0438     }
0439 
0440     /* Request the SMBus I2C bus config region */
0441     if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
0442         dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
0443             "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
0444         release_region(piix4_smba, SMBIOSIZE);
0445         return -EBUSY;
0446     }
0447     i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
0448     release_region(piix4_smba + i2ccfg_offset, 1);
0449 
0450     if (i2ccfg & 1)
0451         dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
0452     else
0453         dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
0454 
0455     dev_info(&PIIX4_dev->dev,
0456          "SMBus Host Controller at 0x%x, revision %d\n",
0457          piix4_smba, i2ccfg >> 4);
0458 
0459     /* Find which register is used for port selection */
0460     if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
0461         PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
0462         if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
0463             (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
0464              PIIX4_dev->revision >= 0x1F)) {
0465             piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
0466             piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
0467             piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
0468         } else {
0469             piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
0470             piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
0471             piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
0472         }
0473     } else {
0474         mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
0475         retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
0476         if (retval) {
0477             release_region(piix4_smba, SMBIOSIZE);
0478             return retval;
0479         }
0480 
0481         outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
0482         port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
0483         piix4_port_sel_sb800 = (port_sel & 0x01) ?
0484                        SB800_PIIX4_PORT_IDX_ALT :
0485                        SB800_PIIX4_PORT_IDX;
0486         piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
0487         piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
0488         piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg);
0489     }
0490 
0491     dev_info(&PIIX4_dev->dev,
0492          "Using register 0x%02x for SMBus port selection\n",
0493          (unsigned int)piix4_port_sel_sb800);
0494 
0495     return piix4_smba;
0496 }
0497 
0498 static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
0499                const struct pci_device_id *id,
0500                unsigned short base_reg_addr)
0501 {
0502     /* Set up auxiliary SMBus controllers found on some
0503      * AMD chipsets e.g. SP5100 (SB700 derivative) */
0504 
0505     unsigned short piix4_smba;
0506 
0507     /* Read address of auxiliary SMBus controller */
0508     pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
0509     if ((piix4_smba & 1) == 0) {
0510         dev_dbg(&PIIX4_dev->dev,
0511             "Auxiliary SMBus controller not enabled\n");
0512         return -ENODEV;
0513     }
0514 
0515     piix4_smba &= 0xfff0;
0516     if (piix4_smba == 0) {
0517         dev_dbg(&PIIX4_dev->dev,
0518             "Auxiliary SMBus base address uninitialized\n");
0519         return -ENODEV;
0520     }
0521 
0522     if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
0523         return -ENODEV;
0524 
0525     if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
0526         dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
0527             "already in use!\n", piix4_smba);
0528         return -EBUSY;
0529     }
0530 
0531     dev_info(&PIIX4_dev->dev,
0532          "Auxiliary SMBus Host Controller at 0x%x\n",
0533          piix4_smba);
0534 
0535     return piix4_smba;
0536 }
0537 
0538 static int piix4_transaction(struct i2c_adapter *piix4_adapter)
0539 {
0540     struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
0541     unsigned short piix4_smba = adapdata->smba;
0542     int temp;
0543     int result = 0;
0544     int timeout = 0;
0545 
0546     dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
0547         "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
0548         inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
0549         inb_p(SMBHSTDAT1));
0550 
0551     /* Make sure the SMBus host is ready to start transmitting */
0552     if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
0553         dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
0554             "Resetting...\n", temp);
0555         outb_p(temp, SMBHSTSTS);
0556         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
0557             dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
0558             return -EBUSY;
0559         } else {
0560             dev_dbg(&piix4_adapter->dev, "Successful!\n");
0561         }
0562     }
0563 
0564     /* start the transaction by setting bit 6 */
0565     outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
0566 
0567     /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
0568     if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
0569         usleep_range(2000, 2100);
0570     else
0571         usleep_range(250, 500);
0572 
0573     while ((++timeout < MAX_TIMEOUT) &&
0574            ((temp = inb_p(SMBHSTSTS)) & 0x01))
0575         usleep_range(250, 500);
0576 
0577     /* If the SMBus is still busy, we give up */
0578     if (timeout == MAX_TIMEOUT) {
0579         dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
0580         result = -ETIMEDOUT;
0581     }
0582 
0583     if (temp & 0x10) {
0584         result = -EIO;
0585         dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
0586     }
0587 
0588     if (temp & 0x08) {
0589         result = -EIO;
0590         dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
0591             "locked until next hard reset. (sorry!)\n");
0592         /* Clock stops and slave is stuck in mid-transmission */
0593     }
0594 
0595     if (temp & 0x04) {
0596         result = -ENXIO;
0597         dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
0598     }
0599 
0600     if (inb_p(SMBHSTSTS) != 0x00)
0601         outb_p(inb(SMBHSTSTS), SMBHSTSTS);
0602 
0603     if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
0604         dev_err(&piix4_adapter->dev, "Failed reset at end of "
0605             "transaction (%02x)\n", temp);
0606     }
0607     dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
0608         "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
0609         inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
0610         inb_p(SMBHSTDAT1));
0611     return result;
0612 }
0613 
0614 /* Return negative errno on error. */
0615 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
0616          unsigned short flags, char read_write,
0617          u8 command, int size, union i2c_smbus_data * data)
0618 {
0619     struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
0620     unsigned short piix4_smba = adapdata->smba;
0621     int i, len;
0622     int status;
0623 
0624     switch (size) {
0625     case I2C_SMBUS_QUICK:
0626         outb_p((addr << 1) | read_write,
0627                SMBHSTADD);
0628         size = PIIX4_QUICK;
0629         break;
0630     case I2C_SMBUS_BYTE:
0631         outb_p((addr << 1) | read_write,
0632                SMBHSTADD);
0633         if (read_write == I2C_SMBUS_WRITE)
0634             outb_p(command, SMBHSTCMD);
0635         size = PIIX4_BYTE;
0636         break;
0637     case I2C_SMBUS_BYTE_DATA:
0638         outb_p((addr << 1) | read_write,
0639                SMBHSTADD);
0640         outb_p(command, SMBHSTCMD);
0641         if (read_write == I2C_SMBUS_WRITE)
0642             outb_p(data->byte, SMBHSTDAT0);
0643         size = PIIX4_BYTE_DATA;
0644         break;
0645     case I2C_SMBUS_WORD_DATA:
0646         outb_p((addr << 1) | read_write,
0647                SMBHSTADD);
0648         outb_p(command, SMBHSTCMD);
0649         if (read_write == I2C_SMBUS_WRITE) {
0650             outb_p(data->word & 0xff, SMBHSTDAT0);
0651             outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
0652         }
0653         size = PIIX4_WORD_DATA;
0654         break;
0655     case I2C_SMBUS_BLOCK_DATA:
0656         outb_p((addr << 1) | read_write,
0657                SMBHSTADD);
0658         outb_p(command, SMBHSTCMD);
0659         if (read_write == I2C_SMBUS_WRITE) {
0660             len = data->block[0];
0661             if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
0662                 return -EINVAL;
0663             outb_p(len, SMBHSTDAT0);
0664             inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
0665             for (i = 1; i <= len; i++)
0666                 outb_p(data->block[i], SMBBLKDAT);
0667         }
0668         size = PIIX4_BLOCK_DATA;
0669         break;
0670     default:
0671         dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
0672         return -EOPNOTSUPP;
0673     }
0674 
0675     outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
0676 
0677     status = piix4_transaction(adap);
0678     if (status)
0679         return status;
0680 
0681     if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
0682         return 0;
0683 
0684 
0685     switch (size) {
0686     case PIIX4_BYTE:
0687     case PIIX4_BYTE_DATA:
0688         data->byte = inb_p(SMBHSTDAT0);
0689         break;
0690     case PIIX4_WORD_DATA:
0691         data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
0692         break;
0693     case PIIX4_BLOCK_DATA:
0694         data->block[0] = inb_p(SMBHSTDAT0);
0695         if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
0696             return -EPROTO;
0697         inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
0698         for (i = 1; i <= data->block[0]; i++)
0699             data->block[i] = inb_p(SMBBLKDAT);
0700         break;
0701     }
0702     return 0;
0703 }
0704 
0705 static uint8_t piix4_imc_read(uint8_t idx)
0706 {
0707     outb_p(idx, KERNCZ_IMC_IDX);
0708     return inb_p(KERNCZ_IMC_DATA);
0709 }
0710 
0711 static void piix4_imc_write(uint8_t idx, uint8_t value)
0712 {
0713     outb_p(idx, KERNCZ_IMC_IDX);
0714     outb_p(value, KERNCZ_IMC_DATA);
0715 }
0716 
0717 static int piix4_imc_sleep(void)
0718 {
0719     int timeout = MAX_TIMEOUT;
0720 
0721     if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
0722         return -EBUSY;
0723 
0724     /* clear response register */
0725     piix4_imc_write(0x82, 0x00);
0726     /* request ownership flag */
0727     piix4_imc_write(0x83, 0xB4);
0728     /* kick off IMC Mailbox command 96 */
0729     piix4_imc_write(0x80, 0x96);
0730 
0731     while (timeout--) {
0732         if (piix4_imc_read(0x82) == 0xfa) {
0733             release_region(KERNCZ_IMC_IDX, 2);
0734             return 0;
0735         }
0736         usleep_range(1000, 2000);
0737     }
0738 
0739     release_region(KERNCZ_IMC_IDX, 2);
0740     return -ETIMEDOUT;
0741 }
0742 
0743 static void piix4_imc_wakeup(void)
0744 {
0745     int timeout = MAX_TIMEOUT;
0746 
0747     if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
0748         return;
0749 
0750     /* clear response register */
0751     piix4_imc_write(0x82, 0x00);
0752     /* release ownership flag */
0753     piix4_imc_write(0x83, 0xB5);
0754     /* kick off IMC Mailbox command 96 */
0755     piix4_imc_write(0x80, 0x96);
0756 
0757     while (timeout--) {
0758         if (piix4_imc_read(0x82) == 0xfa)
0759             break;
0760         usleep_range(1000, 2000);
0761     }
0762 
0763     release_region(KERNCZ_IMC_IDX, 2);
0764 }
0765 
0766 static int piix4_sb800_port_sel(u8 port, struct sb800_mmio_cfg *mmio_cfg)
0767 {
0768     u8 smba_en_lo, val;
0769 
0770     if (mmio_cfg->use_mmio) {
0771         smba_en_lo = ioread8(mmio_cfg->addr + piix4_port_sel_sb800);
0772         val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
0773         if (smba_en_lo != val)
0774             iowrite8(val, mmio_cfg->addr + piix4_port_sel_sb800);
0775 
0776         return (smba_en_lo & piix4_port_mask_sb800);
0777     }
0778 
0779     outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
0780     smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
0781 
0782     val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
0783     if (smba_en_lo != val)
0784         outb_p(val, SB800_PIIX4_SMB_IDX + 1);
0785 
0786     return (smba_en_lo & piix4_port_mask_sb800);
0787 }
0788 
0789 /*
0790  * Handles access to multiple SMBus ports on the SB800.
0791  * The port is selected by bits 2:1 of the smb_en register (0x2c).
0792  * Returns negative errno on error.
0793  *
0794  * Note: The selected port must be returned to the initial selection to avoid
0795  * problems on certain systems.
0796  */
0797 static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
0798          unsigned short flags, char read_write,
0799          u8 command, int size, union i2c_smbus_data *data)
0800 {
0801     struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
0802     unsigned short piix4_smba = adapdata->smba;
0803     int retries = MAX_TIMEOUT;
0804     int smbslvcnt;
0805     u8 prev_port;
0806     int retval;
0807 
0808     retval = piix4_sb800_region_request(&adap->dev, &adapdata->mmio_cfg);
0809     if (retval)
0810         return retval;
0811 
0812     /* Request the SMBUS semaphore, avoid conflicts with the IMC */
0813     smbslvcnt  = inb_p(SMBSLVCNT);
0814     do {
0815         outb_p(smbslvcnt | 0x10, SMBSLVCNT);
0816 
0817         /* Check the semaphore status */
0818         smbslvcnt  = inb_p(SMBSLVCNT);
0819         if (smbslvcnt & 0x10)
0820             break;
0821 
0822         usleep_range(1000, 2000);
0823     } while (--retries);
0824     /* SMBus is still owned by the IMC, we give up */
0825     if (!retries) {
0826         retval = -EBUSY;
0827         goto release;
0828     }
0829 
0830     /*
0831      * Notify the IMC (Integrated Micro Controller) if required.
0832      * Among other responsibilities, the IMC is in charge of monitoring
0833      * the System fans and temperature sensors, and act accordingly.
0834      * All this is done through SMBus and can/will collide
0835      * with our transactions if they are long (BLOCK_DATA).
0836      * Therefore we need to request the ownership flag during those
0837      * transactions.
0838      */
0839     if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
0840         int ret;
0841 
0842         ret = piix4_imc_sleep();
0843         switch (ret) {
0844         case -EBUSY:
0845             dev_warn(&adap->dev,
0846                  "IMC base address index region 0x%x already in use.\n",
0847                  KERNCZ_IMC_IDX);
0848             break;
0849         case -ETIMEDOUT:
0850             dev_warn(&adap->dev,
0851                  "Failed to communicate with the IMC.\n");
0852             break;
0853         default:
0854             break;
0855         }
0856 
0857         /* If IMC communication fails do not retry */
0858         if (ret) {
0859             dev_warn(&adap->dev,
0860                  "Continuing without IMC notification.\n");
0861             adapdata->notify_imc = false;
0862         }
0863     }
0864 
0865     prev_port = piix4_sb800_port_sel(adapdata->port, &adapdata->mmio_cfg);
0866 
0867     retval = piix4_access(adap, addr, flags, read_write,
0868                   command, size, data);
0869 
0870     piix4_sb800_port_sel(prev_port, &adapdata->mmio_cfg);
0871 
0872     /* Release the semaphore */
0873     outb_p(smbslvcnt | 0x20, SMBSLVCNT);
0874 
0875     if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
0876         piix4_imc_wakeup();
0877 
0878 release:
0879     piix4_sb800_region_release(&adap->dev, &adapdata->mmio_cfg);
0880     return retval;
0881 }
0882 
0883 static u32 piix4_func(struct i2c_adapter *adapter)
0884 {
0885     return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
0886         I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
0887         I2C_FUNC_SMBUS_BLOCK_DATA;
0888 }
0889 
0890 static const struct i2c_algorithm smbus_algorithm = {
0891     .smbus_xfer = piix4_access,
0892     .functionality  = piix4_func,
0893 };
0894 
0895 static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
0896     .smbus_xfer = piix4_access_sb800,
0897     .functionality  = piix4_func,
0898 };
0899 
0900 static const struct pci_device_id piix4_ids[] = {
0901     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
0902     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
0903     { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
0904     { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
0905     { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
0906     { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
0907     { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
0908     { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
0909     { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
0910     { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
0911     { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
0912              PCI_DEVICE_ID_SERVERWORKS_OSB4) },
0913     { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
0914              PCI_DEVICE_ID_SERVERWORKS_CSB5) },
0915     { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
0916              PCI_DEVICE_ID_SERVERWORKS_CSB6) },
0917     { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
0918              PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
0919     { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
0920              PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
0921     { 0, }
0922 };
0923 
0924 MODULE_DEVICE_TABLE (pci, piix4_ids);
0925 
0926 static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
0927 static struct i2c_adapter *piix4_aux_adapter;
0928 static int piix4_adapter_count;
0929 
0930 static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
0931                  bool sb800_main, u8 port, bool notify_imc,
0932                  u8 hw_port_nr, const char *name,
0933                  struct i2c_adapter **padap)
0934 {
0935     struct i2c_adapter *adap;
0936     struct i2c_piix4_adapdata *adapdata;
0937     int retval;
0938 
0939     adap = kzalloc(sizeof(*adap), GFP_KERNEL);
0940     if (adap == NULL) {
0941         release_region(smba, SMBIOSIZE);
0942         return -ENOMEM;
0943     }
0944 
0945     adap->owner = THIS_MODULE;
0946     adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
0947     adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
0948                 : &smbus_algorithm;
0949 
0950     adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
0951     if (adapdata == NULL) {
0952         kfree(adap);
0953         release_region(smba, SMBIOSIZE);
0954         return -ENOMEM;
0955     }
0956 
0957     adapdata->mmio_cfg.use_mmio = piix4_sb800_use_mmio(dev);
0958     adapdata->smba = smba;
0959     adapdata->sb800_main = sb800_main;
0960     adapdata->port = port << piix4_port_shift_sb800;
0961     adapdata->notify_imc = notify_imc;
0962 
0963     /* set up the sysfs linkage to our parent device */
0964     adap->dev.parent = &dev->dev;
0965 
0966     if (has_acpi_companion(&dev->dev)) {
0967         acpi_preset_companion(&adap->dev,
0968                       ACPI_COMPANION(&dev->dev),
0969                       hw_port_nr);
0970     }
0971 
0972     snprintf(adap->name, sizeof(adap->name),
0973         "SMBus PIIX4 adapter%s at %04x", name, smba);
0974 
0975     i2c_set_adapdata(adap, adapdata);
0976 
0977     retval = i2c_add_adapter(adap);
0978     if (retval) {
0979         kfree(adapdata);
0980         kfree(adap);
0981         release_region(smba, SMBIOSIZE);
0982         return retval;
0983     }
0984 
0985     *padap = adap;
0986     return 0;
0987 }
0988 
0989 static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
0990                     bool notify_imc)
0991 {
0992     struct i2c_piix4_adapdata *adapdata;
0993     int port;
0994     int retval;
0995 
0996     if (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
0997         (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
0998          dev->revision >= 0x1F)) {
0999         piix4_adapter_count = HUDSON2_MAIN_PORTS;
1000     } else {
1001         piix4_adapter_count = PIIX4_MAX_ADAPTERS;
1002     }
1003 
1004     for (port = 0; port < piix4_adapter_count; port++) {
1005         u8 hw_port_nr = port == 0 ? 0 : port + 1;
1006 
1007         retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
1008                        hw_port_nr,
1009                        piix4_main_port_names_sb800[port],
1010                        &piix4_main_adapters[port]);
1011         if (retval < 0)
1012             goto error;
1013     }
1014 
1015     return retval;
1016 
1017 error:
1018     dev_err(&dev->dev,
1019         "Error setting up SB800 adapters. Unregistering!\n");
1020     while (--port >= 0) {
1021         adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
1022         if (adapdata->smba) {
1023             i2c_del_adapter(piix4_main_adapters[port]);
1024             kfree(adapdata);
1025             kfree(piix4_main_adapters[port]);
1026             piix4_main_adapters[port] = NULL;
1027         }
1028     }
1029 
1030     return retval;
1031 }
1032 
1033 static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
1034 {
1035     int retval;
1036     bool is_sb800 = false;
1037 
1038     if ((dev->vendor == PCI_VENDOR_ID_ATI &&
1039          dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
1040          dev->revision >= 0x40) ||
1041         dev->vendor == PCI_VENDOR_ID_AMD ||
1042         dev->vendor == PCI_VENDOR_ID_HYGON) {
1043         bool notify_imc = false;
1044         is_sb800 = true;
1045 
1046         if ((dev->vendor == PCI_VENDOR_ID_AMD ||
1047              dev->vendor == PCI_VENDOR_ID_HYGON) &&
1048             dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
1049             u8 imc;
1050 
1051             /*
1052              * Detect if IMC is active or not, this method is
1053              * described on coreboot's AMD IMC notes
1054              */
1055             pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
1056                          0x40, &imc);
1057             if (imc & 0x80)
1058                 notify_imc = true;
1059         }
1060 
1061         /* base address location etc changed in SB800 */
1062         retval = piix4_setup_sb800(dev, id, 0);
1063         if (retval < 0)
1064             return retval;
1065 
1066         /*
1067          * Try to register multiplexed main SMBus adapter,
1068          * give up if we can't
1069          */
1070         retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
1071         if (retval < 0)
1072             return retval;
1073     } else {
1074         retval = piix4_setup(dev, id);
1075         if (retval < 0)
1076             return retval;
1077 
1078         /* Try to register main SMBus adapter, give up if we can't */
1079         retval = piix4_add_adapter(dev, retval, false, 0, false, 0,
1080                        "", &piix4_main_adapters[0]);
1081         if (retval < 0)
1082             return retval;
1083     }
1084 
1085     /* Check for auxiliary SMBus on some AMD chipsets */
1086     retval = -ENODEV;
1087 
1088     if (dev->vendor == PCI_VENDOR_ID_ATI &&
1089         dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
1090         if (dev->revision < 0x40) {
1091             retval = piix4_setup_aux(dev, id, 0x58);
1092         } else {
1093             /* SB800 added aux bus too */
1094             retval = piix4_setup_sb800(dev, id, 1);
1095         }
1096     }
1097 
1098     if (dev->vendor == PCI_VENDOR_ID_AMD &&
1099         (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS ||
1100          dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) {
1101         retval = piix4_setup_sb800(dev, id, 1);
1102     }
1103 
1104     if (retval > 0) {
1105         /* Try to add the aux adapter if it exists,
1106          * piix4_add_adapter will clean up if this fails */
1107         piix4_add_adapter(dev, retval, false, 0, false, 1,
1108                   is_sb800 ? piix4_aux_port_name_sb800 : "",
1109                   &piix4_aux_adapter);
1110     }
1111 
1112     return 0;
1113 }
1114 
1115 static void piix4_adap_remove(struct i2c_adapter *adap)
1116 {
1117     struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
1118 
1119     if (adapdata->smba) {
1120         i2c_del_adapter(adap);
1121         if (adapdata->port == (0 << piix4_port_shift_sb800))
1122             release_region(adapdata->smba, SMBIOSIZE);
1123         kfree(adapdata);
1124         kfree(adap);
1125     }
1126 }
1127 
1128 static void piix4_remove(struct pci_dev *dev)
1129 {
1130     int port = piix4_adapter_count;
1131 
1132     while (--port >= 0) {
1133         if (piix4_main_adapters[port]) {
1134             piix4_adap_remove(piix4_main_adapters[port]);
1135             piix4_main_adapters[port] = NULL;
1136         }
1137     }
1138 
1139     if (piix4_aux_adapter) {
1140         piix4_adap_remove(piix4_aux_adapter);
1141         piix4_aux_adapter = NULL;
1142     }
1143 }
1144 
1145 static struct pci_driver piix4_driver = {
1146     .name       = "piix4_smbus",
1147     .id_table   = piix4_ids,
1148     .probe      = piix4_probe,
1149     .remove     = piix4_remove,
1150 };
1151 
1152 module_pci_driver(piix4_driver);
1153 
1154 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>");
1155 MODULE_AUTHOR("Philip Edelbrock <phil@netroedge.com>");
1156 MODULE_DESCRIPTION("PIIX4 SMBus driver");
1157 MODULE_LICENSE("GPL");
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