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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Actions Semiconductor Owl SoC's I2C driver
0004  *
0005  * Copyright (c) 2014 Actions Semi Inc.
0006  * Author: David Liu <liuwei@actions-semi.com>
0007  *
0008  * Copyright (c) 2018 Linaro Ltd.
0009  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/i2c.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/iopoll.h>
0018 #include <linux/module.h>
0019 #include <linux/of_device.h>
0020 
0021 /* I2C registers */
0022 #define OWL_I2C_REG_CTL     0x0000
0023 #define OWL_I2C_REG_CLKDIV  0x0004
0024 #define OWL_I2C_REG_STAT    0x0008
0025 #define OWL_I2C_REG_ADDR    0x000C
0026 #define OWL_I2C_REG_TXDAT   0x0010
0027 #define OWL_I2C_REG_RXDAT   0x0014
0028 #define OWL_I2C_REG_CMD     0x0018
0029 #define OWL_I2C_REG_FIFOCTL 0x001C
0030 #define OWL_I2C_REG_FIFOSTAT    0x0020
0031 #define OWL_I2C_REG_DATCNT  0x0024
0032 #define OWL_I2C_REG_RCNT    0x0028
0033 
0034 /* I2Cx_CTL Bit Mask */
0035 #define OWL_I2C_CTL_RB      BIT(1)
0036 #define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2)
0037 #define OWL_I2C_CTL_GBCC_NONE   OWL_I2C_CTL_GBCC(0)
0038 #define OWL_I2C_CTL_GBCC_START  OWL_I2C_CTL_GBCC(1)
0039 #define OWL_I2C_CTL_GBCC_STOP   OWL_I2C_CTL_GBCC(2)
0040 #define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3)
0041 #define OWL_I2C_CTL_IRQE    BIT(5)
0042 #define OWL_I2C_CTL_EN      BIT(7)
0043 #define OWL_I2C_CTL_AE      BIT(8)
0044 #define OWL_I2C_CTL_SHSM    BIT(10)
0045 
0046 #define OWL_I2C_DIV_FACTOR(x)   ((x) & 0xff)
0047 
0048 /* I2Cx_STAT Bit Mask */
0049 #define OWL_I2C_STAT_RACK   BIT(0)
0050 #define OWL_I2C_STAT_BEB    BIT(1)
0051 #define OWL_I2C_STAT_IRQP   BIT(2)
0052 #define OWL_I2C_STAT_LAB    BIT(3)
0053 #define OWL_I2C_STAT_STPD   BIT(4)
0054 #define OWL_I2C_STAT_STAD   BIT(5)
0055 #define OWL_I2C_STAT_BBB    BIT(6)
0056 #define OWL_I2C_STAT_TCB    BIT(7)
0057 #define OWL_I2C_STAT_LBST   BIT(8)
0058 #define OWL_I2C_STAT_SAMB   BIT(9)
0059 #define OWL_I2C_STAT_SRGC   BIT(10)
0060 
0061 /* I2Cx_CMD Bit Mask */
0062 #define OWL_I2C_CMD_SBE     BIT(0)
0063 #define OWL_I2C_CMD_RBE     BIT(4)
0064 #define OWL_I2C_CMD_DE      BIT(8)
0065 #define OWL_I2C_CMD_NS      BIT(9)
0066 #define OWL_I2C_CMD_SE      BIT(10)
0067 #define OWL_I2C_CMD_MSS     BIT(11)
0068 #define OWL_I2C_CMD_WRS     BIT(12)
0069 #define OWL_I2C_CMD_SECL    BIT(15)
0070 
0071 #define OWL_I2C_CMD_AS(x)   (((x) & 0x7) << 1)
0072 #define OWL_I2C_CMD_SAS(x)  (((x) & 0x7) << 5)
0073 
0074 /* I2Cx_FIFOCTL Bit Mask */
0075 #define OWL_I2C_FIFOCTL_NIB BIT(0)
0076 #define OWL_I2C_FIFOCTL_RFR BIT(1)
0077 #define OWL_I2C_FIFOCTL_TFR BIT(2)
0078 
0079 /* I2Cc_FIFOSTAT Bit Mask */
0080 #define OWL_I2C_FIFOSTAT_CECB   BIT(0)
0081 #define OWL_I2C_FIFOSTAT_RNB    BIT(1)
0082 #define OWL_I2C_FIFOSTAT_RFE    BIT(2)
0083 #define OWL_I2C_FIFOSTAT_TFF    BIT(5)
0084 #define OWL_I2C_FIFOSTAT_TFD    GENMASK(23, 16)
0085 #define OWL_I2C_FIFOSTAT_RFD    GENMASK(15, 8)
0086 
0087 /* I2C bus timeout */
0088 #define OWL_I2C_TIMEOUT_MS  (4 * 1000)
0089 #define OWL_I2C_TIMEOUT     msecs_to_jiffies(OWL_I2C_TIMEOUT_MS)
0090 
0091 #define OWL_I2C_MAX_RETRIES 50
0092 
0093 struct owl_i2c_dev {
0094     struct i2c_adapter  adap;
0095     struct i2c_msg      *msg;
0096     struct completion   msg_complete;
0097     struct clk      *clk;
0098     spinlock_t      lock;
0099     void __iomem        *base;
0100     unsigned long       clk_rate;
0101     u32         bus_freq;
0102     u32         msg_ptr;
0103     int         err;
0104 };
0105 
0106 static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state)
0107 {
0108     unsigned int regval;
0109 
0110     regval = readl(reg);
0111 
0112     if (state)
0113         regval |= val;
0114     else
0115         regval &= ~val;
0116 
0117     writel(regval, reg);
0118 }
0119 
0120 static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev)
0121 {
0122     owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
0123                OWL_I2C_CTL_EN, false);
0124     mdelay(1);
0125     owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
0126                OWL_I2C_CTL_EN, true);
0127 
0128     /* Clear status registers */
0129     writel(0, i2c_dev->base + OWL_I2C_REG_STAT);
0130 }
0131 
0132 static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev)
0133 {
0134     unsigned int val, timeout = 0;
0135 
0136     /* Reset FIFO */
0137     owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
0138                OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR,
0139                true);
0140 
0141     /* Wait 50ms for FIFO reset complete */
0142     do {
0143         val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL);
0144         if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR)))
0145             break;
0146         usleep_range(500, 1000);
0147     } while (timeout++ < OWL_I2C_MAX_RETRIES);
0148 
0149     if (timeout > OWL_I2C_MAX_RETRIES) {
0150         dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n");
0151         return -ETIMEDOUT;
0152     }
0153 
0154     return 0;
0155 }
0156 
0157 static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev)
0158 {
0159     unsigned int val;
0160 
0161     val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16);
0162 
0163     /* Set clock divider factor */
0164     writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV);
0165 }
0166 
0167 static void owl_i2c_xfer_data(struct owl_i2c_dev *i2c_dev)
0168 {
0169     struct i2c_msg *msg = i2c_dev->msg;
0170     unsigned int stat, fifostat;
0171 
0172     i2c_dev->err = 0;
0173 
0174     /* Handle NACK from slave */
0175     fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT);
0176     if (fifostat & OWL_I2C_FIFOSTAT_RNB) {
0177         i2c_dev->err = -ENXIO;
0178         /* Clear NACK error bit by writing "1" */
0179         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT,
0180                    OWL_I2C_FIFOSTAT_RNB, true);
0181         return;
0182     }
0183 
0184     /* Handle bus error */
0185     stat = readl(i2c_dev->base + OWL_I2C_REG_STAT);
0186     if (stat & OWL_I2C_STAT_BEB) {
0187         i2c_dev->err = -EIO;
0188         /* Clear BUS error bit by writing "1" */
0189         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
0190                    OWL_I2C_STAT_BEB, true);
0191         return;
0192     }
0193 
0194     /* Handle FIFO read */
0195     if (msg->flags & I2C_M_RD) {
0196         while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
0197             OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) {
0198             msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base +
0199                                  OWL_I2C_REG_RXDAT);
0200         }
0201     } else {
0202         /* Handle the remaining bytes which were not sent */
0203         while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
0204              OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) {
0205             writel(msg->buf[i2c_dev->msg_ptr++],
0206                    i2c_dev->base + OWL_I2C_REG_TXDAT);
0207         }
0208     }
0209 }
0210 
0211 static irqreturn_t owl_i2c_interrupt(int irq, void *_dev)
0212 {
0213     struct owl_i2c_dev *i2c_dev = _dev;
0214 
0215     spin_lock(&i2c_dev->lock);
0216 
0217     owl_i2c_xfer_data(i2c_dev);
0218 
0219     /* Clear pending interrupts */
0220     owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT,
0221                OWL_I2C_STAT_IRQP, true);
0222 
0223     complete_all(&i2c_dev->msg_complete);
0224     spin_unlock(&i2c_dev->lock);
0225 
0226     return IRQ_HANDLED;
0227 }
0228 
0229 static u32 owl_i2c_func(struct i2c_adapter *adap)
0230 {
0231     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0232 }
0233 
0234 static int owl_i2c_check_bus_busy(struct i2c_adapter *adap)
0235 {
0236     struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
0237     unsigned long timeout;
0238 
0239     /* Check for Bus busy */
0240     timeout = jiffies + OWL_I2C_TIMEOUT;
0241     while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) {
0242         if (time_after(jiffies, timeout)) {
0243             dev_err(&adap->dev, "Bus busy timeout\n");
0244             return -ETIMEDOUT;
0245         }
0246     }
0247 
0248     return 0;
0249 }
0250 
0251 static int owl_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg *msgs,
0252                    int num, bool atomic)
0253 {
0254     struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
0255     struct i2c_msg *msg;
0256     unsigned long time_left, flags;
0257     unsigned int i2c_cmd, val;
0258     unsigned int addr;
0259     int ret, idx;
0260 
0261     spin_lock_irqsave(&i2c_dev->lock, flags);
0262 
0263     /* Reset I2C controller */
0264     owl_i2c_reset(i2c_dev);
0265 
0266     /* Set bus frequency */
0267     owl_i2c_set_freq(i2c_dev);
0268 
0269     /*
0270      * Spinlock should be released before calling reset FIFO and
0271      * bus busy check since those functions may sleep
0272      */
0273     spin_unlock_irqrestore(&i2c_dev->lock, flags);
0274 
0275     /* Reset FIFO */
0276     ret = owl_i2c_reset_fifo(i2c_dev);
0277     if (ret)
0278         goto unlocked_err_exit;
0279 
0280     /* Check for bus busy */
0281     ret = owl_i2c_check_bus_busy(adap);
0282     if (ret)
0283         goto unlocked_err_exit;
0284 
0285     spin_lock_irqsave(&i2c_dev->lock, flags);
0286 
0287     /* Check for Arbitration lost */
0288     val = readl(i2c_dev->base + OWL_I2C_REG_STAT);
0289     if (val & OWL_I2C_STAT_LAB) {
0290         val &= ~OWL_I2C_STAT_LAB;
0291         writel(val, i2c_dev->base + OWL_I2C_REG_STAT);
0292         ret = -EAGAIN;
0293         goto err_exit;
0294     }
0295 
0296     if (!atomic)
0297         reinit_completion(&i2c_dev->msg_complete);
0298 
0299     /* Enable/disable I2C controller interrupt */
0300     owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
0301                OWL_I2C_CTL_IRQE, !atomic);
0302 
0303     /*
0304      * Select: FIFO enable, Master mode, Stop enable, Data count enable,
0305      * Send start bit
0306      */
0307     i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE |
0308           OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE;
0309 
0310     /* Handle repeated start condition */
0311     if (num > 1) {
0312         /* Set internal address length and enable repeated start */
0313         i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) |
0314                OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE;
0315 
0316         /* Write slave address */
0317         addr = i2c_8bit_addr_from_msg(&msgs[0]);
0318         writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
0319 
0320         /* Write internal register address */
0321         for (idx = 0; idx < msgs[0].len; idx++)
0322             writel(msgs[0].buf[idx],
0323                    i2c_dev->base + OWL_I2C_REG_TXDAT);
0324 
0325         msg = &msgs[1];
0326     } else {
0327         /* Set address length */
0328         i2c_cmd |= OWL_I2C_CMD_AS(1);
0329         msg = &msgs[0];
0330     }
0331 
0332     i2c_dev->msg = msg;
0333     i2c_dev->msg_ptr = 0;
0334 
0335     /* Set data count for the message */
0336     writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT);
0337 
0338     addr = i2c_8bit_addr_from_msg(msg);
0339     writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT);
0340 
0341     if (!(msg->flags & I2C_M_RD)) {
0342         /* Write data to FIFO */
0343         for (idx = 0; idx < msg->len; idx++) {
0344             /* Check for FIFO full */
0345             if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) &
0346                 OWL_I2C_FIFOSTAT_TFF)
0347                 break;
0348 
0349             writel(msg->buf[idx],
0350                    i2c_dev->base + OWL_I2C_REG_TXDAT);
0351         }
0352 
0353         i2c_dev->msg_ptr = idx;
0354     }
0355 
0356     /* Ignore the NACK if needed */
0357     if (msg->flags & I2C_M_IGNORE_NAK)
0358         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
0359                    OWL_I2C_FIFOCTL_NIB, true);
0360     else
0361         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL,
0362                    OWL_I2C_FIFOCTL_NIB, false);
0363 
0364     /* Start the transfer */
0365     writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD);
0366 
0367     spin_unlock_irqrestore(&i2c_dev->lock, flags);
0368 
0369     if (atomic) {
0370         /* Wait for Command Execute Completed or NACK Error bits */
0371         ret = readl_poll_timeout_atomic(i2c_dev->base + OWL_I2C_REG_FIFOSTAT,
0372                         val, val & (OWL_I2C_FIFOSTAT_CECB |
0373                                 OWL_I2C_FIFOSTAT_RNB),
0374                         10, OWL_I2C_TIMEOUT_MS * 1000);
0375     } else {
0376         time_left = wait_for_completion_timeout(&i2c_dev->msg_complete,
0377                             adap->timeout);
0378         if (!time_left)
0379             ret = -ETIMEDOUT;
0380     }
0381 
0382     spin_lock_irqsave(&i2c_dev->lock, flags);
0383 
0384     if (ret) {
0385         dev_err(&adap->dev, "Transaction timed out\n");
0386         /* Send stop condition and release the bus */
0387         owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
0388                    OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB,
0389                    true);
0390         goto err_exit;
0391     }
0392 
0393     if (atomic)
0394         owl_i2c_xfer_data(i2c_dev);
0395 
0396     ret = i2c_dev->err < 0 ? i2c_dev->err : num;
0397 
0398 err_exit:
0399     spin_unlock_irqrestore(&i2c_dev->lock, flags);
0400 
0401 unlocked_err_exit:
0402     /* Disable I2C controller */
0403     owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL,
0404                OWL_I2C_CTL_EN, false);
0405 
0406     return ret;
0407 }
0408 
0409 static int owl_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
0410             int num)
0411 {
0412     return owl_i2c_xfer_common(adap, msgs, num, false);
0413 }
0414 
0415 static int owl_i2c_xfer_atomic(struct i2c_adapter *adap,
0416                    struct i2c_msg *msgs, int num)
0417 {
0418     return owl_i2c_xfer_common(adap, msgs, num, true);
0419 }
0420 
0421 static const struct i2c_algorithm owl_i2c_algorithm = {
0422     .master_xfer         = owl_i2c_xfer,
0423     .master_xfer_atomic  = owl_i2c_xfer_atomic,
0424     .functionality       = owl_i2c_func,
0425 };
0426 
0427 static const struct i2c_adapter_quirks owl_i2c_quirks = {
0428     .flags      = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST,
0429     .max_read_len   = 240,
0430     .max_write_len  = 240,
0431     .max_comb_1st_msg_len = 6,
0432     .max_comb_2nd_msg_len = 240,
0433 };
0434 
0435 static int owl_i2c_probe(struct platform_device *pdev)
0436 {
0437     struct device *dev = &pdev->dev;
0438     struct owl_i2c_dev *i2c_dev;
0439     int ret, irq;
0440 
0441     i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL);
0442     if (!i2c_dev)
0443         return -ENOMEM;
0444 
0445     i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
0446     if (IS_ERR(i2c_dev->base))
0447         return PTR_ERR(i2c_dev->base);
0448 
0449     irq = platform_get_irq(pdev, 0);
0450     if (irq < 0)
0451         return irq;
0452 
0453     if (of_property_read_u32(dev->of_node, "clock-frequency",
0454                  &i2c_dev->bus_freq))
0455         i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
0456 
0457     /* We support only frequencies of 100k and 400k for now */
0458     if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ &&
0459         i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ) {
0460         dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq);
0461         return -EINVAL;
0462     }
0463 
0464     i2c_dev->clk = devm_clk_get(dev, NULL);
0465     if (IS_ERR(i2c_dev->clk)) {
0466         dev_err(dev, "failed to get clock\n");
0467         return PTR_ERR(i2c_dev->clk);
0468     }
0469 
0470     ret = clk_prepare_enable(i2c_dev->clk);
0471     if (ret)
0472         return ret;
0473 
0474     i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk);
0475     if (!i2c_dev->clk_rate) {
0476         dev_err(dev, "input clock rate should not be zero\n");
0477         ret = -EINVAL;
0478         goto disable_clk;
0479     }
0480 
0481     init_completion(&i2c_dev->msg_complete);
0482     spin_lock_init(&i2c_dev->lock);
0483     i2c_dev->adap.owner = THIS_MODULE;
0484     i2c_dev->adap.algo = &owl_i2c_algorithm;
0485     i2c_dev->adap.timeout = OWL_I2C_TIMEOUT;
0486     i2c_dev->adap.quirks = &owl_i2c_quirks;
0487     i2c_dev->adap.dev.parent = dev;
0488     i2c_dev->adap.dev.of_node = dev->of_node;
0489     snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
0490          "%s", "OWL I2C adapter");
0491     i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
0492 
0493     platform_set_drvdata(pdev, i2c_dev);
0494 
0495     ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name,
0496                    i2c_dev);
0497     if (ret) {
0498         dev_err(dev, "failed to request irq %d\n", irq);
0499         goto disable_clk;
0500     }
0501 
0502     return i2c_add_adapter(&i2c_dev->adap);
0503 
0504 disable_clk:
0505     clk_disable_unprepare(i2c_dev->clk);
0506 
0507     return ret;
0508 }
0509 
0510 static const struct of_device_id owl_i2c_of_match[] = {
0511     { .compatible = "actions,s500-i2c" },
0512     { .compatible = "actions,s700-i2c" },
0513     { .compatible = "actions,s900-i2c" },
0514     { /* sentinel */ }
0515 };
0516 MODULE_DEVICE_TABLE(of, owl_i2c_of_match);
0517 
0518 static struct platform_driver owl_i2c_driver = {
0519     .probe      = owl_i2c_probe,
0520     .driver     = {
0521         .name   = "owl-i2c",
0522         .of_match_table = of_match_ptr(owl_i2c_of_match),
0523         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0524     },
0525 };
0526 module_platform_driver(owl_i2c_driver);
0527 
0528 MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>");
0529 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
0530 MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver");
0531 MODULE_LICENSE("GPL");
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