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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * TI OMAP I2C master mode driver
0004  *
0005  * Copyright (C) 2003 MontaVista Software, Inc.
0006  * Copyright (C) 2005 Nokia Corporation
0007  * Copyright (C) 2004 - 2007 Texas Instruments.
0008  *
0009  * Originally written by MontaVista Software, Inc.
0010  * Additional contributions by:
0011  *  Tony Lindgren <tony@atomide.com>
0012  *  Imre Deak <imre.deak@nokia.com>
0013  *  Juha Yrjölä <juha.yrjola@solidboot.com>
0014  *  Syed Khasim <x0khasim@ti.com>
0015  *  Nishant Menon <nm@ti.com>
0016  */
0017 
0018 #include <linux/module.h>
0019 #include <linux/delay.h>
0020 #include <linux/i2c.h>
0021 #include <linux/err.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/completion.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/clk.h>
0026 #include <linux/io.h>
0027 #include <linux/of.h>
0028 #include <linux/of_device.h>
0029 #include <linux/slab.h>
0030 #include <linux/platform_data/i2c-omap.h>
0031 #include <linux/pm_runtime.h>
0032 #include <linux/pinctrl/consumer.h>
0033 
0034 /* I2C controller revisions */
0035 #define OMAP_I2C_OMAP1_REV_2        0x20
0036 
0037 /* I2C controller revisions present on specific hardware */
0038 #define OMAP_I2C_REV_ON_2430        0x00000036
0039 #define OMAP_I2C_REV_ON_3430_3530   0x0000003C
0040 #define OMAP_I2C_REV_ON_3630        0x00000040
0041 #define OMAP_I2C_REV_ON_4430_PLUS   0x50400002
0042 
0043 /* timeout waiting for the controller to respond */
0044 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
0045 
0046 /* timeout for pm runtime autosuspend */
0047 #define OMAP_I2C_PM_TIMEOUT     1000    /* ms */
0048 
0049 /* timeout for making decision on bus free status */
0050 #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
0051 
0052 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
0053 enum {
0054     OMAP_I2C_REV_REG = 0,
0055     OMAP_I2C_IE_REG,
0056     OMAP_I2C_STAT_REG,
0057     OMAP_I2C_IV_REG,
0058     OMAP_I2C_WE_REG,
0059     OMAP_I2C_SYSS_REG,
0060     OMAP_I2C_BUF_REG,
0061     OMAP_I2C_CNT_REG,
0062     OMAP_I2C_DATA_REG,
0063     OMAP_I2C_SYSC_REG,
0064     OMAP_I2C_CON_REG,
0065     OMAP_I2C_OA_REG,
0066     OMAP_I2C_SA_REG,
0067     OMAP_I2C_PSC_REG,
0068     OMAP_I2C_SCLL_REG,
0069     OMAP_I2C_SCLH_REG,
0070     OMAP_I2C_SYSTEST_REG,
0071     OMAP_I2C_BUFSTAT_REG,
0072     /* only on OMAP4430 */
0073     OMAP_I2C_IP_V2_REVNB_LO,
0074     OMAP_I2C_IP_V2_REVNB_HI,
0075     OMAP_I2C_IP_V2_IRQSTATUS_RAW,
0076     OMAP_I2C_IP_V2_IRQENABLE_SET,
0077     OMAP_I2C_IP_V2_IRQENABLE_CLR,
0078 };
0079 
0080 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
0081 #define OMAP_I2C_IE_XDR     (1 << 14)   /* TX Buffer drain int enable */
0082 #define OMAP_I2C_IE_RDR     (1 << 13)   /* RX Buffer drain int enable */
0083 #define OMAP_I2C_IE_XRDY    (1 << 4)    /* TX data ready int enable */
0084 #define OMAP_I2C_IE_RRDY    (1 << 3)    /* RX data ready int enable */
0085 #define OMAP_I2C_IE_ARDY    (1 << 2)    /* Access ready int enable */
0086 #define OMAP_I2C_IE_NACK    (1 << 1)    /* No ack interrupt enable */
0087 #define OMAP_I2C_IE_AL      (1 << 0)    /* Arbitration lost int ena */
0088 
0089 /* I2C Status Register (OMAP_I2C_STAT): */
0090 #define OMAP_I2C_STAT_XDR   (1 << 14)   /* TX Buffer draining */
0091 #define OMAP_I2C_STAT_RDR   (1 << 13)   /* RX Buffer draining */
0092 #define OMAP_I2C_STAT_BB    (1 << 12)   /* Bus busy */
0093 #define OMAP_I2C_STAT_ROVR  (1 << 11)   /* Receive overrun */
0094 #define OMAP_I2C_STAT_XUDF  (1 << 10)   /* Transmit underflow */
0095 #define OMAP_I2C_STAT_AAS   (1 << 9)    /* Address as slave */
0096 #define OMAP_I2C_STAT_BF    (1 << 8)    /* Bus Free */
0097 #define OMAP_I2C_STAT_XRDY  (1 << 4)    /* Transmit data ready */
0098 #define OMAP_I2C_STAT_RRDY  (1 << 3)    /* Receive data ready */
0099 #define OMAP_I2C_STAT_ARDY  (1 << 2)    /* Register access ready */
0100 #define OMAP_I2C_STAT_NACK  (1 << 1)    /* No ack interrupt enable */
0101 #define OMAP_I2C_STAT_AL    (1 << 0)    /* Arbitration lost int ena */
0102 
0103 /* I2C WE wakeup enable register */
0104 #define OMAP_I2C_WE_XDR_WE  (1 << 14)   /* TX drain wakup */
0105 #define OMAP_I2C_WE_RDR_WE  (1 << 13)   /* RX drain wakeup */
0106 #define OMAP_I2C_WE_AAS_WE  (1 << 9)    /* Address as slave wakeup*/
0107 #define OMAP_I2C_WE_BF_WE   (1 << 8)    /* Bus free wakeup */
0108 #define OMAP_I2C_WE_STC_WE  (1 << 6)    /* Start condition wakeup */
0109 #define OMAP_I2C_WE_GC_WE   (1 << 5)    /* General call wakeup */
0110 #define OMAP_I2C_WE_DRDY_WE (1 << 3)    /* TX/RX data ready wakeup */
0111 #define OMAP_I2C_WE_ARDY_WE (1 << 2)    /* Reg access ready wakeup */
0112 #define OMAP_I2C_WE_NACK_WE (1 << 1)    /* No acknowledgment wakeup */
0113 #define OMAP_I2C_WE_AL_WE   (1 << 0)    /* Arbitration lost wakeup */
0114 
0115 #define OMAP_I2C_WE_ALL     (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
0116                 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
0117                 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
0118                 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
0119                 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
0120 
0121 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
0122 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)   /* RX DMA channel enable */
0123 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)   /* RX FIFO Clear */
0124 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)    /* TX DMA channel enable */
0125 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)    /* TX FIFO Clear */
0126 
0127 /* I2C Configuration Register (OMAP_I2C_CON): */
0128 #define OMAP_I2C_CON_EN     (1 << 15)   /* I2C module enable */
0129 #define OMAP_I2C_CON_BE     (1 << 14)   /* Big endian mode */
0130 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)   /* High Speed support */
0131 #define OMAP_I2C_CON_STB    (1 << 11)   /* Start byte mode (master) */
0132 #define OMAP_I2C_CON_MST    (1 << 10)   /* Master/slave mode */
0133 #define OMAP_I2C_CON_TRX    (1 << 9)    /* TX/RX mode (master only) */
0134 #define OMAP_I2C_CON_XA     (1 << 8)    /* Expand address */
0135 #define OMAP_I2C_CON_RM     (1 << 2)    /* Repeat mode (master only) */
0136 #define OMAP_I2C_CON_STP    (1 << 1)    /* Stop cond (master only) */
0137 #define OMAP_I2C_CON_STT    (1 << 0)    /* Start condition (master) */
0138 
0139 /* I2C SCL time value when Master */
0140 #define OMAP_I2C_SCLL_HSSCLL    8
0141 #define OMAP_I2C_SCLH_HSSCLH    8
0142 
0143 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
0144 #define OMAP_I2C_SYSTEST_ST_EN      (1 << 15)   /* System test enable */
0145 #define OMAP_I2C_SYSTEST_FREE       (1 << 14)   /* Free running mode */
0146 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12)   /* Test mode select */
0147 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)        /* Test mode select */
0148 /* Functional mode */
0149 #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8)    /* SCL line input value */
0150 #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7)    /* SCL line output value */
0151 #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6)    /* SDA line input value */
0152 #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5)    /* SDA line output value */
0153 /* SDA/SCL IO mode */
0154 #define OMAP_I2C_SYSTEST_SCL_I      (1 << 3)    /* SCL line sense in */
0155 #define OMAP_I2C_SYSTEST_SCL_O      (1 << 2)    /* SCL line drive out */
0156 #define OMAP_I2C_SYSTEST_SDA_I      (1 << 1)    /* SDA line sense in */
0157 #define OMAP_I2C_SYSTEST_SDA_O      (1 << 0)    /* SDA line drive out */
0158 
0159 /* OCP_SYSSTATUS bit definitions */
0160 #define SYSS_RESETDONE_MASK     (1 << 0)
0161 
0162 /* OCP_SYSCONFIG bit definitions */
0163 #define SYSC_CLOCKACTIVITY_MASK     (0x3 << 8)
0164 #define SYSC_SIDLEMODE_MASK     (0x3 << 3)
0165 #define SYSC_ENAWAKEUP_MASK     (1 << 2)
0166 #define SYSC_SOFTRESET_MASK     (1 << 1)
0167 #define SYSC_AUTOIDLE_MASK      (1 << 0)
0168 
0169 #define SYSC_IDLEMODE_SMART     0x2
0170 #define SYSC_CLOCKACTIVITY_FCLK     0x2
0171 
0172 /* Errata definitions */
0173 #define I2C_OMAP_ERRATA_I207        (1 << 0)
0174 #define I2C_OMAP_ERRATA_I462        (1 << 1)
0175 
0176 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK  0x6FFF
0177 
0178 struct omap_i2c_dev {
0179     struct device       *dev;
0180     void __iomem        *base;      /* virtual */
0181     int         irq;
0182     int         reg_shift;      /* bit shift for I2C register addresses */
0183     struct completion   cmd_complete;
0184     struct resource     *ioarea;
0185     u32         latency;    /* maximum mpu wkup latency */
0186     void            (*set_mpu_wkup_lat)(struct device *dev,
0187                             long latency);
0188     u32         speed;      /* Speed of bus in kHz */
0189     u32         flags;
0190     u16         scheme;
0191     u16         cmd_err;
0192     u8          *buf;
0193     u8          *regs;
0194     size_t          buf_len;
0195     struct i2c_adapter  adapter;
0196     u8          threshold;
0197     u8          fifo_size;  /* use as flag and value
0198                          * fifo_size==0 implies no fifo
0199                          * if set, should be trsh+1
0200                          */
0201     u32         rev;
0202     unsigned        b_hw:1;     /* bad h/w fixes */
0203     unsigned        bb_valid:1; /* true when BB-bit reflects
0204                          * the I2C bus state
0205                          */
0206     unsigned        receiver:1; /* true when we're in receiver mode */
0207     u16         iestate;    /* Saved interrupt register */
0208     u16         pscstate;
0209     u16         scllstate;
0210     u16         sclhstate;
0211     u16         syscstate;
0212     u16         westate;
0213     u16         errata;
0214 };
0215 
0216 static const u8 reg_map_ip_v1[] = {
0217     [OMAP_I2C_REV_REG] = 0x00,
0218     [OMAP_I2C_IE_REG] = 0x01,
0219     [OMAP_I2C_STAT_REG] = 0x02,
0220     [OMAP_I2C_IV_REG] = 0x03,
0221     [OMAP_I2C_WE_REG] = 0x03,
0222     [OMAP_I2C_SYSS_REG] = 0x04,
0223     [OMAP_I2C_BUF_REG] = 0x05,
0224     [OMAP_I2C_CNT_REG] = 0x06,
0225     [OMAP_I2C_DATA_REG] = 0x07,
0226     [OMAP_I2C_SYSC_REG] = 0x08,
0227     [OMAP_I2C_CON_REG] = 0x09,
0228     [OMAP_I2C_OA_REG] = 0x0a,
0229     [OMAP_I2C_SA_REG] = 0x0b,
0230     [OMAP_I2C_PSC_REG] = 0x0c,
0231     [OMAP_I2C_SCLL_REG] = 0x0d,
0232     [OMAP_I2C_SCLH_REG] = 0x0e,
0233     [OMAP_I2C_SYSTEST_REG] = 0x0f,
0234     [OMAP_I2C_BUFSTAT_REG] = 0x10,
0235 };
0236 
0237 static const u8 reg_map_ip_v2[] = {
0238     [OMAP_I2C_REV_REG] = 0x04,
0239     [OMAP_I2C_IE_REG] = 0x2c,
0240     [OMAP_I2C_STAT_REG] = 0x28,
0241     [OMAP_I2C_IV_REG] = 0x34,
0242     [OMAP_I2C_WE_REG] = 0x34,
0243     [OMAP_I2C_SYSS_REG] = 0x90,
0244     [OMAP_I2C_BUF_REG] = 0x94,
0245     [OMAP_I2C_CNT_REG] = 0x98,
0246     [OMAP_I2C_DATA_REG] = 0x9c,
0247     [OMAP_I2C_SYSC_REG] = 0x10,
0248     [OMAP_I2C_CON_REG] = 0xa4,
0249     [OMAP_I2C_OA_REG] = 0xa8,
0250     [OMAP_I2C_SA_REG] = 0xac,
0251     [OMAP_I2C_PSC_REG] = 0xb0,
0252     [OMAP_I2C_SCLL_REG] = 0xb4,
0253     [OMAP_I2C_SCLH_REG] = 0xb8,
0254     [OMAP_I2C_SYSTEST_REG] = 0xbC,
0255     [OMAP_I2C_BUFSTAT_REG] = 0xc0,
0256     [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
0257     [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
0258     [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
0259     [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
0260     [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
0261 };
0262 
0263 static int omap_i2c_xfer_data(struct omap_i2c_dev *omap);
0264 
0265 static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
0266                       int reg, u16 val)
0267 {
0268     writew_relaxed(val, omap->base +
0269             (omap->regs[reg] << omap->reg_shift));
0270 }
0271 
0272 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
0273 {
0274     return readw_relaxed(omap->base +
0275                 (omap->regs[reg] << omap->reg_shift));
0276 }
0277 
0278 static void __omap_i2c_init(struct omap_i2c_dev *omap)
0279 {
0280 
0281     omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
0282 
0283     /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
0284     omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
0285 
0286     /* SCL low and high time values */
0287     omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
0288     omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
0289     if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
0290         omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
0291 
0292     /* Take the I2C module out of reset: */
0293     omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
0294 
0295     /*
0296      * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
0297      * bus is busy. It will be changed to 1 on the next IP FCLK clock.
0298      * udelay(1) will be enough to fix that.
0299      */
0300 
0301     /*
0302      * Don't write to this register if the IE state is 0 as it can
0303      * cause deadlock.
0304      */
0305     if (omap->iestate)
0306         omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
0307 }
0308 
0309 static int omap_i2c_reset(struct omap_i2c_dev *omap)
0310 {
0311     unsigned long timeout;
0312     u16 sysc;
0313 
0314     if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
0315         sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
0316 
0317         /* Disable I2C controller before soft reset */
0318         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
0319             omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
0320                 ~(OMAP_I2C_CON_EN));
0321 
0322         omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
0323         /* For some reason we need to set the EN bit before the
0324          * reset done bit gets set. */
0325         timeout = jiffies + OMAP_I2C_TIMEOUT;
0326         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
0327         while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
0328              SYSS_RESETDONE_MASK)) {
0329             if (time_after(jiffies, timeout)) {
0330                 dev_warn(omap->dev, "timeout waiting "
0331                         "for controller reset\n");
0332                 return -ETIMEDOUT;
0333             }
0334             msleep(1);
0335         }
0336 
0337         /* SYSC register is cleared by the reset; rewrite it */
0338         omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
0339 
0340         if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
0341             /* Schedule I2C-bus monitoring on the next transfer */
0342             omap->bb_valid = 0;
0343         }
0344     }
0345 
0346     return 0;
0347 }
0348 
0349 static int omap_i2c_init(struct omap_i2c_dev *omap)
0350 {
0351     u16 psc = 0, scll = 0, sclh = 0;
0352     u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
0353     unsigned long fclk_rate = 12000000;
0354     unsigned long internal_clk = 0;
0355     struct clk *fclk;
0356     int error;
0357 
0358     if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
0359         /*
0360          * Enabling all wakup sources to stop I2C freezing on
0361          * WFI instruction.
0362          * REVISIT: Some wkup sources might not be needed.
0363          */
0364         omap->westate = OMAP_I2C_WE_ALL;
0365     }
0366 
0367     if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
0368         /*
0369          * The I2C functional clock is the armxor_ck, so there's
0370          * no need to get "armxor_ck" separately.  Now, if OMAP2420
0371          * always returns 12MHz for the functional clock, we can
0372          * do this bit unconditionally.
0373          */
0374         fclk = clk_get(omap->dev, "fck");
0375         if (IS_ERR(fclk)) {
0376             error = PTR_ERR(fclk);
0377             dev_err(omap->dev, "could not get fck: %i\n", error);
0378 
0379             return error;
0380         }
0381 
0382         fclk_rate = clk_get_rate(fclk);
0383         clk_put(fclk);
0384 
0385         /* TRM for 5912 says the I2C clock must be prescaled to be
0386          * between 7 - 12 MHz. The XOR input clock is typically
0387          * 12, 13 or 19.2 MHz. So we should have code that produces:
0388          *
0389          * XOR MHz  Divider     Prescaler
0390          * 12       1       0
0391          * 13       2       1
0392          * 19.2     2       1
0393          */
0394         if (fclk_rate > 12000000)
0395             psc = fclk_rate / 12000000;
0396     }
0397 
0398     if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
0399 
0400         /*
0401          * HSI2C controller internal clk rate should be 19.2 Mhz for
0402          * HS and for all modes on 2430. On 34xx we can use lower rate
0403          * to get longer filter period for better noise suppression.
0404          * The filter is iclk (fclk for HS) period.
0405          */
0406         if (omap->speed > 400 ||
0407                    omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
0408             internal_clk = 19200;
0409         else if (omap->speed > 100)
0410             internal_clk = 9600;
0411         else
0412             internal_clk = 4000;
0413         fclk = clk_get(omap->dev, "fck");
0414         if (IS_ERR(fclk)) {
0415             error = PTR_ERR(fclk);
0416             dev_err(omap->dev, "could not get fck: %i\n", error);
0417 
0418             return error;
0419         }
0420         fclk_rate = clk_get_rate(fclk) / 1000;
0421         clk_put(fclk);
0422 
0423         /* Compute prescaler divisor */
0424         psc = fclk_rate / internal_clk;
0425         psc = psc - 1;
0426 
0427         /* If configured for High Speed */
0428         if (omap->speed > 400) {
0429             unsigned long scl;
0430 
0431             /* For first phase of HS mode */
0432             scl = internal_clk / 400;
0433             fsscll = scl - (scl / 3) - 7;
0434             fssclh = (scl / 3) - 5;
0435 
0436             /* For second phase of HS mode */
0437             scl = fclk_rate / omap->speed;
0438             hsscll = scl - (scl / 3) - 7;
0439             hssclh = (scl / 3) - 5;
0440         } else if (omap->speed > 100) {
0441             unsigned long scl;
0442 
0443             /* Fast mode */
0444             scl = internal_clk / omap->speed;
0445             fsscll = scl - (scl / 3) - 7;
0446             fssclh = (scl / 3) - 5;
0447         } else {
0448             /* Standard mode */
0449             fsscll = internal_clk / (omap->speed * 2) - 7;
0450             fssclh = internal_clk / (omap->speed * 2) - 5;
0451         }
0452         scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
0453         sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
0454     } else {
0455         /* Program desired operating rate */
0456         fclk_rate /= (psc + 1) * 1000;
0457         if (psc > 2)
0458             psc = 2;
0459         scll = fclk_rate / (omap->speed * 2) - 7 + psc;
0460         sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
0461     }
0462 
0463     omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
0464             OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
0465             OMAP_I2C_IE_AL)  | ((omap->fifo_size) ?
0466                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
0467 
0468     omap->pscstate = psc;
0469     omap->scllstate = scll;
0470     omap->sclhstate = sclh;
0471 
0472     if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
0473         /* Not implemented */
0474         omap->bb_valid = 1;
0475     }
0476 
0477     __omap_i2c_init(omap);
0478 
0479     return 0;
0480 }
0481 
0482 /*
0483  * Try bus recovery, but only if SDA is actually low.
0484  */
0485 static int omap_i2c_recover_bus(struct omap_i2c_dev *omap)
0486 {
0487     u16 systest;
0488 
0489     systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
0490     if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
0491         (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC))
0492         return 0; /* bus seems to already be fine */
0493     if (!(systest & OMAP_I2C_SYSTEST_SCL_I_FUNC))
0494         return -EBUSY; /* recovery would not fix SCL */
0495     return i2c_recover_bus(&omap->adapter);
0496 }
0497 
0498 /*
0499  * Waiting on Bus Busy
0500  */
0501 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
0502 {
0503     unsigned long timeout;
0504 
0505     timeout = jiffies + OMAP_I2C_TIMEOUT;
0506     while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
0507         if (time_after(jiffies, timeout))
0508             return omap_i2c_recover_bus(omap);
0509         msleep(1);
0510     }
0511 
0512     return 0;
0513 }
0514 
0515 /*
0516  * Wait while BB-bit doesn't reflect the I2C bus state
0517  *
0518  * In a multimaster environment, after IP software reset, BB-bit value doesn't
0519  * correspond to the current bus state. It may happen what BB-bit will be 0,
0520  * while the bus is busy due to another I2C master activity.
0521  * Here are BB-bit values after reset:
0522  *     SDA   SCL   BB   NOTES
0523  *       0     0    0   1, 2
0524  *       1     0    0   1, 2
0525  *       0     1    1
0526  *       1     1    0   3
0527  * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
0528  * combinations on the bus, it set BB-bit to 1.
0529  * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
0530  * it set BB-bit to 0 and BF to 1.
0531  * BB and BF bits correctly tracks the bus state while IP is suspended
0532  * BB bit became valid on the next FCLK clock after CON_EN bit set
0533  *
0534  * NOTES:
0535  * 1. Any transfer started when BB=0 and bus is busy wouldn't be
0536  *    completed by IP and results in controller timeout.
0537  * 2. Any transfer started when BB=0 and SCL=0 results in IP
0538  *    starting to drive SDA low. In that case IP corrupt data
0539  *    on the bus.
0540  * 3. Any transfer started in the middle of another master's transfer
0541  *    results in unpredictable results and data corruption
0542  */
0543 static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
0544 {
0545     unsigned long bus_free_timeout = 0;
0546     unsigned long timeout;
0547     int bus_free = 0;
0548     u16 stat, systest;
0549 
0550     if (omap->bb_valid)
0551         return 0;
0552 
0553     timeout = jiffies + OMAP_I2C_TIMEOUT;
0554     while (1) {
0555         stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
0556         /*
0557          * We will see BB or BF event in a case IP had detected any
0558          * activity on the I2C bus. Now IP correctly tracks the bus
0559          * state. BB-bit value is valid.
0560          */
0561         if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
0562             break;
0563 
0564         /*
0565          * Otherwise, we must look signals on the bus to make
0566          * the right decision.
0567          */
0568         systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
0569         if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
0570             (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
0571             if (!bus_free) {
0572                 bus_free_timeout = jiffies +
0573                     OMAP_I2C_BUS_FREE_TIMEOUT;
0574                 bus_free = 1;
0575             }
0576 
0577             /*
0578              * SDA and SCL lines was high for 10 ms without bus
0579              * activity detected. The bus is free. Consider
0580              * BB-bit value is valid.
0581              */
0582             if (time_after(jiffies, bus_free_timeout))
0583                 break;
0584         } else {
0585             bus_free = 0;
0586         }
0587 
0588         if (time_after(jiffies, timeout)) {
0589             /*
0590              * SDA or SCL were low for the entire timeout without
0591              * any activity detected. Most likely, a slave is
0592              * locking up the bus with no master driving the clock.
0593              */
0594             dev_warn(omap->dev, "timeout waiting for bus ready\n");
0595             return omap_i2c_recover_bus(omap);
0596         }
0597 
0598         msleep(1);
0599     }
0600 
0601     omap->bb_valid = 1;
0602     return 0;
0603 }
0604 
0605 static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
0606 {
0607     u16     buf;
0608 
0609     if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
0610         return;
0611 
0612     /*
0613      * Set up notification threshold based on message size. We're doing
0614      * this to try and avoid draining feature as much as possible. Whenever
0615      * we have big messages to transfer (bigger than our total fifo size)
0616      * then we might use draining feature to transfer the remaining bytes.
0617      */
0618 
0619     omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
0620 
0621     buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
0622 
0623     if (is_rx) {
0624         /* Clear RX Threshold */
0625         buf &= ~(0x3f << 8);
0626         buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
0627     } else {
0628         /* Clear TX Threshold */
0629         buf &= ~0x3f;
0630         buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
0631     }
0632 
0633     omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
0634 
0635     if (omap->rev < OMAP_I2C_REV_ON_3630)
0636         omap->b_hw = 1; /* Enable hardware fixes */
0637 
0638     /* calculate wakeup latency constraint for MPU */
0639     if (omap->set_mpu_wkup_lat != NULL)
0640         omap->latency = (1000000 * omap->threshold) /
0641             (1000 * omap->speed / 8);
0642 }
0643 
0644 static void omap_i2c_wait(struct omap_i2c_dev *omap)
0645 {
0646     u16 stat;
0647     u16 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
0648     int count = 0;
0649 
0650     do {
0651         stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
0652         count++;
0653     } while (!(stat & mask) && count < 5);
0654 }
0655 
0656 /*
0657  * Low level master read/write transaction.
0658  */
0659 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
0660                  struct i2c_msg *msg, int stop, bool polling)
0661 {
0662     struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
0663     unsigned long timeout;
0664     u16 w;
0665     int ret;
0666 
0667     dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
0668         msg->addr, msg->len, msg->flags, stop);
0669 
0670     omap->receiver = !!(msg->flags & I2C_M_RD);
0671     omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
0672 
0673     omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
0674 
0675     /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
0676     omap->buf = msg->buf;
0677     omap->buf_len = msg->len;
0678 
0679     /* make sure writes to omap->buf_len are ordered */
0680     barrier();
0681 
0682     omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
0683 
0684     /* Clear the FIFO Buffers */
0685     w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
0686     w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
0687     omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
0688 
0689     if (!polling)
0690         reinit_completion(&omap->cmd_complete);
0691     omap->cmd_err = 0;
0692 
0693     w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
0694 
0695     /* High speed configuration */
0696     if (omap->speed > 400)
0697         w |= OMAP_I2C_CON_OPMODE_HS;
0698 
0699     if (msg->flags & I2C_M_STOP)
0700         stop = 1;
0701     if (msg->flags & I2C_M_TEN)
0702         w |= OMAP_I2C_CON_XA;
0703     if (!(msg->flags & I2C_M_RD))
0704         w |= OMAP_I2C_CON_TRX;
0705 
0706     if (!omap->b_hw && stop)
0707         w |= OMAP_I2C_CON_STP;
0708     /*
0709      * NOTE: STAT_BB bit could became 1 here if another master occupy
0710      * the bus. IP successfully complete transfer when the bus will be
0711      * free again (BB reset to 0).
0712      */
0713     omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
0714 
0715     /*
0716      * Don't write stt and stp together on some hardware.
0717      */
0718     if (omap->b_hw && stop) {
0719         unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
0720         u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
0721         while (con & OMAP_I2C_CON_STT) {
0722             con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
0723 
0724             /* Let the user know if i2c is in a bad state */
0725             if (time_after(jiffies, delay)) {
0726                 dev_err(omap->dev, "controller timed out "
0727                 "waiting for start condition to finish\n");
0728                 return -ETIMEDOUT;
0729             }
0730             cpu_relax();
0731         }
0732 
0733         w |= OMAP_I2C_CON_STP;
0734         w &= ~OMAP_I2C_CON_STT;
0735         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
0736     }
0737 
0738     /*
0739      * REVISIT: We should abort the transfer on signals, but the bus goes
0740      * into arbitration and we're currently unable to recover from it.
0741      */
0742     if (!polling) {
0743         timeout = wait_for_completion_timeout(&omap->cmd_complete,
0744                               OMAP_I2C_TIMEOUT);
0745     } else {
0746         do {
0747             omap_i2c_wait(omap);
0748             ret = omap_i2c_xfer_data(omap);
0749         } while (ret == -EAGAIN);
0750 
0751         timeout = !ret;
0752     }
0753 
0754     if (timeout == 0) {
0755         dev_err(omap->dev, "controller timed out\n");
0756         omap_i2c_reset(omap);
0757         __omap_i2c_init(omap);
0758         return -ETIMEDOUT;
0759     }
0760 
0761     if (likely(!omap->cmd_err))
0762         return 0;
0763 
0764     /* We have an error */
0765     if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
0766         omap_i2c_reset(omap);
0767         __omap_i2c_init(omap);
0768         return -EIO;
0769     }
0770 
0771     if (omap->cmd_err & OMAP_I2C_STAT_AL)
0772         return -EAGAIN;
0773 
0774     if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
0775         if (msg->flags & I2C_M_IGNORE_NAK)
0776             return 0;
0777 
0778         w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
0779         w |= OMAP_I2C_CON_STP;
0780         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
0781         return -EREMOTEIO;
0782     }
0783     return -EIO;
0784 }
0785 
0786 
0787 /*
0788  * Prepare controller for a transaction and call omap_i2c_xfer_msg
0789  * to do the work during IRQ processing.
0790  */
0791 static int
0792 omap_i2c_xfer_common(struct i2c_adapter *adap, struct i2c_msg msgs[], int num,
0793              bool polling)
0794 {
0795     struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
0796     int i;
0797     int r;
0798 
0799     r = pm_runtime_get_sync(omap->dev);
0800     if (r < 0)
0801         goto out;
0802 
0803     r = omap_i2c_wait_for_bb_valid(omap);
0804     if (r < 0)
0805         goto out;
0806 
0807     r = omap_i2c_wait_for_bb(omap);
0808     if (r < 0)
0809         goto out;
0810 
0811     if (omap->set_mpu_wkup_lat != NULL)
0812         omap->set_mpu_wkup_lat(omap->dev, omap->latency);
0813 
0814     for (i = 0; i < num; i++) {
0815         r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)),
0816                       polling);
0817         if (r != 0)
0818             break;
0819     }
0820 
0821     if (r == 0)
0822         r = num;
0823 
0824     omap_i2c_wait_for_bb(omap);
0825 
0826     if (omap->set_mpu_wkup_lat != NULL)
0827         omap->set_mpu_wkup_lat(omap->dev, -1);
0828 
0829 out:
0830     pm_runtime_mark_last_busy(omap->dev);
0831     pm_runtime_put_autosuspend(omap->dev);
0832     return r;
0833 }
0834 
0835 static int
0836 omap_i2c_xfer_irq(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
0837 {
0838     return omap_i2c_xfer_common(adap, msgs, num, false);
0839 }
0840 
0841 static int
0842 omap_i2c_xfer_polling(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
0843 {
0844     return omap_i2c_xfer_common(adap, msgs, num, true);
0845 }
0846 
0847 static u32
0848 omap_i2c_func(struct i2c_adapter *adap)
0849 {
0850     return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
0851            I2C_FUNC_PROTOCOL_MANGLING;
0852 }
0853 
0854 static inline void
0855 omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
0856 {
0857     omap->cmd_err |= err;
0858     complete(&omap->cmd_complete);
0859 }
0860 
0861 static inline void
0862 omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
0863 {
0864     omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
0865 }
0866 
0867 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
0868 {
0869     /*
0870      * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
0871      * Not applicable for OMAP4.
0872      * Under certain rare conditions, RDR could be set again
0873      * when the bus is busy, then ignore the interrupt and
0874      * clear the interrupt.
0875      */
0876     if (stat & OMAP_I2C_STAT_RDR) {
0877         /* Step 1: If RDR is set, clear it */
0878         omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
0879 
0880         /* Step 2: */
0881         if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
0882                         & OMAP_I2C_STAT_BB)) {
0883 
0884             /* Step 3: */
0885             if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
0886                         & OMAP_I2C_STAT_RDR) {
0887                 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
0888                 dev_dbg(omap->dev, "RDR when bus is busy.\n");
0889             }
0890 
0891         }
0892     }
0893 }
0894 
0895 /* rev1 devices are apparently only on some 15xx */
0896 #ifdef CONFIG_ARCH_OMAP15XX
0897 
0898 static irqreturn_t
0899 omap_i2c_omap1_isr(int this_irq, void *dev_id)
0900 {
0901     struct omap_i2c_dev *omap = dev_id;
0902     u16 iv, w;
0903 
0904     if (pm_runtime_suspended(omap->dev))
0905         return IRQ_NONE;
0906 
0907     iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
0908     switch (iv) {
0909     case 0x00:  /* None */
0910         break;
0911     case 0x01:  /* Arbitration lost */
0912         dev_err(omap->dev, "Arbitration lost\n");
0913         omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
0914         break;
0915     case 0x02:  /* No acknowledgement */
0916         omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
0917         omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
0918         break;
0919     case 0x03:  /* Register access ready */
0920         omap_i2c_complete_cmd(omap, 0);
0921         break;
0922     case 0x04:  /* Receive data ready */
0923         if (omap->buf_len) {
0924             w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
0925             *omap->buf++ = w;
0926             omap->buf_len--;
0927             if (omap->buf_len) {
0928                 *omap->buf++ = w >> 8;
0929                 omap->buf_len--;
0930             }
0931         } else
0932             dev_err(omap->dev, "RRDY IRQ while no data requested\n");
0933         break;
0934     case 0x05:  /* Transmit data ready */
0935         if (omap->buf_len) {
0936             w = *omap->buf++;
0937             omap->buf_len--;
0938             if (omap->buf_len) {
0939                 w |= *omap->buf++ << 8;
0940                 omap->buf_len--;
0941             }
0942             omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
0943         } else
0944             dev_err(omap->dev, "XRDY IRQ while no data to send\n");
0945         break;
0946     default:
0947         return IRQ_NONE;
0948     }
0949 
0950     return IRQ_HANDLED;
0951 }
0952 #else
0953 #define omap_i2c_omap1_isr      NULL
0954 #endif
0955 
0956 /*
0957  * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
0958  * data to DATA_REG. Otherwise some data bytes can be lost while transferring
0959  * them from the memory to the I2C interface.
0960  */
0961 static int errata_omap3_i462(struct omap_i2c_dev *omap)
0962 {
0963     unsigned long timeout = 10000;
0964     u16 stat;
0965 
0966     do {
0967         stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
0968         if (stat & OMAP_I2C_STAT_XUDF)
0969             break;
0970 
0971         if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
0972             omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
0973                             OMAP_I2C_STAT_XDR));
0974             if (stat & OMAP_I2C_STAT_NACK) {
0975                 omap->cmd_err |= OMAP_I2C_STAT_NACK;
0976                 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
0977             }
0978 
0979             if (stat & OMAP_I2C_STAT_AL) {
0980                 dev_err(omap->dev, "Arbitration lost\n");
0981                 omap->cmd_err |= OMAP_I2C_STAT_AL;
0982                 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
0983             }
0984 
0985             return -EIO;
0986         }
0987 
0988         cpu_relax();
0989     } while (--timeout);
0990 
0991     if (!timeout) {
0992         dev_err(omap->dev, "timeout waiting on XUDF bit\n");
0993         return 0;
0994     }
0995 
0996     return 0;
0997 }
0998 
0999 static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
1000         bool is_rdr)
1001 {
1002     u16     w;
1003 
1004     while (num_bytes--) {
1005         w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
1006         *omap->buf++ = w;
1007         omap->buf_len--;
1008 
1009         /*
1010          * Data reg in 2430, omap3 and
1011          * omap4 is 8 bit wide
1012          */
1013         if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
1014             *omap->buf++ = w >> 8;
1015             omap->buf_len--;
1016         }
1017     }
1018 }
1019 
1020 static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
1021         bool is_xdr)
1022 {
1023     u16     w;
1024 
1025     while (num_bytes--) {
1026         w = *omap->buf++;
1027         omap->buf_len--;
1028 
1029         /*
1030          * Data reg in 2430, omap3 and
1031          * omap4 is 8 bit wide
1032          */
1033         if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
1034             w |= *omap->buf++ << 8;
1035             omap->buf_len--;
1036         }
1037 
1038         if (omap->errata & I2C_OMAP_ERRATA_I462) {
1039             int ret;
1040 
1041             ret = errata_omap3_i462(omap);
1042             if (ret < 0)
1043                 return ret;
1044         }
1045 
1046         omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
1047     }
1048 
1049     return 0;
1050 }
1051 
1052 static irqreturn_t
1053 omap_i2c_isr(int irq, void *dev_id)
1054 {
1055     struct omap_i2c_dev *omap = dev_id;
1056     irqreturn_t ret = IRQ_HANDLED;
1057     u16 mask;
1058     u16 stat;
1059 
1060     stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1061     mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1062 
1063     if (stat & mask)
1064         ret = IRQ_WAKE_THREAD;
1065 
1066     return ret;
1067 }
1068 
1069 static int omap_i2c_xfer_data(struct omap_i2c_dev *omap)
1070 {
1071     u16 bits;
1072     u16 stat;
1073     int err = 0, count = 0;
1074 
1075     do {
1076         bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1077         stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1078         stat &= bits;
1079 
1080         /* If we're in receiver mode, ignore XDR/XRDY */
1081         if (omap->receiver)
1082             stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1083         else
1084             stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
1085 
1086         if (!stat) {
1087             /* my work here is done */
1088             err = -EAGAIN;
1089             break;
1090         }
1091 
1092         dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
1093         if (count++ == 100) {
1094             dev_warn(omap->dev, "Too much work in one IRQ\n");
1095             break;
1096         }
1097 
1098         if (stat & OMAP_I2C_STAT_NACK) {
1099             err |= OMAP_I2C_STAT_NACK;
1100             omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
1101         }
1102 
1103         if (stat & OMAP_I2C_STAT_AL) {
1104             dev_err(omap->dev, "Arbitration lost\n");
1105             err |= OMAP_I2C_STAT_AL;
1106             omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
1107         }
1108 
1109         /*
1110          * ProDB0017052: Clear ARDY bit twice
1111          */
1112         if (stat & OMAP_I2C_STAT_ARDY)
1113             omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
1114 
1115         if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
1116                     OMAP_I2C_STAT_AL)) {
1117             omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
1118                         OMAP_I2C_STAT_RDR |
1119                         OMAP_I2C_STAT_XRDY |
1120                         OMAP_I2C_STAT_XDR |
1121                         OMAP_I2C_STAT_ARDY));
1122             break;
1123         }
1124 
1125         if (stat & OMAP_I2C_STAT_RDR) {
1126             u8 num_bytes = 1;
1127 
1128             if (omap->fifo_size)
1129                 num_bytes = omap->buf_len;
1130 
1131             if (omap->errata & I2C_OMAP_ERRATA_I207) {
1132                 i2c_omap_errata_i207(omap, stat);
1133                 num_bytes = (omap_i2c_read_reg(omap,
1134                     OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
1135             }
1136 
1137             omap_i2c_receive_data(omap, num_bytes, true);
1138             omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
1139             continue;
1140         }
1141 
1142         if (stat & OMAP_I2C_STAT_RRDY) {
1143             u8 num_bytes = 1;
1144 
1145             if (omap->threshold)
1146                 num_bytes = omap->threshold;
1147 
1148             omap_i2c_receive_data(omap, num_bytes, false);
1149             omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
1150             continue;
1151         }
1152 
1153         if (stat & OMAP_I2C_STAT_XDR) {
1154             u8 num_bytes = 1;
1155             int ret;
1156 
1157             if (omap->fifo_size)
1158                 num_bytes = omap->buf_len;
1159 
1160             ret = omap_i2c_transmit_data(omap, num_bytes, true);
1161             if (ret < 0)
1162                 break;
1163 
1164             omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
1165             continue;
1166         }
1167 
1168         if (stat & OMAP_I2C_STAT_XRDY) {
1169             u8 num_bytes = 1;
1170             int ret;
1171 
1172             if (omap->threshold)
1173                 num_bytes = omap->threshold;
1174 
1175             ret = omap_i2c_transmit_data(omap, num_bytes, false);
1176             if (ret < 0)
1177                 break;
1178 
1179             omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
1180             continue;
1181         }
1182 
1183         if (stat & OMAP_I2C_STAT_ROVR) {
1184             dev_err(omap->dev, "Receive overrun\n");
1185             err |= OMAP_I2C_STAT_ROVR;
1186             omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
1187             break;
1188         }
1189 
1190         if (stat & OMAP_I2C_STAT_XUDF) {
1191             dev_err(omap->dev, "Transmit underflow\n");
1192             err |= OMAP_I2C_STAT_XUDF;
1193             omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
1194             break;
1195         }
1196     } while (stat);
1197 
1198     return err;
1199 }
1200 
1201 static irqreturn_t
1202 omap_i2c_isr_thread(int this_irq, void *dev_id)
1203 {
1204     int ret;
1205     struct omap_i2c_dev *omap = dev_id;
1206 
1207     ret = omap_i2c_xfer_data(omap);
1208     if (ret != -EAGAIN)
1209         omap_i2c_complete_cmd(omap, ret);
1210 
1211     return IRQ_HANDLED;
1212 }
1213 
1214 static const struct i2c_algorithm omap_i2c_algo = {
1215     .master_xfer    = omap_i2c_xfer_irq,
1216     .master_xfer_atomic = omap_i2c_xfer_polling,
1217     .functionality  = omap_i2c_func,
1218 };
1219 
1220 static const struct i2c_adapter_quirks omap_i2c_quirks = {
1221     .flags = I2C_AQ_NO_ZERO_LEN,
1222 };
1223 
1224 #ifdef CONFIG_OF
1225 static struct omap_i2c_bus_platform_data omap2420_pdata = {
1226     .rev = OMAP_I2C_IP_VERSION_1,
1227     .flags = OMAP_I2C_FLAG_NO_FIFO |
1228             OMAP_I2C_FLAG_SIMPLE_CLOCK |
1229             OMAP_I2C_FLAG_16BIT_DATA_REG |
1230             OMAP_I2C_FLAG_BUS_SHIFT_2,
1231 };
1232 
1233 static struct omap_i2c_bus_platform_data omap2430_pdata = {
1234     .rev = OMAP_I2C_IP_VERSION_1,
1235     .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1236             OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1237 };
1238 
1239 static struct omap_i2c_bus_platform_data omap3_pdata = {
1240     .rev = OMAP_I2C_IP_VERSION_1,
1241     .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1242 };
1243 
1244 static struct omap_i2c_bus_platform_data omap4_pdata = {
1245     .rev = OMAP_I2C_IP_VERSION_2,
1246 };
1247 
1248 static const struct of_device_id omap_i2c_of_match[] = {
1249     {
1250         .compatible = "ti,omap4-i2c",
1251         .data = &omap4_pdata,
1252     },
1253     {
1254         .compatible = "ti,omap3-i2c",
1255         .data = &omap3_pdata,
1256     },
1257     {
1258         .compatible = "ti,omap2430-i2c",
1259         .data = &omap2430_pdata,
1260     },
1261     {
1262         .compatible = "ti,omap2420-i2c",
1263         .data = &omap2420_pdata,
1264     },
1265     { },
1266 };
1267 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1268 #endif
1269 
1270 #define OMAP_I2C_SCHEME(rev)        ((rev & 0xc000) >> 14)
1271 
1272 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1273 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1274 
1275 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1276 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1277 #define OMAP_I2C_SCHEME_0       0
1278 #define OMAP_I2C_SCHEME_1       1
1279 
1280 static int omap_i2c_get_scl(struct i2c_adapter *adap)
1281 {
1282     struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1283     u32 reg;
1284 
1285     reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1286 
1287     return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
1288 }
1289 
1290 static int omap_i2c_get_sda(struct i2c_adapter *adap)
1291 {
1292     struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1293     u32 reg;
1294 
1295     reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1296 
1297     return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
1298 }
1299 
1300 static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
1301 {
1302     struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1303     u32 reg;
1304 
1305     reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1306     if (val)
1307         reg |= OMAP_I2C_SYSTEST_SCL_O;
1308     else
1309         reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1310     omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1311 }
1312 
1313 static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
1314 {
1315     struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1316     u32 reg;
1317 
1318     reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1319     /* enable test mode */
1320     reg |= OMAP_I2C_SYSTEST_ST_EN;
1321     /* select SDA/SCL IO mode */
1322     reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
1323     /* set SCL to high-impedance state (reset value is 0) */
1324     reg |= OMAP_I2C_SYSTEST_SCL_O;
1325     /* set SDA to high-impedance state (reset value is 0) */
1326     reg |= OMAP_I2C_SYSTEST_SDA_O;
1327     omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1328 }
1329 
1330 static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
1331 {
1332     struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1333     u32 reg;
1334 
1335     reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1336     /* restore reset values */
1337     reg &= ~OMAP_I2C_SYSTEST_ST_EN;
1338     reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
1339     reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1340     reg &= ~OMAP_I2C_SYSTEST_SDA_O;
1341     omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1342 }
1343 
1344 static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
1345     .get_scl        = omap_i2c_get_scl,
1346     .get_sda        = omap_i2c_get_sda,
1347     .set_scl        = omap_i2c_set_scl,
1348     .prepare_recovery   = omap_i2c_prepare_recovery,
1349     .unprepare_recovery = omap_i2c_unprepare_recovery,
1350     .recover_bus        = i2c_generic_scl_recovery,
1351 };
1352 
1353 static int
1354 omap_i2c_probe(struct platform_device *pdev)
1355 {
1356     struct omap_i2c_dev *omap;
1357     struct i2c_adapter  *adap;
1358     const struct omap_i2c_bus_platform_data *pdata =
1359         dev_get_platdata(&pdev->dev);
1360     struct device_node  *node = pdev->dev.of_node;
1361     const struct of_device_id *match;
1362     int irq;
1363     int r;
1364     u32 rev;
1365     u16 minor, major;
1366 
1367     irq = platform_get_irq(pdev, 0);
1368     if (irq < 0)
1369         return irq;
1370 
1371     omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1372     if (!omap)
1373         return -ENOMEM;
1374 
1375     omap->base = devm_platform_ioremap_resource(pdev, 0);
1376     if (IS_ERR(omap->base))
1377         return PTR_ERR(omap->base);
1378 
1379     match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1380     if (match) {
1381         u32 freq = I2C_MAX_STANDARD_MODE_FREQ;
1382 
1383         pdata = match->data;
1384         omap->flags = pdata->flags;
1385 
1386         of_property_read_u32(node, "clock-frequency", &freq);
1387         /* convert DT freq value in Hz into kHz for speed */
1388         omap->speed = freq / 1000;
1389     } else if (pdata != NULL) {
1390         omap->speed = pdata->clkrate;
1391         omap->flags = pdata->flags;
1392         omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1393     }
1394 
1395     omap->dev = &pdev->dev;
1396     omap->irq = irq;
1397 
1398     platform_set_drvdata(pdev, omap);
1399     init_completion(&omap->cmd_complete);
1400 
1401     omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1402 
1403     pm_runtime_enable(omap->dev);
1404     pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
1405     pm_runtime_use_autosuspend(omap->dev);
1406 
1407     r = pm_runtime_resume_and_get(omap->dev);
1408     if (r < 0)
1409         goto err_disable_pm;
1410 
1411     /*
1412      * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1413      * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1414      * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1415      * readw_relaxed is done.
1416      */
1417     rev = readw_relaxed(omap->base + 0x04);
1418 
1419     omap->scheme = OMAP_I2C_SCHEME(rev);
1420     switch (omap->scheme) {
1421     case OMAP_I2C_SCHEME_0:
1422         omap->regs = (u8 *)reg_map_ip_v1;
1423         omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
1424         minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1425         major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1426         break;
1427     case OMAP_I2C_SCHEME_1:
1428     default:
1429         omap->regs = (u8 *)reg_map_ip_v2;
1430         rev = (rev << 16) |
1431             omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
1432         minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1433         major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1434         omap->rev = rev;
1435     }
1436 
1437     omap->errata = 0;
1438 
1439     if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
1440             omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
1441         omap->errata |= I2C_OMAP_ERRATA_I207;
1442 
1443     if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
1444         omap->errata |= I2C_OMAP_ERRATA_I462;
1445 
1446     if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1447         u16 s;
1448 
1449         /* Set up the fifo size - Get total size */
1450         s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1451         omap->fifo_size = 0x8 << s;
1452 
1453         /*
1454          * Set up notification threshold as half the total available
1455          * size. This is to ensure that we can handle the status on int
1456          * call back latencies.
1457          */
1458 
1459         omap->fifo_size = (omap->fifo_size / 2);
1460 
1461         if (omap->rev < OMAP_I2C_REV_ON_3630)
1462             omap->b_hw = 1; /* Enable hardware fixes */
1463 
1464         /* calculate wakeup latency constraint for MPU */
1465         if (omap->set_mpu_wkup_lat != NULL)
1466             omap->latency = (1000000 * omap->fifo_size) /
1467                        (1000 * omap->speed / 8);
1468     }
1469 
1470     /* reset ASAP, clearing any IRQs */
1471     omap_i2c_init(omap);
1472 
1473     if (omap->rev < OMAP_I2C_OMAP1_REV_2)
1474         r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
1475                 IRQF_NO_SUSPEND, pdev->name, omap);
1476     else
1477         r = devm_request_threaded_irq(&pdev->dev, omap->irq,
1478                 omap_i2c_isr, omap_i2c_isr_thread,
1479                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1480                 pdev->name, omap);
1481 
1482     if (r) {
1483         dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
1484         goto err_unuse_clocks;
1485     }
1486 
1487     adap = &omap->adapter;
1488     i2c_set_adapdata(adap, omap);
1489     adap->owner = THIS_MODULE;
1490     adap->class = I2C_CLASS_DEPRECATED;
1491     strscpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1492     adap->algo = &omap_i2c_algo;
1493     adap->quirks = &omap_i2c_quirks;
1494     adap->dev.parent = &pdev->dev;
1495     adap->dev.of_node = pdev->dev.of_node;
1496     adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
1497 
1498     /* i2c device drivers may be active on return from add_adapter() */
1499     adap->nr = pdev->id;
1500     r = i2c_add_numbered_adapter(adap);
1501     if (r)
1502         goto err_unuse_clocks;
1503 
1504     dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1505          major, minor, omap->speed);
1506 
1507     pm_runtime_mark_last_busy(omap->dev);
1508     pm_runtime_put_autosuspend(omap->dev);
1509 
1510     return 0;
1511 
1512 err_unuse_clocks:
1513     omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1514     pm_runtime_dont_use_autosuspend(omap->dev);
1515     pm_runtime_put_sync(omap->dev);
1516 err_disable_pm:
1517     pm_runtime_disable(&pdev->dev);
1518 
1519     return r;
1520 }
1521 
1522 static int omap_i2c_remove(struct platform_device *pdev)
1523 {
1524     struct omap_i2c_dev *omap = platform_get_drvdata(pdev);
1525     int ret;
1526 
1527     i2c_del_adapter(&omap->adapter);
1528     ret = pm_runtime_resume_and_get(&pdev->dev);
1529     if (ret < 0)
1530         return ret;
1531 
1532     omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1533     pm_runtime_dont_use_autosuspend(&pdev->dev);
1534     pm_runtime_put_sync(&pdev->dev);
1535     pm_runtime_disable(&pdev->dev);
1536     return 0;
1537 }
1538 
1539 static int __maybe_unused omap_i2c_runtime_suspend(struct device *dev)
1540 {
1541     struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1542 
1543     omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1544 
1545     if (omap->scheme == OMAP_I2C_SCHEME_0)
1546         omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
1547     else
1548         omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1549                    OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1550 
1551     if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
1552         omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
1553     } else {
1554         omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
1555 
1556         /* Flush posted write */
1557         omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1558     }
1559 
1560     pinctrl_pm_select_sleep_state(dev);
1561 
1562     return 0;
1563 }
1564 
1565 static int __maybe_unused omap_i2c_runtime_resume(struct device *dev)
1566 {
1567     struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1568 
1569     pinctrl_pm_select_default_state(dev);
1570 
1571     if (!omap->regs)
1572         return 0;
1573 
1574     __omap_i2c_init(omap);
1575 
1576     return 0;
1577 }
1578 
1579 static const struct dev_pm_ops omap_i2c_pm_ops = {
1580     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1581                       pm_runtime_force_resume)
1582     SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1583                omap_i2c_runtime_resume, NULL)
1584 };
1585 
1586 static struct platform_driver omap_i2c_driver = {
1587     .probe      = omap_i2c_probe,
1588     .remove     = omap_i2c_remove,
1589     .driver     = {
1590         .name   = "omap_i2c",
1591         .pm = &omap_i2c_pm_ops,
1592         .of_match_table = of_match_ptr(omap_i2c_of_match),
1593     },
1594 };
1595 
1596 /* I2C may be needed to bring up other drivers */
1597 static int __init
1598 omap_i2c_init_driver(void)
1599 {
1600     return platform_driver_register(&omap_i2c_driver);
1601 }
1602 subsys_initcall(omap_i2c_init_driver);
1603 
1604 static void __exit omap_i2c_exit_driver(void)
1605 {
1606     platform_driver_unregister(&omap_i2c_driver);
1607 }
1608 module_exit(omap_i2c_exit_driver);
1609 
1610 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1611 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1612 MODULE_LICENSE("GPL");
1613 MODULE_ALIAS("platform:omap_i2c");
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