i2c/busses/i2c-octeon-core.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #include <linux/atomic.h>
0003 #include <linux/clk.h>
0004 #include <linux/delay.h>
0005 #include <linux/device.h>
0006 #include <linux/i2c.h>
0007 #include <linux/i2c-smbus.h>
0008 #include <linux/io.h>
0009 #include <linux/kernel.h>
0010
0011 /* Controller command patterns */
0012 #define SW_TWSI_V       BIT_ULL(63) /* Valid bit */
0013 #define SW_TWSI_EIA     BIT_ULL(61) /* Extended internal address */
0014 #define SW_TWSI_R       BIT_ULL(56) /* Result or read bit */
0015 #define SW_TWSI_SOVR        BIT_ULL(55) /* Size override */
0016 #define SW_TWSI_SIZE_SHIFT  52
0017 #define SW_TWSI_ADDR_SHIFT  40
0018 #define SW_TWSI_IA_SHIFT    32      /* Internal address */
0019
0020 /* Controller opcode word (bits 60:57) */
0021 #define SW_TWSI_OP_SHIFT    57
0022 #define SW_TWSI_OP_7        (0ULL << SW_TWSI_OP_SHIFT)
0023 #define SW_TWSI_OP_7_IA     (1ULL << SW_TWSI_OP_SHIFT)
0024 #define SW_TWSI_OP_10       (2ULL << SW_TWSI_OP_SHIFT)
0025 #define SW_TWSI_OP_10_IA    (3ULL << SW_TWSI_OP_SHIFT)
0026 #define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
0027 #define SW_TWSI_OP_EOP      (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
0028
0029 /* Controller extended opcode word (bits 34:32) */
0030 #define SW_TWSI_EOP_SHIFT   32
0031 #define SW_TWSI_EOP_TWSI_DATA   (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
0032 #define SW_TWSI_EOP_TWSI_CTL    (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
0033 #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
0034 #define SW_TWSI_EOP_TWSI_STAT   (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
0035 #define SW_TWSI_EOP_TWSI_RST    (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
0036
0037 /* Controller command and status bits */
0038 #define TWSI_CTL_CE     0x80    /* High level controller enable */
0039 #define TWSI_CTL_ENAB       0x40    /* Bus enable */
0040 #define TWSI_CTL_STA        0x20    /* Master-mode start, HW clears when done */
0041 #define TWSI_CTL_STP        0x10    /* Master-mode stop, HW clears when done */
0042 #define TWSI_CTL_IFLG       0x08    /* HW event, SW writes 0 to ACK */
0043 #define TWSI_CTL_AAK        0x04    /* Assert ACK */
0044
0045 /* Status values */
0046 #define STAT_BUS_ERROR      0x00
0047 #define STAT_START      0x08
0048 #define STAT_REP_START      0x10
0049 #define STAT_TXADDR_ACK     0x18
0050 #define STAT_TXADDR_NAK     0x20
0051 #define STAT_TXDATA_ACK     0x28
0052 #define STAT_TXDATA_NAK     0x30
0053 #define STAT_LOST_ARB_38    0x38
0054 #define STAT_RXADDR_ACK     0x40
0055 #define STAT_RXADDR_NAK     0x48
0056 #define STAT_RXDATA_ACK     0x50
0057 #define STAT_RXDATA_NAK     0x58
0058 #define STAT_SLAVE_60       0x60
0059 #define STAT_LOST_ARB_68    0x68
0060 #define STAT_SLAVE_70       0x70
0061 #define STAT_LOST_ARB_78    0x78
0062 #define STAT_SLAVE_80       0x80
0063 #define STAT_SLAVE_88       0x88
0064 #define STAT_GENDATA_ACK    0x90
0065 #define STAT_GENDATA_NAK    0x98
0066 #define STAT_SLAVE_A0       0xA0
0067 #define STAT_SLAVE_A8       0xA8
0068 #define STAT_LOST_ARB_B0    0xB0
0069 #define STAT_SLAVE_LOST     0xB8
0070 #define STAT_SLAVE_NAK      0xC0
0071 #define STAT_SLAVE_ACK      0xC8
0072 #define STAT_AD2W_ACK       0xD0
0073 #define STAT_AD2W_NAK       0xD8
0074 #define STAT_IDLE       0xF8
0075
0076 /* TWSI_INT values */
0077 #define TWSI_INT_ST_INT     BIT_ULL(0)
0078 #define TWSI_INT_TS_INT     BIT_ULL(1)
0079 #define TWSI_INT_CORE_INT   BIT_ULL(2)
0080 #define TWSI_INT_ST_EN      BIT_ULL(4)
0081 #define TWSI_INT_TS_EN      BIT_ULL(5)
0082 #define TWSI_INT_CORE_EN    BIT_ULL(6)
0083 #define TWSI_INT_SDA_OVR    BIT_ULL(8)
0084 #define TWSI_INT_SCL_OVR    BIT_ULL(9)
0085 #define TWSI_INT_SDA        BIT_ULL(10)
0086 #define TWSI_INT_SCL        BIT_ULL(11)
0087
0088 #define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */
0089
0090 /* Register offsets */
0091 struct octeon_i2c_reg_offset {
0092     unsigned int sw_twsi;
0093     unsigned int twsi_int;
0094     unsigned int sw_twsi_ext;
0095 };
0096
0097 #define SW_TWSI(x)  (x->roff.sw_twsi)
0098 #define TWSI_INT(x) (x->roff.twsi_int)
0099 #define SW_TWSI_EXT(x)  (x->roff.sw_twsi_ext)
0100
0101 struct octeon_i2c {
0102     wait_queue_head_t queue;
0103     struct i2c_adapter adap;
0104     struct octeon_i2c_reg_offset roff;
0105     struct clk *clk;
0106     int irq;
0107     int hlc_irq;        /* For cn7890 only */
0108     u32 twsi_freq;
0109     int sys_freq;
0110     void __iomem *twsi_base;
0111     struct device *dev;
0112     bool hlc_enabled;
0113     bool broken_irq_mode;
0114     bool broken_irq_check;
0115     void (*int_enable)(struct octeon_i2c *);
0116     void (*int_disable)(struct octeon_i2c *);
0117     void (*hlc_int_enable)(struct octeon_i2c *);
0118     void (*hlc_int_disable)(struct octeon_i2c *);
0119     atomic_t int_enable_cnt;
0120     atomic_t hlc_int_enable_cnt;
0121     struct i2c_smbus_alert_setup alert_data;
0122     struct i2c_client *ara;
0123 };
0124
0125 static inline void octeon_i2c_writeq_flush(u64 val, void __iomem *addr)
0126 {
0127     __raw_writeq(val, addr);
0128     __raw_readq(addr);  /* wait for write to land */
0129 }
0130
0131 /**
0132  * octeon_i2c_reg_write - write an I2C core register
0133  * @i2c: The struct octeon_i2c
0134  * @eop_reg: Register selector
0135  * @data: Value to be written
0136  *
0137  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
0138  */
0139 static inline void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data)
0140 {
0141     int tries = 1000;
0142     u64 tmp;
0143
0144     __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI(i2c));
0145     do {
0146         tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
0147         if (--tries < 0)
0148             return;
0149     } while ((tmp & SW_TWSI_V) != 0);
0150 }
0151
0152 #define octeon_i2c_ctl_write(i2c, val)                  \
0153     octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CTL, val)
0154 #define octeon_i2c_data_write(i2c, val)                 \
0155     octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_DATA, val)
0156
0157 /**
0158  * octeon_i2c_reg_read - read lower bits of an I2C core register
0159  * @i2c: The struct octeon_i2c
0160  * @eop_reg: Register selector
0161  *
0162  * Returns the data.
0163  *
0164  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
0165  */
0166 static inline int octeon_i2c_reg_read(struct octeon_i2c *i2c, u64 eop_reg,
0167                       int *error)
0168 {
0169     int tries = 1000;
0170     u64 tmp;
0171
0172     __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI(i2c));
0173     do {
0174         tmp = __raw_readq(i2c->twsi_base + SW_TWSI(i2c));
0175         if (--tries < 0) {
0176             /* signal that the returned data is invalid */
0177             if (error)
0178                 *error = -EIO;
0179             return 0;
0180         }
0181     } while ((tmp & SW_TWSI_V) != 0);
0182
0183     return tmp & 0xFF;
0184 }
0185
0186 #define octeon_i2c_ctl_read(i2c)                    \
0187     octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_CTL, NULL)
0188 #define octeon_i2c_data_read(i2c, error)                \
0189     octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_DATA, error)
0190 #define octeon_i2c_stat_read(i2c)                   \
0191     octeon_i2c_reg_read(i2c, SW_TWSI_EOP_TWSI_STAT, NULL)
0192
0193 /**
0194  * octeon_i2c_read_int - read the TWSI_INT register
0195  * @i2c: The struct octeon_i2c
0196  *
0197  * Returns the value of the register.
0198  */
0199 static inline u64 octeon_i2c_read_int(struct octeon_i2c *i2c)
0200 {
0201     return __raw_readq(i2c->twsi_base + TWSI_INT(i2c));
0202 }
0203
0204 /**
0205  * octeon_i2c_write_int - write the TWSI_INT register
0206  * @i2c: The struct octeon_i2c
0207  * @data: Value to be written
0208  */
0209 static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
0210 {
0211     octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c));
0212 }
0213
0214 /* Prototypes */
0215 irqreturn_t octeon_i2c_isr(int irq, void *dev_id);
0216 int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
0217 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c);
0218 void octeon_i2c_set_clock(struct octeon_i2c *i2c);
0219 extern struct i2c_bus_recovery_info octeon_i2c_recovery_info;