Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
0004  * (https://opencores.org/project/i2c/overview)
0005  *
0006  * Peter Korsgaard <peter@korsgaard.com>
0007  *
0008  * Support for the GRLIB port of the controller by
0009  * Andreas Larsson <andreas@gaisler.com>
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/delay.h>
0014 #include <linux/err.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/errno.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/i2c.h>
0020 #include <linux/interrupt.h>
0021 #include <linux/wait.h>
0022 #include <linux/platform_data/i2c-ocores.h>
0023 #include <linux/slab.h>
0024 #include <linux/io.h>
0025 #include <linux/log2.h>
0026 #include <linux/spinlock.h>
0027 #include <linux/jiffies.h>
0028 
0029 /*
0030  * 'process_lock' exists because ocores_process() and ocores_process_timeout()
0031  * can't run in parallel.
0032  */
0033 struct ocores_i2c {
0034     void __iomem *base;
0035     int iobase;
0036     u32 reg_shift;
0037     u32 reg_io_width;
0038     unsigned long flags;
0039     wait_queue_head_t wait;
0040     struct i2c_adapter adap;
0041     struct i2c_msg *msg;
0042     int pos;
0043     int nmsgs;
0044     int state; /* see STATE_ */
0045     spinlock_t process_lock;
0046     struct clk *clk;
0047     int ip_clock_khz;
0048     int bus_clock_khz;
0049     void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
0050     u8 (*getreg)(struct ocores_i2c *i2c, int reg);
0051 };
0052 
0053 /* registers */
0054 #define OCI2C_PRELOW        0
0055 #define OCI2C_PREHIGH       1
0056 #define OCI2C_CONTROL       2
0057 #define OCI2C_DATA      3
0058 #define OCI2C_CMD       4 /* write only */
0059 #define OCI2C_STATUS        4 /* read only, same address as OCI2C_CMD */
0060 
0061 #define OCI2C_CTRL_IEN      0x40
0062 #define OCI2C_CTRL_EN       0x80
0063 
0064 #define OCI2C_CMD_START     0x91
0065 #define OCI2C_CMD_STOP      0x41
0066 #define OCI2C_CMD_READ      0x21
0067 #define OCI2C_CMD_WRITE     0x11
0068 #define OCI2C_CMD_READ_ACK  0x21
0069 #define OCI2C_CMD_READ_NACK 0x29
0070 #define OCI2C_CMD_IACK      0x01
0071 
0072 #define OCI2C_STAT_IF       0x01
0073 #define OCI2C_STAT_TIP      0x02
0074 #define OCI2C_STAT_ARBLOST  0x20
0075 #define OCI2C_STAT_BUSY     0x40
0076 #define OCI2C_STAT_NACK     0x80
0077 
0078 #define STATE_DONE      0
0079 #define STATE_START     1
0080 #define STATE_WRITE     2
0081 #define STATE_READ      3
0082 #define STATE_ERROR     4
0083 
0084 #define TYPE_OCORES     0
0085 #define TYPE_GRLIB      1
0086 
0087 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
0088 
0089 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
0090 {
0091     iowrite8(value, i2c->base + (reg << i2c->reg_shift));
0092 }
0093 
0094 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
0095 {
0096     iowrite16(value, i2c->base + (reg << i2c->reg_shift));
0097 }
0098 
0099 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
0100 {
0101     iowrite32(value, i2c->base + (reg << i2c->reg_shift));
0102 }
0103 
0104 static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value)
0105 {
0106     iowrite16be(value, i2c->base + (reg << i2c->reg_shift));
0107 }
0108 
0109 static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value)
0110 {
0111     iowrite32be(value, i2c->base + (reg << i2c->reg_shift));
0112 }
0113 
0114 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
0115 {
0116     return ioread8(i2c->base + (reg << i2c->reg_shift));
0117 }
0118 
0119 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
0120 {
0121     return ioread16(i2c->base + (reg << i2c->reg_shift));
0122 }
0123 
0124 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
0125 {
0126     return ioread32(i2c->base + (reg << i2c->reg_shift));
0127 }
0128 
0129 static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg)
0130 {
0131     return ioread16be(i2c->base + (reg << i2c->reg_shift));
0132 }
0133 
0134 static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg)
0135 {
0136     return ioread32be(i2c->base + (reg << i2c->reg_shift));
0137 }
0138 
0139 static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value)
0140 {
0141     outb(value, i2c->iobase + reg);
0142 }
0143 
0144 static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg)
0145 {
0146     return inb(i2c->iobase + reg);
0147 }
0148 
0149 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
0150 {
0151     i2c->setreg(i2c, reg, value);
0152 }
0153 
0154 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
0155 {
0156     return i2c->getreg(i2c, reg);
0157 }
0158 
0159 static void ocores_process(struct ocores_i2c *i2c, u8 stat)
0160 {
0161     struct i2c_msg *msg = i2c->msg;
0162     unsigned long flags;
0163 
0164     /*
0165      * If we spin here is because we are in timeout, so we are going
0166      * to be in STATE_ERROR. See ocores_process_timeout()
0167      */
0168     spin_lock_irqsave(&i2c->process_lock, flags);
0169 
0170     if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
0171         /* stop has been sent */
0172         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
0173         wake_up(&i2c->wait);
0174         goto out;
0175     }
0176 
0177     /* error? */
0178     if (stat & OCI2C_STAT_ARBLOST) {
0179         i2c->state = STATE_ERROR;
0180         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
0181         goto out;
0182     }
0183 
0184     if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
0185         i2c->state =
0186             (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
0187 
0188         if (stat & OCI2C_STAT_NACK) {
0189             i2c->state = STATE_ERROR;
0190             oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
0191             goto out;
0192         }
0193     } else {
0194         msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
0195     }
0196 
0197     /* end of msg? */
0198     if (i2c->pos == msg->len) {
0199         i2c->nmsgs--;
0200         i2c->msg++;
0201         i2c->pos = 0;
0202         msg = i2c->msg;
0203 
0204         if (i2c->nmsgs) {   /* end? */
0205             /* send start? */
0206             if (!(msg->flags & I2C_M_NOSTART)) {
0207                 u8 addr = i2c_8bit_addr_from_msg(msg);
0208 
0209                 i2c->state = STATE_START;
0210 
0211                 oc_setreg(i2c, OCI2C_DATA, addr);
0212                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
0213                 goto out;
0214             }
0215             i2c->state = (msg->flags & I2C_M_RD)
0216                 ? STATE_READ : STATE_WRITE;
0217         } else {
0218             i2c->state = STATE_DONE;
0219             oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
0220             goto out;
0221         }
0222     }
0223 
0224     if (i2c->state == STATE_READ) {
0225         oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
0226               OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
0227     } else {
0228         oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
0229         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
0230     }
0231 
0232 out:
0233     spin_unlock_irqrestore(&i2c->process_lock, flags);
0234 }
0235 
0236 static irqreturn_t ocores_isr(int irq, void *dev_id)
0237 {
0238     struct ocores_i2c *i2c = dev_id;
0239     u8 stat = oc_getreg(i2c, OCI2C_STATUS);
0240 
0241     if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
0242         if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
0243             return IRQ_NONE;
0244     } else if (!(stat & OCI2C_STAT_IF)) {
0245         return IRQ_NONE;
0246     }
0247     ocores_process(i2c, stat);
0248 
0249     return IRQ_HANDLED;
0250 }
0251 
0252 /**
0253  * ocores_process_timeout() - Process timeout event
0254  * @i2c: ocores I2C device instance
0255  */
0256 static void ocores_process_timeout(struct ocores_i2c *i2c)
0257 {
0258     unsigned long flags;
0259 
0260     spin_lock_irqsave(&i2c->process_lock, flags);
0261     i2c->state = STATE_ERROR;
0262     oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
0263     spin_unlock_irqrestore(&i2c->process_lock, flags);
0264 }
0265 
0266 /**
0267  * ocores_wait() - Wait until something change in a given register
0268  * @i2c: ocores I2C device instance
0269  * @reg: register to query
0270  * @mask: bitmask to apply on register value
0271  * @val: expected result
0272  * @timeout: timeout in jiffies
0273  *
0274  * Timeout is necessary to avoid to stay here forever when the chip
0275  * does not answer correctly.
0276  *
0277  * Return: 0 on success, -ETIMEDOUT on timeout
0278  */
0279 static int ocores_wait(struct ocores_i2c *i2c,
0280                int reg, u8 mask, u8 val,
0281                const unsigned long timeout)
0282 {
0283     unsigned long j;
0284 
0285     j = jiffies + timeout;
0286     while (1) {
0287         u8 status = oc_getreg(i2c, reg);
0288 
0289         if ((status & mask) == val)
0290             break;
0291 
0292         if (time_after(jiffies, j))
0293             return -ETIMEDOUT;
0294     }
0295     return 0;
0296 }
0297 
0298 /**
0299  * ocores_poll_wait() - Wait until is possible to process some data
0300  * @i2c: ocores I2C device instance
0301  *
0302  * Used when the device is in polling mode (interrupts disabled).
0303  *
0304  * Return: 0 on success, -ETIMEDOUT on timeout
0305  */
0306 static int ocores_poll_wait(struct ocores_i2c *i2c)
0307 {
0308     u8 mask;
0309     int err;
0310 
0311     if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
0312         /* transfer is over */
0313         mask = OCI2C_STAT_BUSY;
0314     } else {
0315         /* on going transfer */
0316         mask = OCI2C_STAT_TIP;
0317         /*
0318          * We wait for the data to be transferred (8bit),
0319          * then we start polling on the ACK/NACK bit
0320          */
0321         udelay((8 * 1000) / i2c->bus_clock_khz);
0322     }
0323 
0324     /*
0325      * once we are here we expect to get the expected result immediately
0326      * so if after 1ms we timeout then something is broken.
0327      */
0328     err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1));
0329     if (err)
0330         dev_warn(i2c->adap.dev.parent,
0331              "%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
0332              __func__, mask);
0333     return err;
0334 }
0335 
0336 /**
0337  * ocores_process_polling() - It handles an IRQ-less transfer
0338  * @i2c: ocores I2C device instance
0339  *
0340  * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
0341  * (only that IRQ are not produced). This means that we can re-use entirely
0342  * ocores_isr(), we just add our polling code around it.
0343  *
0344  * It can run in atomic context
0345  */
0346 static void ocores_process_polling(struct ocores_i2c *i2c)
0347 {
0348     while (1) {
0349         irqreturn_t ret;
0350         int err;
0351 
0352         err = ocores_poll_wait(i2c);
0353         if (err) {
0354             i2c->state = STATE_ERROR;
0355             break; /* timeout */
0356         }
0357 
0358         ret = ocores_isr(-1, i2c);
0359         if (ret == IRQ_NONE)
0360             break; /* all messages have been transferred */
0361         else {
0362             if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
0363                 if (i2c->state == STATE_DONE)
0364                     break;
0365         }
0366     }
0367 }
0368 
0369 static int ocores_xfer_core(struct ocores_i2c *i2c,
0370                 struct i2c_msg *msgs, int num,
0371                 bool polling)
0372 {
0373     int ret;
0374     u8 ctrl;
0375 
0376     ctrl = oc_getreg(i2c, OCI2C_CONTROL);
0377     if (polling)
0378         oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
0379     else
0380         oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN);
0381 
0382     i2c->msg = msgs;
0383     i2c->pos = 0;
0384     i2c->nmsgs = num;
0385     i2c->state = STATE_START;
0386 
0387     oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
0388     oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
0389 
0390     if (polling) {
0391         ocores_process_polling(i2c);
0392     } else {
0393         ret = wait_event_timeout(i2c->wait,
0394                      (i2c->state == STATE_ERROR) ||
0395                      (i2c->state == STATE_DONE), HZ);
0396         if (ret == 0) {
0397             ocores_process_timeout(i2c);
0398             return -ETIMEDOUT;
0399         }
0400     }
0401 
0402     return (i2c->state == STATE_DONE) ? num : -EIO;
0403 }
0404 
0405 static int ocores_xfer_polling(struct i2c_adapter *adap,
0406                    struct i2c_msg *msgs, int num)
0407 {
0408     return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true);
0409 }
0410 
0411 static int ocores_xfer(struct i2c_adapter *adap,
0412                struct i2c_msg *msgs, int num)
0413 {
0414     return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false);
0415 }
0416 
0417 static int ocores_init(struct device *dev, struct ocores_i2c *i2c)
0418 {
0419     int prescale;
0420     int diff;
0421     u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
0422 
0423     /* make sure the device is disabled */
0424     ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
0425     oc_setreg(i2c, OCI2C_CONTROL, ctrl);
0426 
0427     prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1;
0428     prescale = clamp(prescale, 0, 0xffff);
0429 
0430     diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz;
0431     if (abs(diff) > i2c->bus_clock_khz / 10) {
0432         dev_err(dev,
0433             "Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
0434             i2c->ip_clock_khz, i2c->bus_clock_khz);
0435         return -EINVAL;
0436     }
0437 
0438     oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
0439     oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
0440 
0441     /* Init the device */
0442     oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
0443     oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
0444 
0445     return 0;
0446 }
0447 
0448 
0449 static u32 ocores_func(struct i2c_adapter *adap)
0450 {
0451     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0452 }
0453 
0454 static struct i2c_algorithm ocores_algorithm = {
0455     .master_xfer = ocores_xfer,
0456     .master_xfer_atomic = ocores_xfer_polling,
0457     .functionality = ocores_func,
0458 };
0459 
0460 static const struct i2c_adapter ocores_adapter = {
0461     .owner = THIS_MODULE,
0462     .name = "i2c-ocores",
0463     .class = I2C_CLASS_DEPRECATED,
0464     .algo = &ocores_algorithm,
0465 };
0466 
0467 static const struct of_device_id ocores_i2c_match[] = {
0468     {
0469         .compatible = "opencores,i2c-ocores",
0470         .data = (void *)TYPE_OCORES,
0471     },
0472     {
0473         .compatible = "aeroflexgaisler,i2cmst",
0474         .data = (void *)TYPE_GRLIB,
0475     },
0476     {
0477         .compatible = "sifive,fu540-c000-i2c",
0478     },
0479     {
0480         .compatible = "sifive,i2c0",
0481     },
0482     {},
0483 };
0484 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
0485 
0486 #ifdef CONFIG_OF
0487 /*
0488  * Read and write functions for the GRLIB port of the controller. Registers are
0489  * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
0490  * register. The subsequent registers have their offsets decreased accordingly.
0491  */
0492 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
0493 {
0494     u32 rd;
0495     int rreg = reg;
0496 
0497     if (reg != OCI2C_PRELOW)
0498         rreg--;
0499     rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
0500     if (reg == OCI2C_PREHIGH)
0501         return (u8)(rd >> 8);
0502     else
0503         return (u8)rd;
0504 }
0505 
0506 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
0507 {
0508     u32 curr, wr;
0509     int rreg = reg;
0510 
0511     if (reg != OCI2C_PRELOW)
0512         rreg--;
0513     if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
0514         curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
0515         if (reg == OCI2C_PRELOW)
0516             wr = (curr & 0xff00) | value;
0517         else
0518             wr = (((u32)value) << 8) | (curr & 0xff);
0519     } else {
0520         wr = value;
0521     }
0522     iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
0523 }
0524 
0525 static int ocores_i2c_of_probe(struct platform_device *pdev,
0526                 struct ocores_i2c *i2c)
0527 {
0528     struct device_node *np = pdev->dev.of_node;
0529     const struct of_device_id *match;
0530     u32 val;
0531     u32 clock_frequency;
0532     bool clock_frequency_present;
0533 
0534     if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
0535         /* no 'reg-shift', check for deprecated 'regstep' */
0536         if (!of_property_read_u32(np, "regstep", &val)) {
0537             if (!is_power_of_2(val)) {
0538                 dev_err(&pdev->dev, "invalid regstep %d\n",
0539                     val);
0540                 return -EINVAL;
0541             }
0542             i2c->reg_shift = ilog2(val);
0543             dev_warn(&pdev->dev,
0544                 "regstep property deprecated, use reg-shift\n");
0545         }
0546     }
0547 
0548     clock_frequency_present = !of_property_read_u32(np, "clock-frequency",
0549                             &clock_frequency);
0550     i2c->bus_clock_khz = 100;
0551 
0552     i2c->clk = devm_clk_get(&pdev->dev, NULL);
0553 
0554     if (!IS_ERR(i2c->clk)) {
0555         int ret = clk_prepare_enable(i2c->clk);
0556 
0557         if (ret) {
0558             dev_err(&pdev->dev,
0559                 "clk_prepare_enable failed: %d\n", ret);
0560             return ret;
0561         }
0562         i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000;
0563         if (clock_frequency_present)
0564             i2c->bus_clock_khz = clock_frequency / 1000;
0565     }
0566 
0567     if (i2c->ip_clock_khz == 0) {
0568         if (of_property_read_u32(np, "opencores,ip-clock-frequency",
0569                         &val)) {
0570             if (!clock_frequency_present) {
0571                 dev_err(&pdev->dev,
0572                     "Missing required parameter 'opencores,ip-clock-frequency'\n");
0573                 clk_disable_unprepare(i2c->clk);
0574                 return -ENODEV;
0575             }
0576             i2c->ip_clock_khz = clock_frequency / 1000;
0577             dev_warn(&pdev->dev,
0578                  "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
0579         } else {
0580             i2c->ip_clock_khz = val / 1000;
0581             if (clock_frequency_present)
0582                 i2c->bus_clock_khz = clock_frequency / 1000;
0583         }
0584     }
0585 
0586     of_property_read_u32(pdev->dev.of_node, "reg-io-width",
0587                 &i2c->reg_io_width);
0588 
0589     match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
0590     if (match && (long)match->data == TYPE_GRLIB) {
0591         dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
0592         i2c->setreg = oc_setreg_grlib;
0593         i2c->getreg = oc_getreg_grlib;
0594     }
0595 
0596     return 0;
0597 }
0598 #else
0599 #define ocores_i2c_of_probe(pdev, i2c) -ENODEV
0600 #endif
0601 
0602 static int ocores_i2c_probe(struct platform_device *pdev)
0603 {
0604     struct ocores_i2c *i2c;
0605     struct ocores_i2c_platform_data *pdata;
0606     struct resource *res;
0607     int irq;
0608     int ret;
0609     int i;
0610 
0611     i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
0612     if (!i2c)
0613         return -ENOMEM;
0614 
0615     spin_lock_init(&i2c->process_lock);
0616 
0617     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0618     if (res) {
0619         i2c->base = devm_ioremap_resource(&pdev->dev, res);
0620         if (IS_ERR(i2c->base))
0621             return PTR_ERR(i2c->base);
0622     } else {
0623         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
0624         if (!res)
0625             return -EINVAL;
0626         i2c->iobase = res->start;
0627         if (!devm_request_region(&pdev->dev, res->start,
0628                      resource_size(res),
0629                      pdev->name)) {
0630             dev_err(&pdev->dev, "Can't get I/O resource.\n");
0631             return -EBUSY;
0632         }
0633         i2c->setreg = oc_setreg_io_8;
0634         i2c->getreg = oc_getreg_io_8;
0635     }
0636 
0637     pdata = dev_get_platdata(&pdev->dev);
0638     if (pdata) {
0639         i2c->reg_shift = pdata->reg_shift;
0640         i2c->reg_io_width = pdata->reg_io_width;
0641         i2c->ip_clock_khz = pdata->clock_khz;
0642         if (pdata->bus_khz)
0643             i2c->bus_clock_khz = pdata->bus_khz;
0644         else
0645             i2c->bus_clock_khz = 100;
0646     } else {
0647         ret = ocores_i2c_of_probe(pdev, i2c);
0648         if (ret)
0649             return ret;
0650     }
0651 
0652     if (i2c->reg_io_width == 0)
0653         i2c->reg_io_width = 1; /* Set to default value */
0654 
0655     if (!i2c->setreg || !i2c->getreg) {
0656         bool be = pdata ? pdata->big_endian :
0657             of_device_is_big_endian(pdev->dev.of_node);
0658 
0659         switch (i2c->reg_io_width) {
0660         case 1:
0661             i2c->setreg = oc_setreg_8;
0662             i2c->getreg = oc_getreg_8;
0663             break;
0664 
0665         case 2:
0666             i2c->setreg = be ? oc_setreg_16be : oc_setreg_16;
0667             i2c->getreg = be ? oc_getreg_16be : oc_getreg_16;
0668             break;
0669 
0670         case 4:
0671             i2c->setreg = be ? oc_setreg_32be : oc_setreg_32;
0672             i2c->getreg = be ? oc_getreg_32be : oc_getreg_32;
0673             break;
0674 
0675         default:
0676             dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
0677                 i2c->reg_io_width);
0678             ret = -EINVAL;
0679             goto err_clk;
0680         }
0681     }
0682 
0683     init_waitqueue_head(&i2c->wait);
0684 
0685     irq = platform_get_irq_optional(pdev, 0);
0686     /*
0687      * Since the SoC does have an interrupt, its DT has an interrupt
0688      * property - But this should be bypassed as the IRQ logic in this
0689      * SoC is broken.
0690      */
0691     if (of_device_is_compatible(pdev->dev.of_node,
0692                     "sifive,fu540-c000-i2c")) {
0693         i2c->flags |= OCORES_FLAG_BROKEN_IRQ;
0694         irq = -ENXIO;
0695     }
0696 
0697     if (irq == -ENXIO) {
0698         ocores_algorithm.master_xfer = ocores_xfer_polling;
0699     } else {
0700         if (irq < 0)
0701             return irq;
0702     }
0703 
0704     if (ocores_algorithm.master_xfer != ocores_xfer_polling) {
0705         ret = devm_request_any_context_irq(&pdev->dev, irq,
0706                            ocores_isr, 0,
0707                            pdev->name, i2c);
0708         if (ret) {
0709             dev_err(&pdev->dev, "Cannot claim IRQ\n");
0710             goto err_clk;
0711         }
0712     }
0713 
0714     ret = ocores_init(&pdev->dev, i2c);
0715     if (ret)
0716         goto err_clk;
0717 
0718     /* hook up driver to tree */
0719     platform_set_drvdata(pdev, i2c);
0720     i2c->adap = ocores_adapter;
0721     i2c_set_adapdata(&i2c->adap, i2c);
0722     i2c->adap.dev.parent = &pdev->dev;
0723     i2c->adap.dev.of_node = pdev->dev.of_node;
0724 
0725     /* add i2c adapter to i2c tree */
0726     ret = i2c_add_adapter(&i2c->adap);
0727     if (ret)
0728         goto err_clk;
0729 
0730     /* add in known devices to the bus */
0731     if (pdata) {
0732         for (i = 0; i < pdata->num_devices; i++)
0733             i2c_new_client_device(&i2c->adap, pdata->devices + i);
0734     }
0735 
0736     return 0;
0737 
0738 err_clk:
0739     clk_disable_unprepare(i2c->clk);
0740     return ret;
0741 }
0742 
0743 static int ocores_i2c_remove(struct platform_device *pdev)
0744 {
0745     struct ocores_i2c *i2c = platform_get_drvdata(pdev);
0746     u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
0747 
0748     /* disable i2c logic */
0749     ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
0750     oc_setreg(i2c, OCI2C_CONTROL, ctrl);
0751 
0752     /* remove adapter & data */
0753     i2c_del_adapter(&i2c->adap);
0754 
0755     if (!IS_ERR(i2c->clk))
0756         clk_disable_unprepare(i2c->clk);
0757 
0758     return 0;
0759 }
0760 
0761 #ifdef CONFIG_PM_SLEEP
0762 static int ocores_i2c_suspend(struct device *dev)
0763 {
0764     struct ocores_i2c *i2c = dev_get_drvdata(dev);
0765     u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
0766 
0767     /* make sure the device is disabled */
0768     ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
0769     oc_setreg(i2c, OCI2C_CONTROL, ctrl);
0770 
0771     if (!IS_ERR(i2c->clk))
0772         clk_disable_unprepare(i2c->clk);
0773     return 0;
0774 }
0775 
0776 static int ocores_i2c_resume(struct device *dev)
0777 {
0778     struct ocores_i2c *i2c = dev_get_drvdata(dev);
0779 
0780     if (!IS_ERR(i2c->clk)) {
0781         unsigned long rate;
0782         int ret = clk_prepare_enable(i2c->clk);
0783 
0784         if (ret) {
0785             dev_err(dev,
0786                 "clk_prepare_enable failed: %d\n", ret);
0787             return ret;
0788         }
0789         rate = clk_get_rate(i2c->clk) / 1000;
0790         if (rate)
0791             i2c->ip_clock_khz = rate;
0792     }
0793     return ocores_init(dev, i2c);
0794 }
0795 
0796 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
0797 #define OCORES_I2C_PM   (&ocores_i2c_pm)
0798 #else
0799 #define OCORES_I2C_PM   NULL
0800 #endif
0801 
0802 static struct platform_driver ocores_i2c_driver = {
0803     .probe   = ocores_i2c_probe,
0804     .remove  = ocores_i2c_remove,
0805     .driver  = {
0806         .name = "ocores-i2c",
0807         .of_match_table = ocores_i2c_match,
0808         .pm = OCORES_I2C_PM,
0809     },
0810 };
0811 
0812 module_platform_driver(ocores_i2c_driver);
0813 
0814 MODULE_AUTHOR("Peter Korsgaard <peter@korsgaard.com>");
0815 MODULE_DESCRIPTION("OpenCores I2C bus driver");
0816 MODULE_LICENSE("GPL");
0817 MODULE_ALIAS("platform:ocores-i2c");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!