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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2009 ST-Ericsson SA
0004  * Copyright (C) 2009 STMicroelectronics
0005  *
0006  * I2C master mode controller driver, used in Nomadik 8815
0007  * and Ux500 platforms.
0008  *
0009  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
0010  * Author: Sachin Verma <sachin.verma@st.com>
0011  */
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/amba/bus.h>
0015 #include <linux/slab.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/i2c.h>
0018 #include <linux/err.h>
0019 #include <linux/clk.h>
0020 #include <linux/io.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/of.h>
0023 #include <linux/pinctrl/consumer.h>
0024 
0025 #define DRIVER_NAME "nmk-i2c"
0026 
0027 /* I2C Controller register offsets */
0028 #define I2C_CR      (0x000)
0029 #define I2C_SCR     (0x004)
0030 #define I2C_HSMCR   (0x008)
0031 #define I2C_MCR     (0x00C)
0032 #define I2C_TFR     (0x010)
0033 #define I2C_SR      (0x014)
0034 #define I2C_RFR     (0x018)
0035 #define I2C_TFTR    (0x01C)
0036 #define I2C_RFTR    (0x020)
0037 #define I2C_DMAR    (0x024)
0038 #define I2C_BRCR    (0x028)
0039 #define I2C_IMSCR   (0x02C)
0040 #define I2C_RISR    (0x030)
0041 #define I2C_MISR    (0x034)
0042 #define I2C_ICR     (0x038)
0043 
0044 /* Control registers */
0045 #define I2C_CR_PE       (0x1 << 0)  /* Peripheral Enable */
0046 #define I2C_CR_OM       (0x3 << 1)  /* Operating mode */
0047 #define I2C_CR_SAM      (0x1 << 3)  /* Slave addressing mode */
0048 #define I2C_CR_SM       (0x3 << 4)  /* Speed mode */
0049 #define I2C_CR_SGCM     (0x1 << 6)  /* Slave general call mode */
0050 #define I2C_CR_FTX      (0x1 << 7)  /* Flush Transmit */
0051 #define I2C_CR_FRX      (0x1 << 8)  /* Flush Receive */
0052 #define I2C_CR_DMA_TX_EN    (0x1 << 9)  /* DMA Tx enable */
0053 #define I2C_CR_DMA_RX_EN    (0x1 << 10) /* DMA Rx Enable */
0054 #define I2C_CR_DMA_SLE      (0x1 << 11) /* DMA sync. logic enable */
0055 #define I2C_CR_LM       (0x1 << 12) /* Loopback mode */
0056 #define I2C_CR_FON      (0x3 << 13) /* Filtering on */
0057 #define I2C_CR_FS       (0x3 << 15) /* Force stop enable */
0058 
0059 /* Master controller (MCR) register */
0060 #define I2C_MCR_OP      (0x1 << 0)  /* Operation */
0061 #define I2C_MCR_A7      (0x7f << 1) /* 7-bit address */
0062 #define I2C_MCR_EA10        (0x7 << 8)  /* 10-bit Extended address */
0063 #define I2C_MCR_SB      (0x1 << 11) /* Extended address */
0064 #define I2C_MCR_AM      (0x3 << 12) /* Address type */
0065 #define I2C_MCR_STOP        (0x1 << 14) /* Stop condition */
0066 #define I2C_MCR_LENGTH      (0x7ff << 15)   /* Transaction length */
0067 
0068 /* Status register (SR) */
0069 #define I2C_SR_OP       (0x3 << 0)  /* Operation */
0070 #define I2C_SR_STATUS       (0x3 << 2)  /* controller status */
0071 #define I2C_SR_CAUSE        (0x7 << 4)  /* Abort cause */
0072 #define I2C_SR_TYPE     (0x3 << 7)  /* Receive type */
0073 #define I2C_SR_LENGTH       (0x7ff << 9)    /* Transfer length */
0074 
0075 /* Interrupt mask set/clear (IMSCR) bits */
0076 #define I2C_IT_TXFE     (0x1 << 0)
0077 #define I2C_IT_TXFNE        (0x1 << 1)
0078 #define I2C_IT_TXFF     (0x1 << 2)
0079 #define I2C_IT_TXFOVR       (0x1 << 3)
0080 #define I2C_IT_RXFE     (0x1 << 4)
0081 #define I2C_IT_RXFNF        (0x1 << 5)
0082 #define I2C_IT_RXFF     (0x1 << 6)
0083 #define I2C_IT_RFSR     (0x1 << 16)
0084 #define I2C_IT_RFSE     (0x1 << 17)
0085 #define I2C_IT_WTSR     (0x1 << 18)
0086 #define I2C_IT_MTD      (0x1 << 19)
0087 #define I2C_IT_STD      (0x1 << 20)
0088 #define I2C_IT_MAL      (0x1 << 24)
0089 #define I2C_IT_BERR     (0x1 << 25)
0090 #define I2C_IT_MTDWS        (0x1 << 28)
0091 
0092 #define GEN_MASK(val, mask, sb)  (((val) << (sb)) & (mask))
0093 
0094 /* some bits in ICR are reserved */
0095 #define I2C_CLEAR_ALL_INTS  0x131f007f
0096 
0097 /* first three msb bits are reserved */
0098 #define IRQ_MASK(mask)      (mask & 0x1fffffff)
0099 
0100 /* maximum threshold value */
0101 #define MAX_I2C_FIFO_THRESHOLD  15
0102 
0103 enum i2c_freq_mode {
0104     I2C_FREQ_MODE_STANDARD,     /* up to 100 Kb/s */
0105     I2C_FREQ_MODE_FAST,     /* up to 400 Kb/s */
0106     I2C_FREQ_MODE_HIGH_SPEED,   /* up to 3.4 Mb/s */
0107     I2C_FREQ_MODE_FAST_PLUS,    /* up to 1 Mb/s */
0108 };
0109 
0110 /**
0111  * struct i2c_vendor_data - per-vendor variations
0112  * @has_mtdws: variant has the MTDWS bit
0113  * @fifodepth: variant FIFO depth
0114  */
0115 struct i2c_vendor_data {
0116     bool has_mtdws;
0117     u32 fifodepth;
0118 };
0119 
0120 enum i2c_status {
0121     I2C_NOP,
0122     I2C_ON_GOING,
0123     I2C_OK,
0124     I2C_ABORT
0125 };
0126 
0127 /* operation */
0128 enum i2c_operation {
0129     I2C_NO_OPERATION = 0xff,
0130     I2C_WRITE = 0x00,
0131     I2C_READ = 0x01
0132 };
0133 
0134 /**
0135  * struct i2c_nmk_client - client specific data
0136  * @slave_adr: 7-bit slave address
0137  * @count: no. bytes to be transferred
0138  * @buffer: client data buffer
0139  * @xfer_bytes: bytes transferred till now
0140  * @operation: current I2C operation
0141  */
0142 struct i2c_nmk_client {
0143     unsigned short      slave_adr;
0144     unsigned long       count;
0145     unsigned char       *buffer;
0146     unsigned long       xfer_bytes;
0147     enum i2c_operation  operation;
0148 };
0149 
0150 /**
0151  * struct nmk_i2c_dev - private data structure of the controller.
0152  * @vendor: vendor data for this variant.
0153  * @adev: parent amba device.
0154  * @adap: corresponding I2C adapter.
0155  * @irq: interrupt line for the controller.
0156  * @virtbase: virtual io memory area.
0157  * @clk: hardware i2c block clock.
0158  * @cli: holder of client specific data.
0159  * @clk_freq: clock frequency for the operation mode
0160  * @tft: Tx FIFO Threshold in bytes
0161  * @rft: Rx FIFO Threshold in bytes
0162  * @timeout: Slave response timeout (ms)
0163  * @sm: speed mode
0164  * @stop: stop condition.
0165  * @xfer_complete: acknowledge completion for a I2C message.
0166  * @result: controller propogated result.
0167  */
0168 struct nmk_i2c_dev {
0169     struct i2c_vendor_data      *vendor;
0170     struct amba_device      *adev;
0171     struct i2c_adapter      adap;
0172     int             irq;
0173     void __iomem            *virtbase;
0174     struct clk          *clk;
0175     struct i2c_nmk_client       cli;
0176     u32             clk_freq;
0177     unsigned char           tft;
0178     unsigned char           rft;
0179     int             timeout;
0180     enum i2c_freq_mode      sm;
0181     int             stop;
0182     struct completion       xfer_complete;
0183     int             result;
0184 };
0185 
0186 /* controller's abort causes */
0187 static const char *abort_causes[] = {
0188     "no ack received after address transmission",
0189     "no ack received during data phase",
0190     "ack received after xmission of master code",
0191     "master lost arbitration",
0192     "slave restarts",
0193     "slave reset",
0194     "overflow, maxsize is 2047 bytes",
0195 };
0196 
0197 static inline void i2c_set_bit(void __iomem *reg, u32 mask)
0198 {
0199     writel(readl(reg) | mask, reg);
0200 }
0201 
0202 static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
0203 {
0204     writel(readl(reg) & ~mask, reg);
0205 }
0206 
0207 /**
0208  * flush_i2c_fifo() - This function flushes the I2C FIFO
0209  * @dev: private data of I2C Driver
0210  *
0211  * This function flushes the I2C Tx and Rx FIFOs. It returns
0212  * 0 on successful flushing of FIFO
0213  */
0214 static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
0215 {
0216 #define LOOP_ATTEMPTS 10
0217     int i;
0218     unsigned long timeout;
0219 
0220     /*
0221      * flush the transmit and receive FIFO. The flushing
0222      * operation takes several cycles before to be completed.
0223      * On the completion, the I2C internal logic clears these
0224      * bits, until then no one must access Tx, Rx FIFO and
0225      * should poll on these bits waiting for the completion.
0226      */
0227     writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
0228 
0229     for (i = 0; i < LOOP_ATTEMPTS; i++) {
0230         timeout = jiffies + dev->adap.timeout;
0231 
0232         while (!time_after(jiffies, timeout)) {
0233             if ((readl(dev->virtbase + I2C_CR) &
0234                 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
0235                     return 0;
0236         }
0237     }
0238 
0239     dev_err(&dev->adev->dev,
0240         "flushing operation timed out giving up after %d attempts",
0241         LOOP_ATTEMPTS);
0242 
0243     return -ETIMEDOUT;
0244 }
0245 
0246 /**
0247  * disable_all_interrupts() - Disable all interrupts of this I2c Bus
0248  * @dev: private data of I2C Driver
0249  */
0250 static void disable_all_interrupts(struct nmk_i2c_dev *dev)
0251 {
0252     u32 mask = IRQ_MASK(0);
0253     writel(mask, dev->virtbase + I2C_IMSCR);
0254 }
0255 
0256 /**
0257  * clear_all_interrupts() - Clear all interrupts of I2C Controller
0258  * @dev: private data of I2C Driver
0259  */
0260 static void clear_all_interrupts(struct nmk_i2c_dev *dev)
0261 {
0262     u32 mask;
0263     mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
0264     writel(mask, dev->virtbase + I2C_ICR);
0265 }
0266 
0267 /**
0268  * init_hw() - initialize the I2C hardware
0269  * @dev: private data of I2C Driver
0270  */
0271 static int init_hw(struct nmk_i2c_dev *dev)
0272 {
0273     int stat;
0274 
0275     stat = flush_i2c_fifo(dev);
0276     if (stat)
0277         goto exit;
0278 
0279     /* disable the controller */
0280     i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
0281 
0282     disable_all_interrupts(dev);
0283 
0284     clear_all_interrupts(dev);
0285 
0286     dev->cli.operation = I2C_NO_OPERATION;
0287 
0288 exit:
0289     return stat;
0290 }
0291 
0292 /* enable peripheral, master mode operation */
0293 #define DEFAULT_I2C_REG_CR  ((1 << 1) | I2C_CR_PE)
0294 
0295 /**
0296  * load_i2c_mcr_reg() - load the MCR register
0297  * @dev: private data of controller
0298  * @flags: message flags
0299  */
0300 static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
0301 {
0302     u32 mcr = 0;
0303     unsigned short slave_adr_3msb_bits;
0304 
0305     mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
0306 
0307     if (unlikely(flags & I2C_M_TEN)) {
0308         /* 10-bit address transaction */
0309         mcr |= GEN_MASK(2, I2C_MCR_AM, 12);
0310         /*
0311          * Get the top 3 bits.
0312          * EA10 represents extended address in MCR. This includes
0313          * the extension (MSB bits) of the 7 bit address loaded
0314          * in A7
0315          */
0316         slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
0317 
0318         mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
0319     } else {
0320         /* 7-bit address transaction */
0321         mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
0322     }
0323 
0324     /* start byte procedure not applied */
0325     mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
0326 
0327     /* check the operation, master read/write? */
0328     if (dev->cli.operation == I2C_WRITE)
0329         mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
0330     else
0331         mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
0332 
0333     /* stop or repeated start? */
0334     if (dev->stop)
0335         mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
0336     else
0337         mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
0338 
0339     mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
0340 
0341     return mcr;
0342 }
0343 
0344 /**
0345  * setup_i2c_controller() - setup the controller
0346  * @dev: private data of controller
0347  */
0348 static void setup_i2c_controller(struct nmk_i2c_dev *dev)
0349 {
0350     u32 brcr1, brcr2;
0351     u32 i2c_clk, div;
0352     u32 ns;
0353     u16 slsu;
0354 
0355     writel(0x0, dev->virtbase + I2C_CR);
0356     writel(0x0, dev->virtbase + I2C_HSMCR);
0357     writel(0x0, dev->virtbase + I2C_TFTR);
0358     writel(0x0, dev->virtbase + I2C_RFTR);
0359     writel(0x0, dev->virtbase + I2C_DMAR);
0360 
0361     i2c_clk = clk_get_rate(dev->clk);
0362 
0363     /*
0364      * set the slsu:
0365      *
0366      * slsu defines the data setup time after SCL clock
0367      * stretching in terms of i2c clk cycles + 1 (zero means
0368      * "wait one cycle"), the needed setup time for the three
0369      * modes are 250ns, 100ns, 10ns respectively.
0370      *
0371      * As the time for one cycle T in nanoseconds is
0372      * T = (1/f) * 1000000000 =>
0373      * slsu = cycles / (1000000000 / f) + 1
0374      */
0375     ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk);
0376     switch (dev->sm) {
0377     case I2C_FREQ_MODE_FAST:
0378     case I2C_FREQ_MODE_FAST_PLUS:
0379         slsu = DIV_ROUND_UP(100, ns); /* Fast */
0380         break;
0381     case I2C_FREQ_MODE_HIGH_SPEED:
0382         slsu = DIV_ROUND_UP(10, ns); /* High */
0383         break;
0384     case I2C_FREQ_MODE_STANDARD:
0385     default:
0386         slsu = DIV_ROUND_UP(250, ns); /* Standard */
0387         break;
0388     }
0389     slsu += 1;
0390 
0391     dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu);
0392     writel(slsu << 16, dev->virtbase + I2C_SCR);
0393 
0394     /*
0395      * The spec says, in case of std. mode the divider is
0396      * 2 whereas it is 3 for fast and fastplus mode of
0397      * operation. TODO - high speed support.
0398      */
0399     div = (dev->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2;
0400 
0401     /*
0402      * generate the mask for baud rate counters. The controller
0403      * has two baud rate counters. One is used for High speed
0404      * operation, and the other is for std, fast mode, fast mode
0405      * plus operation. Currently we do not supprt high speed mode
0406      * so set brcr1 to 0.
0407      */
0408     brcr1 = 0 << 16;
0409     brcr2 = (i2c_clk/(dev->clk_freq * div)) & 0xffff;
0410 
0411     /* set the baud rate counter register */
0412     writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
0413 
0414     /*
0415      * set the speed mode. Currently we support
0416      * only standard and fast mode of operation
0417      * TODO - support for fast mode plus (up to 1Mb/s)
0418      * and high speed (up to 3.4 Mb/s)
0419      */
0420     if (dev->sm > I2C_FREQ_MODE_FAST) {
0421         dev_err(&dev->adev->dev,
0422             "do not support this mode defaulting to std. mode\n");
0423         brcr2 = i2c_clk / (I2C_MAX_STANDARD_MODE_FREQ * 2) & 0xffff;
0424         writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
0425         writel(I2C_FREQ_MODE_STANDARD << 4,
0426                 dev->virtbase + I2C_CR);
0427     }
0428     writel(dev->sm << 4, dev->virtbase + I2C_CR);
0429 
0430     /* set the Tx and Rx FIFO threshold */
0431     writel(dev->tft, dev->virtbase + I2C_TFTR);
0432     writel(dev->rft, dev->virtbase + I2C_RFTR);
0433 }
0434 
0435 /**
0436  * read_i2c() - Read from I2C client device
0437  * @dev: private data of I2C Driver
0438  * @flags: message flags
0439  *
0440  * This function reads from i2c client device when controller is in
0441  * master mode. There is a completion timeout. If there is no transfer
0442  * before timeout error is returned.
0443  */
0444 static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
0445 {
0446     int status = 0;
0447     u32 mcr, irq_mask;
0448     unsigned long timeout;
0449 
0450     mcr = load_i2c_mcr_reg(dev, flags);
0451     writel(mcr, dev->virtbase + I2C_MCR);
0452 
0453     /* load the current CR value */
0454     writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
0455             dev->virtbase + I2C_CR);
0456 
0457     /* enable the controller */
0458     i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
0459 
0460     init_completion(&dev->xfer_complete);
0461 
0462     /* enable interrupts by setting the mask */
0463     irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
0464             I2C_IT_MAL | I2C_IT_BERR);
0465 
0466     if (dev->stop || !dev->vendor->has_mtdws)
0467         irq_mask |= I2C_IT_MTD;
0468     else
0469         irq_mask |= I2C_IT_MTDWS;
0470 
0471     irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
0472 
0473     writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
0474             dev->virtbase + I2C_IMSCR);
0475 
0476     timeout = wait_for_completion_timeout(
0477         &dev->xfer_complete, dev->adap.timeout);
0478 
0479     if (timeout == 0) {
0480         /* Controller timed out */
0481         dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
0482                 dev->cli.slave_adr);
0483         status = -ETIMEDOUT;
0484     }
0485     return status;
0486 }
0487 
0488 static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
0489 {
0490     int count;
0491 
0492     for (count = (no_bytes - 2);
0493             (count > 0) &&
0494             (dev->cli.count != 0);
0495             count--) {
0496         /* write to the Tx FIFO */
0497         writeb(*dev->cli.buffer,
0498             dev->virtbase + I2C_TFR);
0499         dev->cli.buffer++;
0500         dev->cli.count--;
0501         dev->cli.xfer_bytes++;
0502     }
0503 
0504 }
0505 
0506 /**
0507  * write_i2c() - Write data to I2C client.
0508  * @dev: private data of I2C Driver
0509  * @flags: message flags
0510  *
0511  * This function writes data to I2C client
0512  */
0513 static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
0514 {
0515     u32 status = 0;
0516     u32 mcr, irq_mask;
0517     unsigned long timeout;
0518 
0519     mcr = load_i2c_mcr_reg(dev, flags);
0520 
0521     writel(mcr, dev->virtbase + I2C_MCR);
0522 
0523     /* load the current CR value */
0524     writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
0525             dev->virtbase + I2C_CR);
0526 
0527     /* enable the controller */
0528     i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
0529 
0530     init_completion(&dev->xfer_complete);
0531 
0532     /* enable interrupts by settings the masks */
0533     irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
0534 
0535     /* Fill the TX FIFO with transmit data */
0536     fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
0537 
0538     if (dev->cli.count != 0)
0539         irq_mask |= I2C_IT_TXFNE;
0540 
0541     /*
0542      * check if we want to transfer a single or multiple bytes, if so
0543      * set the MTDWS bit (Master Transaction Done Without Stop)
0544      * to start repeated start operation
0545      */
0546     if (dev->stop || !dev->vendor->has_mtdws)
0547         irq_mask |= I2C_IT_MTD;
0548     else
0549         irq_mask |= I2C_IT_MTDWS;
0550 
0551     irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
0552 
0553     writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
0554             dev->virtbase + I2C_IMSCR);
0555 
0556     timeout = wait_for_completion_timeout(
0557         &dev->xfer_complete, dev->adap.timeout);
0558 
0559     if (timeout == 0) {
0560         /* Controller timed out */
0561         dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
0562                 dev->cli.slave_adr);
0563         status = -ETIMEDOUT;
0564     }
0565 
0566     return status;
0567 }
0568 
0569 /**
0570  * nmk_i2c_xfer_one() - transmit a single I2C message
0571  * @dev: device with a message encoded into it
0572  * @flags: message flags
0573  */
0574 static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
0575 {
0576     int status;
0577 
0578     if (flags & I2C_M_RD) {
0579         /* read operation */
0580         dev->cli.operation = I2C_READ;
0581         status = read_i2c(dev, flags);
0582     } else {
0583         /* write operation */
0584         dev->cli.operation = I2C_WRITE;
0585         status = write_i2c(dev, flags);
0586     }
0587 
0588     if (status || (dev->result)) {
0589         u32 i2c_sr;
0590         u32 cause;
0591 
0592         i2c_sr = readl(dev->virtbase + I2C_SR);
0593         /*
0594          * Check if the controller I2C operation status
0595          * is set to ABORT(11b).
0596          */
0597         if (((i2c_sr >> 2) & 0x3) == 0x3) {
0598             /* get the abort cause */
0599             cause = (i2c_sr >> 4) & 0x7;
0600             dev_err(&dev->adev->dev, "%s\n",
0601                 cause >= ARRAY_SIZE(abort_causes) ?
0602                 "unknown reason" :
0603                 abort_causes[cause]);
0604         }
0605 
0606         (void) init_hw(dev);
0607 
0608         status = status ? status : dev->result;
0609     }
0610 
0611     return status;
0612 }
0613 
0614 /**
0615  * nmk_i2c_xfer() - I2C transfer function used by kernel framework
0616  * @i2c_adap: Adapter pointer to the controller
0617  * @msgs: Pointer to data to be written.
0618  * @num_msgs: Number of messages to be executed
0619  *
0620  * This is the function called by the generic kernel i2c_transfer()
0621  * or i2c_smbus...() API calls. Note that this code is protected by the
0622  * semaphore set in the kernel i2c_transfer() function.
0623  *
0624  * NOTE:
0625  * READ TRANSFER : We impose a restriction of the first message to be the
0626  *      index message for any read transaction.
0627  *      - a no index is coded as '0',
0628  *      - 2byte big endian index is coded as '3'
0629  *      !!! msg[0].buf holds the actual index.
0630  *      This is compatible with generic messages of smbus emulator
0631  *      that send a one byte index.
0632  *      eg. a I2C transation to read 2 bytes from index 0
0633  *          idx = 0;
0634  *          msg[0].addr = client->addr;
0635  *          msg[0].flags = 0x0;
0636  *          msg[0].len = 1;
0637  *          msg[0].buf = &idx;
0638  *
0639  *          msg[1].addr = client->addr;
0640  *          msg[1].flags = I2C_M_RD;
0641  *          msg[1].len = 2;
0642  *          msg[1].buf = rd_buff
0643  *          i2c_transfer(adap, msg, 2);
0644  *
0645  * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
0646  *      If you want to emulate an SMBUS write transaction put the
0647  *      index as first byte(or first and second) in the payload.
0648  *      eg. a I2C transation to write 2 bytes from index 1
0649  *          wr_buff[0] = 0x1;
0650  *          wr_buff[1] = 0x23;
0651  *          wr_buff[2] = 0x46;
0652  *          msg[0].flags = 0x0;
0653  *          msg[0].len = 3;
0654  *          msg[0].buf = wr_buff;
0655  *          i2c_transfer(adap, msg, 1);
0656  *
0657  * To read or write a block of data (multiple bytes) using SMBUS emulation
0658  * please use the i2c_smbus_read_i2c_block_data()
0659  * or i2c_smbus_write_i2c_block_data() API
0660  */
0661 static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
0662         struct i2c_msg msgs[], int num_msgs)
0663 {
0664     int status = 0;
0665     int i;
0666     struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
0667     int j;
0668 
0669     pm_runtime_get_sync(&dev->adev->dev);
0670 
0671     /* Attempt three times to send the message queue */
0672     for (j = 0; j < 3; j++) {
0673         /* setup the i2c controller */
0674         setup_i2c_controller(dev);
0675 
0676         for (i = 0; i < num_msgs; i++) {
0677             dev->cli.slave_adr  = msgs[i].addr;
0678             dev->cli.buffer     = msgs[i].buf;
0679             dev->cli.count      = msgs[i].len;
0680             dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
0681             dev->result = 0;
0682 
0683             status = nmk_i2c_xfer_one(dev, msgs[i].flags);
0684             if (status != 0)
0685                 break;
0686         }
0687         if (status == 0)
0688             break;
0689     }
0690 
0691     pm_runtime_put_sync(&dev->adev->dev);
0692 
0693     /* return the no. messages processed */
0694     if (status)
0695         return status;
0696     else
0697         return num_msgs;
0698 }
0699 
0700 /**
0701  * disable_interrupts() - disable the interrupts
0702  * @dev: private data of controller
0703  * @irq: interrupt number
0704  */
0705 static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
0706 {
0707     irq = IRQ_MASK(irq);
0708     writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
0709             dev->virtbase + I2C_IMSCR);
0710     return 0;
0711 }
0712 
0713 /**
0714  * i2c_irq_handler() - interrupt routine
0715  * @irq: interrupt number
0716  * @arg: data passed to the handler
0717  *
0718  * This is the interrupt handler for the i2c driver. Currently
0719  * it handles the major interrupts like Rx & Tx FIFO management
0720  * interrupts, master transaction interrupts, arbitration and
0721  * bus error interrupts. The rest of the interrupts are treated as
0722  * unhandled.
0723  */
0724 static irqreturn_t i2c_irq_handler(int irq, void *arg)
0725 {
0726     struct nmk_i2c_dev *dev = arg;
0727     u32 tft, rft;
0728     u32 count;
0729     u32 misr, src;
0730 
0731     /* load Tx FIFO and Rx FIFO threshold values */
0732     tft = readl(dev->virtbase + I2C_TFTR);
0733     rft = readl(dev->virtbase + I2C_RFTR);
0734 
0735     /* read interrupt status register */
0736     misr = readl(dev->virtbase + I2C_MISR);
0737 
0738     src = __ffs(misr);
0739     switch ((1 << src)) {
0740 
0741     /* Transmit FIFO nearly empty interrupt */
0742     case I2C_IT_TXFNE:
0743     {
0744         if (dev->cli.operation == I2C_READ) {
0745             /*
0746              * in read operation why do we care for writing?
0747              * so disable the Transmit FIFO interrupt
0748              */
0749             disable_interrupts(dev, I2C_IT_TXFNE);
0750         } else {
0751             fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
0752             /*
0753              * if done, close the transfer by disabling the
0754              * corresponding TXFNE interrupt
0755              */
0756             if (dev->cli.count == 0)
0757                 disable_interrupts(dev, I2C_IT_TXFNE);
0758         }
0759     }
0760     break;
0761 
0762     /*
0763      * Rx FIFO nearly full interrupt.
0764      * This is set when the numer of entries in Rx FIFO is
0765      * greater or equal than the threshold value programmed
0766      * in RFT
0767      */
0768     case I2C_IT_RXFNF:
0769         for (count = rft; count > 0; count--) {
0770             /* Read the Rx FIFO */
0771             *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
0772             dev->cli.buffer++;
0773         }
0774         dev->cli.count -= rft;
0775         dev->cli.xfer_bytes += rft;
0776         break;
0777 
0778     /* Rx FIFO full */
0779     case I2C_IT_RXFF:
0780         for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
0781             *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
0782             dev->cli.buffer++;
0783         }
0784         dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
0785         dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
0786         break;
0787 
0788     /* Master Transaction Done with/without stop */
0789     case I2C_IT_MTD:
0790     case I2C_IT_MTDWS:
0791         if (dev->cli.operation == I2C_READ) {
0792             while (!(readl(dev->virtbase + I2C_RISR)
0793                  & I2C_IT_RXFE)) {
0794                 if (dev->cli.count == 0)
0795                     break;
0796                 *dev->cli.buffer =
0797                     readb(dev->virtbase + I2C_RFR);
0798                 dev->cli.buffer++;
0799                 dev->cli.count--;
0800                 dev->cli.xfer_bytes++;
0801             }
0802         }
0803 
0804         disable_all_interrupts(dev);
0805         clear_all_interrupts(dev);
0806 
0807         if (dev->cli.count) {
0808             dev->result = -EIO;
0809             dev_err(&dev->adev->dev,
0810                 "%lu bytes still remain to be xfered\n",
0811                 dev->cli.count);
0812             (void) init_hw(dev);
0813         }
0814         complete(&dev->xfer_complete);
0815 
0816         break;
0817 
0818     /* Master Arbitration lost interrupt */
0819     case I2C_IT_MAL:
0820         dev->result = -EIO;
0821         (void) init_hw(dev);
0822 
0823         i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
0824         complete(&dev->xfer_complete);
0825 
0826         break;
0827 
0828     /*
0829      * Bus Error interrupt.
0830      * This happens when an unexpected start/stop condition occurs
0831      * during the transaction.
0832      */
0833     case I2C_IT_BERR:
0834         dev->result = -EIO;
0835         /* get the status */
0836         if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
0837             (void) init_hw(dev);
0838 
0839         i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
0840         complete(&dev->xfer_complete);
0841 
0842         break;
0843 
0844     /*
0845      * Tx FIFO overrun interrupt.
0846      * This is set when a write operation in Tx FIFO is performed and
0847      * the Tx FIFO is full.
0848      */
0849     case I2C_IT_TXFOVR:
0850         dev->result = -EIO;
0851         (void) init_hw(dev);
0852 
0853         dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
0854         complete(&dev->xfer_complete);
0855 
0856         break;
0857 
0858     /* unhandled interrupts by this driver - TODO*/
0859     case I2C_IT_TXFE:
0860     case I2C_IT_TXFF:
0861     case I2C_IT_RXFE:
0862     case I2C_IT_RFSR:
0863     case I2C_IT_RFSE:
0864     case I2C_IT_WTSR:
0865     case I2C_IT_STD:
0866         dev_err(&dev->adev->dev, "unhandled Interrupt\n");
0867         break;
0868     default:
0869         dev_err(&dev->adev->dev, "spurious Interrupt..\n");
0870         break;
0871     }
0872 
0873     return IRQ_HANDLED;
0874 }
0875 
0876 #ifdef CONFIG_PM_SLEEP
0877 static int nmk_i2c_suspend_late(struct device *dev)
0878 {
0879     int ret;
0880 
0881     ret = pm_runtime_force_suspend(dev);
0882     if (ret)
0883         return ret;
0884 
0885     pinctrl_pm_select_sleep_state(dev);
0886     return 0;
0887 }
0888 
0889 static int nmk_i2c_resume_early(struct device *dev)
0890 {
0891     return pm_runtime_force_resume(dev);
0892 }
0893 #endif
0894 
0895 #ifdef CONFIG_PM
0896 static int nmk_i2c_runtime_suspend(struct device *dev)
0897 {
0898     struct amba_device *adev = to_amba_device(dev);
0899     struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
0900 
0901     clk_disable_unprepare(nmk_i2c->clk);
0902     pinctrl_pm_select_idle_state(dev);
0903     return 0;
0904 }
0905 
0906 static int nmk_i2c_runtime_resume(struct device *dev)
0907 {
0908     struct amba_device *adev = to_amba_device(dev);
0909     struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
0910     int ret;
0911 
0912     ret = clk_prepare_enable(nmk_i2c->clk);
0913     if (ret) {
0914         dev_err(dev, "can't prepare_enable clock\n");
0915         return ret;
0916     }
0917 
0918     pinctrl_pm_select_default_state(dev);
0919 
0920     ret = init_hw(nmk_i2c);
0921     if (ret) {
0922         clk_disable_unprepare(nmk_i2c->clk);
0923         pinctrl_pm_select_idle_state(dev);
0924     }
0925 
0926     return ret;
0927 }
0928 #endif
0929 
0930 static const struct dev_pm_ops nmk_i2c_pm = {
0931     SET_LATE_SYSTEM_SLEEP_PM_OPS(nmk_i2c_suspend_late, nmk_i2c_resume_early)
0932     SET_RUNTIME_PM_OPS(nmk_i2c_runtime_suspend,
0933             nmk_i2c_runtime_resume,
0934             NULL)
0935 };
0936 
0937 static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
0938 {
0939     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
0940 }
0941 
0942 static const struct i2c_algorithm nmk_i2c_algo = {
0943     .master_xfer    = nmk_i2c_xfer,
0944     .functionality  = nmk_i2c_functionality
0945 };
0946 
0947 static void nmk_i2c_of_probe(struct device_node *np,
0948                  struct nmk_i2c_dev *nmk)
0949 {
0950     /* Default to 100 kHz if no frequency is given in the node */
0951     if (of_property_read_u32(np, "clock-frequency", &nmk->clk_freq))
0952         nmk->clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
0953 
0954     /* This driver only supports 'standard' and 'fast' modes of operation. */
0955     if (nmk->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ)
0956         nmk->sm = I2C_FREQ_MODE_STANDARD;
0957     else
0958         nmk->sm = I2C_FREQ_MODE_FAST;
0959     nmk->tft = 1; /* Tx FIFO threshold */
0960     nmk->rft = 8; /* Rx FIFO threshold */
0961     nmk->timeout = 200; /* Slave response timeout(ms) */
0962 }
0963 
0964 static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
0965 {
0966     int ret = 0;
0967     struct device_node *np = adev->dev.of_node;
0968     struct nmk_i2c_dev  *dev;
0969     struct i2c_adapter *adap;
0970     struct i2c_vendor_data *vendor = id->data;
0971     u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
0972 
0973     dev = devm_kzalloc(&adev->dev, sizeof(struct nmk_i2c_dev), GFP_KERNEL);
0974     if (!dev) {
0975         dev_err(&adev->dev, "cannot allocate memory\n");
0976         ret = -ENOMEM;
0977         goto err_no_mem;
0978     }
0979     dev->vendor = vendor;
0980     dev->adev = adev;
0981     nmk_i2c_of_probe(np, dev);
0982 
0983     if (dev->tft > max_fifo_threshold) {
0984         dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
0985              dev->tft, max_fifo_threshold);
0986         dev->tft = max_fifo_threshold;
0987     }
0988 
0989     if (dev->rft > max_fifo_threshold) {
0990         dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
0991             dev->rft, max_fifo_threshold);
0992         dev->rft = max_fifo_threshold;
0993     }
0994 
0995     amba_set_drvdata(adev, dev);
0996 
0997     dev->virtbase = devm_ioremap(&adev->dev, adev->res.start,
0998                 resource_size(&adev->res));
0999     if (!dev->virtbase) {
1000         ret = -ENOMEM;
1001         goto err_no_mem;
1002     }
1003 
1004     dev->irq = adev->irq[0];
1005     ret = devm_request_irq(&adev->dev, dev->irq, i2c_irq_handler, 0,
1006                 DRIVER_NAME, dev);
1007     if (ret) {
1008         dev_err(&adev->dev, "cannot claim the irq %d\n", dev->irq);
1009         goto err_no_mem;
1010     }
1011 
1012     dev->clk = devm_clk_get(&adev->dev, NULL);
1013     if (IS_ERR(dev->clk)) {
1014         dev_err(&adev->dev, "could not get i2c clock\n");
1015         ret = PTR_ERR(dev->clk);
1016         goto err_no_mem;
1017     }
1018 
1019     ret = clk_prepare_enable(dev->clk);
1020     if (ret) {
1021         dev_err(&adev->dev, "can't prepare_enable clock\n");
1022         goto err_no_mem;
1023     }
1024 
1025     init_hw(dev);
1026 
1027     adap = &dev->adap;
1028     adap->dev.of_node = np;
1029     adap->dev.parent = &adev->dev;
1030     adap->owner = THIS_MODULE;
1031     adap->class = I2C_CLASS_DEPRECATED;
1032     adap->algo = &nmk_i2c_algo;
1033     adap->timeout = msecs_to_jiffies(dev->timeout);
1034     snprintf(adap->name, sizeof(adap->name),
1035          "Nomadik I2C at %pR", &adev->res);
1036 
1037     i2c_set_adapdata(adap, dev);
1038 
1039     dev_info(&adev->dev,
1040          "initialize %s on virtual base %p\n",
1041          adap->name, dev->virtbase);
1042 
1043     ret = i2c_add_adapter(adap);
1044     if (ret)
1045         goto err_no_adap;
1046 
1047     pm_runtime_put(&adev->dev);
1048 
1049     return 0;
1050 
1051  err_no_adap:
1052     clk_disable_unprepare(dev->clk);
1053  err_no_mem:
1054 
1055     return ret;
1056 }
1057 
1058 static void nmk_i2c_remove(struct amba_device *adev)
1059 {
1060     struct resource *res = &adev->res;
1061     struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
1062 
1063     i2c_del_adapter(&dev->adap);
1064     flush_i2c_fifo(dev);
1065     disable_all_interrupts(dev);
1066     clear_all_interrupts(dev);
1067     /* disable the controller */
1068     i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
1069     clk_disable_unprepare(dev->clk);
1070     release_mem_region(res->start, resource_size(res));
1071 }
1072 
1073 static struct i2c_vendor_data vendor_stn8815 = {
1074     .has_mtdws = false,
1075     .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */
1076 };
1077 
1078 static struct i2c_vendor_data vendor_db8500 = {
1079     .has_mtdws = true,
1080     .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */
1081 };
1082 
1083 static const struct amba_id nmk_i2c_ids[] = {
1084     {
1085         .id = 0x00180024,
1086         .mask   = 0x00ffffff,
1087         .data   = &vendor_stn8815,
1088     },
1089     {
1090         .id = 0x00380024,
1091         .mask   = 0x00ffffff,
1092         .data   = &vendor_db8500,
1093     },
1094     {},
1095 };
1096 
1097 MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1098 
1099 static struct amba_driver nmk_i2c_driver = {
1100     .drv = {
1101         .owner = THIS_MODULE,
1102         .name = DRIVER_NAME,
1103         .pm = &nmk_i2c_pm,
1104     },
1105     .id_table = nmk_i2c_ids,
1106     .probe = nmk_i2c_probe,
1107     .remove = nmk_i2c_remove,
1108 };
1109 
1110 static int __init nmk_i2c_init(void)
1111 {
1112     return amba_driver_register(&nmk_i2c_driver);
1113 }
1114 
1115 static void __exit nmk_i2c_exit(void)
1116 {
1117     amba_driver_unregister(&nmk_i2c_driver);
1118 }
1119 
1120 subsys_initcall(nmk_i2c_init);
1121 module_exit(nmk_i2c_exit);
1122 
1123 MODULE_AUTHOR("Sachin Verma");
1124 MODULE_AUTHOR("Srinidhi KASAGAR");
1125 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1126 MODULE_LICENSE("GPL");
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