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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Freescale MXS I2C bus driver
0004  *
0005  * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
0006  * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
0007  *
0008  * based on a (non-working) driver which was:
0009  *
0010  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
0011  */
0012 
0013 #include <linux/slab.h>
0014 #include <linux/device.h>
0015 #include <linux/module.h>
0016 #include <linux/i2c.h>
0017 #include <linux/err.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/completion.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/jiffies.h>
0022 #include <linux/io.h>
0023 #include <linux/stmp_device.h>
0024 #include <linux/of.h>
0025 #include <linux/of_device.h>
0026 #include <linux/dma-mapping.h>
0027 #include <linux/dmaengine.h>
0028 #include <linux/dma/mxs-dma.h>
0029 
0030 #define DRIVER_NAME "mxs-i2c"
0031 
0032 #define MXS_I2C_CTRL0       (0x00)
0033 #define MXS_I2C_CTRL0_SET   (0x04)
0034 #define MXS_I2C_CTRL0_CLR   (0x08)
0035 
0036 #define MXS_I2C_CTRL0_SFTRST            0x80000000
0037 #define MXS_I2C_CTRL0_RUN           0x20000000
0038 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST      0x02000000
0039 #define MXS_I2C_CTRL0_PIO_MODE          0x01000000
0040 #define MXS_I2C_CTRL0_RETAIN_CLOCK      0x00200000
0041 #define MXS_I2C_CTRL0_POST_SEND_STOP        0x00100000
0042 #define MXS_I2C_CTRL0_PRE_SEND_START        0x00080000
0043 #define MXS_I2C_CTRL0_MASTER_MODE       0x00020000
0044 #define MXS_I2C_CTRL0_DIRECTION         0x00010000
0045 #define MXS_I2C_CTRL0_XFER_COUNT(v)     ((v) & 0x0000FFFF)
0046 
0047 #define MXS_I2C_TIMING0     (0x10)
0048 #define MXS_I2C_TIMING1     (0x20)
0049 #define MXS_I2C_TIMING2     (0x30)
0050 
0051 #define MXS_I2C_CTRL1       (0x40)
0052 #define MXS_I2C_CTRL1_SET   (0x44)
0053 #define MXS_I2C_CTRL1_CLR   (0x48)
0054 
0055 #define MXS_I2C_CTRL1_CLR_GOT_A_NAK     0x10000000
0056 #define MXS_I2C_CTRL1_BUS_FREE_IRQ      0x80
0057 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
0058 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ      0x20
0059 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
0060 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ        0x08
0061 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ       0x04
0062 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ        0x02
0063 #define MXS_I2C_CTRL1_SLAVE_IRQ         0x01
0064 
0065 #define MXS_I2C_STAT        (0x50)
0066 #define MXS_I2C_STAT_GOT_A_NAK          0x10000000
0067 #define MXS_I2C_STAT_BUS_BUSY           0x00000800
0068 #define MXS_I2C_STAT_CLK_GEN_BUSY       0x00000400
0069 
0070 #define MXS_I2C_DATA(i2c)   ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0)
0071 
0072 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8)
0073 
0074 #define MXS_I2C_DEBUG0_DMAREQ   0x80000000
0075 
0076 #define MXS_I2C_IRQ_MASK    (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
0077                  MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
0078                  MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
0079                  MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
0080                  MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
0081                  MXS_I2C_CTRL1_SLAVE_IRQ)
0082 
0083 
0084 #define MXS_CMD_I2C_SELECT  (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
0085                  MXS_I2C_CTRL0_PRE_SEND_START | \
0086                  MXS_I2C_CTRL0_MASTER_MODE |    \
0087                  MXS_I2C_CTRL0_DIRECTION |  \
0088                  MXS_I2C_CTRL0_XFER_COUNT(1))
0089 
0090 #define MXS_CMD_I2C_WRITE   (MXS_I2C_CTRL0_PRE_SEND_START | \
0091                  MXS_I2C_CTRL0_MASTER_MODE |    \
0092                  MXS_I2C_CTRL0_DIRECTION)
0093 
0094 #define MXS_CMD_I2C_READ    (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
0095                  MXS_I2C_CTRL0_MASTER_MODE)
0096 
0097 enum mxs_i2c_devtype {
0098     MXS_I2C_UNKNOWN = 0,
0099     MXS_I2C_V1,
0100     MXS_I2C_V2,
0101 };
0102 
0103 /**
0104  * struct mxs_i2c_dev - per device, private MXS-I2C data
0105  *
0106  * @dev: driver model device node
0107  * @dev_type: distinguish i.MX23/i.MX28 features
0108  * @regs: IO registers pointer
0109  * @cmd_complete: completion object for transaction wait
0110  * @cmd_err: error code for last transaction
0111  * @adapter: i2c subsystem adapter node
0112  */
0113 struct mxs_i2c_dev {
0114     struct device *dev;
0115     enum mxs_i2c_devtype dev_type;
0116     void __iomem *regs;
0117     struct completion cmd_complete;
0118     int cmd_err;
0119     struct i2c_adapter adapter;
0120 
0121     uint32_t timing0;
0122     uint32_t timing1;
0123     uint32_t timing2;
0124 
0125     /* DMA support components */
0126     struct dma_chan         *dmach;
0127     uint32_t            pio_data[2];
0128     uint32_t            addr_data;
0129     struct scatterlist      sg_io[2];
0130     bool                dma_read;
0131 };
0132 
0133 static int mxs_i2c_reset(struct mxs_i2c_dev *i2c)
0134 {
0135     int ret = stmp_reset_block(i2c->regs);
0136     if (ret)
0137         return ret;
0138 
0139     /*
0140      * Configure timing for the I2C block. The I2C TIMING2 register has to
0141      * be programmed with this particular magic number. The rest is derived
0142      * from the XTAL speed and requested I2C speed.
0143      *
0144      * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
0145      */
0146     writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
0147     writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
0148     writel(i2c->timing2, i2c->regs + MXS_I2C_TIMING2);
0149 
0150     writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
0151 
0152     return 0;
0153 }
0154 
0155 static void mxs_i2c_dma_finish(struct mxs_i2c_dev *i2c)
0156 {
0157     if (i2c->dma_read) {
0158         dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
0159         dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
0160     } else {
0161         dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
0162     }
0163 }
0164 
0165 static void mxs_i2c_dma_irq_callback(void *param)
0166 {
0167     struct mxs_i2c_dev *i2c = param;
0168 
0169     complete(&i2c->cmd_complete);
0170     mxs_i2c_dma_finish(i2c);
0171 }
0172 
0173 static int mxs_i2c_dma_setup_xfer(struct i2c_adapter *adap,
0174             struct i2c_msg *msg, uint32_t flags)
0175 {
0176     struct dma_async_tx_descriptor *desc;
0177     struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
0178 
0179     i2c->addr_data = i2c_8bit_addr_from_msg(msg);
0180 
0181     if (msg->flags & I2C_M_RD) {
0182         i2c->dma_read = true;
0183 
0184         /*
0185          * SELECT command.
0186          */
0187 
0188         /* Queue the PIO register write transfer. */
0189         i2c->pio_data[0] = MXS_CMD_I2C_SELECT;
0190         desc = dmaengine_prep_slave_sg(i2c->dmach,
0191                     (struct scatterlist *)&i2c->pio_data[0],
0192                     1, DMA_TRANS_NONE, 0);
0193         if (!desc) {
0194             dev_err(i2c->dev,
0195                 "Failed to get PIO reg. write descriptor.\n");
0196             goto select_init_pio_fail;
0197         }
0198 
0199         /* Queue the DMA data transfer. */
0200         sg_init_one(&i2c->sg_io[0], &i2c->addr_data, 1);
0201         dma_map_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
0202         desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[0], 1,
0203                     DMA_MEM_TO_DEV,
0204                     DMA_PREP_INTERRUPT |
0205                     MXS_DMA_CTRL_WAIT4END);
0206         if (!desc) {
0207             dev_err(i2c->dev,
0208                 "Failed to get DMA data write descriptor.\n");
0209             goto select_init_dma_fail;
0210         }
0211 
0212         /*
0213          * READ command.
0214          */
0215 
0216         /* Queue the PIO register write transfer. */
0217         i2c->pio_data[1] = flags | MXS_CMD_I2C_READ |
0218                 MXS_I2C_CTRL0_XFER_COUNT(msg->len);
0219         desc = dmaengine_prep_slave_sg(i2c->dmach,
0220                     (struct scatterlist *)&i2c->pio_data[1],
0221                     1, DMA_TRANS_NONE, DMA_PREP_INTERRUPT);
0222         if (!desc) {
0223             dev_err(i2c->dev,
0224                 "Failed to get PIO reg. write descriptor.\n");
0225             goto select_init_dma_fail;
0226         }
0227 
0228         /* Queue the DMA data transfer. */
0229         sg_init_one(&i2c->sg_io[1], msg->buf, msg->len);
0230         dma_map_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
0231         desc = dmaengine_prep_slave_sg(i2c->dmach, &i2c->sg_io[1], 1,
0232                     DMA_DEV_TO_MEM,
0233                     DMA_PREP_INTERRUPT |
0234                     MXS_DMA_CTRL_WAIT4END);
0235         if (!desc) {
0236             dev_err(i2c->dev,
0237                 "Failed to get DMA data write descriptor.\n");
0238             goto read_init_dma_fail;
0239         }
0240     } else {
0241         i2c->dma_read = false;
0242 
0243         /*
0244          * WRITE command.
0245          */
0246 
0247         /* Queue the PIO register write transfer. */
0248         i2c->pio_data[0] = flags | MXS_CMD_I2C_WRITE |
0249                 MXS_I2C_CTRL0_XFER_COUNT(msg->len + 1);
0250         desc = dmaengine_prep_slave_sg(i2c->dmach,
0251                     (struct scatterlist *)&i2c->pio_data[0],
0252                     1, DMA_TRANS_NONE, 0);
0253         if (!desc) {
0254             dev_err(i2c->dev,
0255                 "Failed to get PIO reg. write descriptor.\n");
0256             goto write_init_pio_fail;
0257         }
0258 
0259         /* Queue the DMA data transfer. */
0260         sg_init_table(i2c->sg_io, 2);
0261         sg_set_buf(&i2c->sg_io[0], &i2c->addr_data, 1);
0262         sg_set_buf(&i2c->sg_io[1], msg->buf, msg->len);
0263         dma_map_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
0264         desc = dmaengine_prep_slave_sg(i2c->dmach, i2c->sg_io, 2,
0265                     DMA_MEM_TO_DEV,
0266                     DMA_PREP_INTERRUPT |
0267                     MXS_DMA_CTRL_WAIT4END);
0268         if (!desc) {
0269             dev_err(i2c->dev,
0270                 "Failed to get DMA data write descriptor.\n");
0271             goto write_init_dma_fail;
0272         }
0273     }
0274 
0275     /*
0276      * The last descriptor must have this callback,
0277      * to finish the DMA transaction.
0278      */
0279     desc->callback = mxs_i2c_dma_irq_callback;
0280     desc->callback_param = i2c;
0281 
0282     /* Start the transfer. */
0283     dmaengine_submit(desc);
0284     dma_async_issue_pending(i2c->dmach);
0285     return 0;
0286 
0287 /* Read failpath. */
0288 read_init_dma_fail:
0289     dma_unmap_sg(i2c->dev, &i2c->sg_io[1], 1, DMA_FROM_DEVICE);
0290 select_init_dma_fail:
0291     dma_unmap_sg(i2c->dev, &i2c->sg_io[0], 1, DMA_TO_DEVICE);
0292 select_init_pio_fail:
0293     dmaengine_terminate_sync(i2c->dmach);
0294     return -EINVAL;
0295 
0296 /* Write failpath. */
0297 write_init_dma_fail:
0298     dma_unmap_sg(i2c->dev, i2c->sg_io, 2, DMA_TO_DEVICE);
0299 write_init_pio_fail:
0300     dmaengine_terminate_sync(i2c->dmach);
0301     return -EINVAL;
0302 }
0303 
0304 static int mxs_i2c_pio_wait_xfer_end(struct mxs_i2c_dev *i2c)
0305 {
0306     unsigned long timeout = jiffies + msecs_to_jiffies(1000);
0307 
0308     while (readl(i2c->regs + MXS_I2C_CTRL0) & MXS_I2C_CTRL0_RUN) {
0309         if (readl(i2c->regs + MXS_I2C_CTRL1) &
0310                 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
0311             return -ENXIO;
0312         if (time_after(jiffies, timeout))
0313             return -ETIMEDOUT;
0314         cond_resched();
0315     }
0316 
0317     return 0;
0318 }
0319 
0320 static int mxs_i2c_pio_check_error_state(struct mxs_i2c_dev *i2c)
0321 {
0322     u32 state;
0323 
0324     state = readl(i2c->regs + MXS_I2C_CTRL1_CLR) & MXS_I2C_IRQ_MASK;
0325 
0326     if (state & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
0327         i2c->cmd_err = -ENXIO;
0328     else if (state & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
0329               MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
0330               MXS_I2C_CTRL1_SLAVE_STOP_IRQ |
0331               MXS_I2C_CTRL1_SLAVE_IRQ))
0332         i2c->cmd_err = -EIO;
0333 
0334     return i2c->cmd_err;
0335 }
0336 
0337 static void mxs_i2c_pio_trigger_cmd(struct mxs_i2c_dev *i2c, u32 cmd)
0338 {
0339     u32 reg;
0340 
0341     writel(cmd, i2c->regs + MXS_I2C_CTRL0);
0342 
0343     /* readback makes sure the write is latched into hardware */
0344     reg = readl(i2c->regs + MXS_I2C_CTRL0);
0345     reg |= MXS_I2C_CTRL0_RUN;
0346     writel(reg, i2c->regs + MXS_I2C_CTRL0);
0347 }
0348 
0349 /*
0350  * Start WRITE transaction on the I2C bus. By studying i.MX23 datasheet,
0351  * CTRL0::PIO_MODE bit description clarifies the order in which the registers
0352  * must be written during PIO mode operation. First, the CTRL0 register has
0353  * to be programmed with all the necessary bits but the RUN bit. Then the
0354  * payload has to be written into the DATA register. Finally, the transmission
0355  * is executed by setting the RUN bit in CTRL0.
0356  */
0357 static void mxs_i2c_pio_trigger_write_cmd(struct mxs_i2c_dev *i2c, u32 cmd,
0358                       u32 data)
0359 {
0360     writel(cmd, i2c->regs + MXS_I2C_CTRL0);
0361 
0362     if (i2c->dev_type == MXS_I2C_V1)
0363         writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_SET);
0364 
0365     writel(data, i2c->regs + MXS_I2C_DATA(i2c));
0366     writel(MXS_I2C_CTRL0_RUN, i2c->regs + MXS_I2C_CTRL0_SET);
0367 }
0368 
0369 static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
0370             struct i2c_msg *msg, uint32_t flags)
0371 {
0372     struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
0373     uint32_t addr_data = i2c_8bit_addr_from_msg(msg);
0374     uint32_t data = 0;
0375     int i, ret, xlen = 0, xmit = 0;
0376     uint32_t start;
0377 
0378     /* Mute IRQs coming from this block. */
0379     writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
0380 
0381     /*
0382      * MX23 idea:
0383      * - Enable CTRL0::PIO_MODE (1 << 24)
0384      * - Enable CTRL1::ACK_MODE (1 << 27)
0385      *
0386      * WARNING! The MX23 is broken in some way, even if it claims
0387      * to support PIO, when we try to transfer any amount of data
0388      * that is not aligned to 4 bytes, the DMA engine will have
0389      * bits in DEBUG1::DMA_BYTES_ENABLES still set even after the
0390      * transfer. This in turn will mess up the next transfer as
0391      * the block it emit one byte write onto the bus terminated
0392      * with a NAK+STOP. A possible workaround is to reset the IP
0393      * block after every PIO transmission, which might just work.
0394      *
0395      * NOTE: The CTRL0::PIO_MODE description is important, since
0396      * it outlines how the PIO mode is really supposed to work.
0397      */
0398     if (msg->flags & I2C_M_RD) {
0399         /*
0400          * PIO READ transfer:
0401          *
0402          * This transfer MUST be limited to 4 bytes maximum. It is not
0403          * possible to transfer more than four bytes via PIO, since we
0404          * can not in any way make sure we can read the data from the
0405          * DATA register fast enough. Besides, the RX FIFO is only four
0406          * bytes deep, thus we can only really read up to four bytes at
0407          * time. Finally, there is no bit indicating us that new data
0408          * arrived at the FIFO and can thus be fetched from the DATA
0409          * register.
0410          */
0411         BUG_ON(msg->len > 4);
0412 
0413         /* SELECT command. */
0414         mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
0415                           addr_data);
0416 
0417         ret = mxs_i2c_pio_wait_xfer_end(i2c);
0418         if (ret) {
0419             dev_dbg(i2c->dev,
0420                 "PIO: Failed to send SELECT command!\n");
0421             goto cleanup;
0422         }
0423 
0424         /* READ command. */
0425         mxs_i2c_pio_trigger_cmd(i2c,
0426                     MXS_CMD_I2C_READ | flags |
0427                     MXS_I2C_CTRL0_XFER_COUNT(msg->len));
0428 
0429         ret = mxs_i2c_pio_wait_xfer_end(i2c);
0430         if (ret) {
0431             dev_dbg(i2c->dev,
0432                 "PIO: Failed to send READ command!\n");
0433             goto cleanup;
0434         }
0435 
0436         data = readl(i2c->regs + MXS_I2C_DATA(i2c));
0437         for (i = 0; i < msg->len; i++) {
0438             msg->buf[i] = data & 0xff;
0439             data >>= 8;
0440         }
0441     } else {
0442         /*
0443          * PIO WRITE transfer:
0444          *
0445          * The code below implements clock stretching to circumvent
0446          * the possibility of kernel not being able to supply data
0447          * fast enough. It is possible to transfer arbitrary amount
0448          * of data using PIO write.
0449          */
0450 
0451         /*
0452          * The LSB of data buffer is the first byte blasted across
0453          * the bus. Higher order bytes follow. Thus the following
0454          * filling schematic.
0455          */
0456 
0457         data = addr_data << 24;
0458 
0459         /* Start the transfer with START condition. */
0460         start = MXS_I2C_CTRL0_PRE_SEND_START;
0461 
0462         /* If the transfer is long, use clock stretching. */
0463         if (msg->len > 3)
0464             start |= MXS_I2C_CTRL0_RETAIN_CLOCK;
0465 
0466         for (i = 0; i < msg->len; i++) {
0467             data >>= 8;
0468             data |= (msg->buf[i] << 24);
0469 
0470             xmit = 0;
0471 
0472             /* This is the last transfer of the message. */
0473             if (i + 1 == msg->len) {
0474                 /* Add optional STOP flag. */
0475                 start |= flags;
0476                 /* Remove RETAIN_CLOCK bit. */
0477                 start &= ~MXS_I2C_CTRL0_RETAIN_CLOCK;
0478                 xmit = 1;
0479             }
0480 
0481             /* Four bytes are ready in the "data" variable. */
0482             if ((i & 3) == 2)
0483                 xmit = 1;
0484 
0485             /* Nothing interesting happened, continue stuffing. */
0486             if (!xmit)
0487                 continue;
0488 
0489             /*
0490              * Compute the size of the transfer and shift the
0491              * data accordingly.
0492              *
0493              * i = (4k + 0) .... xlen = 2
0494              * i = (4k + 1) .... xlen = 3
0495              * i = (4k + 2) .... xlen = 4
0496              * i = (4k + 3) .... xlen = 1
0497              */
0498 
0499             if ((i % 4) == 3)
0500                 xlen = 1;
0501             else
0502                 xlen = (i % 4) + 2;
0503 
0504             data >>= (4 - xlen) * 8;
0505 
0506             dev_dbg(i2c->dev,
0507                 "PIO: len=%i pos=%i total=%i [W%s%s%s]\n",
0508                 xlen, i, msg->len,
0509                 start & MXS_I2C_CTRL0_PRE_SEND_START ? "S" : "",
0510                 start & MXS_I2C_CTRL0_POST_SEND_STOP ? "E" : "",
0511                 start & MXS_I2C_CTRL0_RETAIN_CLOCK ? "C" : "");
0512 
0513             writel(MXS_I2C_DEBUG0_DMAREQ,
0514                    i2c->regs + MXS_I2C_DEBUG0_CLR(i2c));
0515 
0516             mxs_i2c_pio_trigger_write_cmd(i2c,
0517                 start | MXS_I2C_CTRL0_MASTER_MODE |
0518                 MXS_I2C_CTRL0_DIRECTION |
0519                 MXS_I2C_CTRL0_XFER_COUNT(xlen), data);
0520 
0521             /* The START condition is sent only once. */
0522             start &= ~MXS_I2C_CTRL0_PRE_SEND_START;
0523 
0524             /* Wait for the end of the transfer. */
0525             ret = mxs_i2c_pio_wait_xfer_end(i2c);
0526             if (ret) {
0527                 dev_dbg(i2c->dev,
0528                     "PIO: Failed to finish WRITE cmd!\n");
0529                 break;
0530             }
0531 
0532             /* Check NAK here. */
0533             ret = readl(i2c->regs + MXS_I2C_STAT) &
0534                     MXS_I2C_STAT_GOT_A_NAK;
0535             if (ret) {
0536                 ret = -ENXIO;
0537                 goto cleanup;
0538             }
0539         }
0540     }
0541 
0542     /* make sure we capture any occurred error into cmd_err */
0543     ret = mxs_i2c_pio_check_error_state(i2c);
0544 
0545 cleanup:
0546     /* Clear any dangling IRQs and re-enable interrupts. */
0547     writel(MXS_I2C_IRQ_MASK, i2c->regs + MXS_I2C_CTRL1_CLR);
0548     writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
0549 
0550     /* Clear the PIO_MODE on i.MX23 */
0551     if (i2c->dev_type == MXS_I2C_V1)
0552         writel(MXS_I2C_CTRL0_PIO_MODE, i2c->regs + MXS_I2C_CTRL0_CLR);
0553 
0554     return ret;
0555 }
0556 
0557 /*
0558  * Low level master read/write transaction.
0559  */
0560 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
0561                 int stop)
0562 {
0563     struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
0564     int ret;
0565     int flags;
0566     int use_pio = 0;
0567     unsigned long time_left;
0568 
0569     flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
0570 
0571     dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
0572         msg->addr, msg->len, msg->flags, stop);
0573 
0574     /*
0575      * The MX28 I2C IP block can only do PIO READ for transfer of to up
0576      * 4 bytes of length. The write transfer is not limited as it can use
0577      * clock stretching to avoid FIFO underruns.
0578      */
0579     if ((msg->flags & I2C_M_RD) && (msg->len <= 4))
0580         use_pio = 1;
0581     if (!(msg->flags & I2C_M_RD) && (msg->len < 7))
0582         use_pio = 1;
0583 
0584     i2c->cmd_err = 0;
0585     if (use_pio) {
0586         ret = mxs_i2c_pio_setup_xfer(adap, msg, flags);
0587         /* No need to reset the block if NAK was received. */
0588         if (ret && (ret != -ENXIO))
0589             mxs_i2c_reset(i2c);
0590     } else {
0591         reinit_completion(&i2c->cmd_complete);
0592         ret = mxs_i2c_dma_setup_xfer(adap, msg, flags);
0593         if (ret)
0594             return ret;
0595 
0596         time_left = wait_for_completion_timeout(&i2c->cmd_complete,
0597                         msecs_to_jiffies(1000));
0598         if (!time_left)
0599             goto timeout;
0600 
0601         ret = i2c->cmd_err;
0602     }
0603 
0604     if (ret == -ENXIO) {
0605         /*
0606          * If the transfer fails with a NAK from the slave the
0607          * controller halts until it gets told to return to idle state.
0608          */
0609         writel(MXS_I2C_CTRL1_CLR_GOT_A_NAK,
0610                i2c->regs + MXS_I2C_CTRL1_SET);
0611     }
0612 
0613     /*
0614      * WARNING!
0615      * The i.MX23 is strange. After each and every operation, it's I2C IP
0616      * block must be reset, otherwise the IP block will misbehave. This can
0617      * be observed on the bus by the block sending out one single byte onto
0618      * the bus. In case such an error happens, bit 27 will be set in the
0619      * DEBUG0 register. This bit is not documented in the i.MX23 datasheet
0620      * and is marked as "TBD" instead. To reset this bit to a correct state,
0621      * reset the whole block. Since the block reset does not take long, do
0622      * reset the block after every transfer to play safe.
0623      */
0624     if (i2c->dev_type == MXS_I2C_V1)
0625         mxs_i2c_reset(i2c);
0626 
0627     dev_dbg(i2c->dev, "Done with err=%d\n", ret);
0628 
0629     return ret;
0630 
0631 timeout:
0632     dev_dbg(i2c->dev, "Timeout!\n");
0633     mxs_i2c_dma_finish(i2c);
0634     ret = mxs_i2c_reset(i2c);
0635     if (ret)
0636         return ret;
0637 
0638     return -ETIMEDOUT;
0639 }
0640 
0641 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
0642             int num)
0643 {
0644     int i;
0645     int err;
0646 
0647     for (i = 0; i < num; i++) {
0648         err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
0649         if (err)
0650             return err;
0651     }
0652 
0653     return num;
0654 }
0655 
0656 static u32 mxs_i2c_func(struct i2c_adapter *adap)
0657 {
0658     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0659 }
0660 
0661 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
0662 {
0663     struct mxs_i2c_dev *i2c = dev_id;
0664     u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
0665 
0666     if (!stat)
0667         return IRQ_NONE;
0668 
0669     if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
0670         i2c->cmd_err = -ENXIO;
0671     else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
0672             MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
0673             MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
0674         /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
0675         i2c->cmd_err = -EIO;
0676 
0677     writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
0678 
0679     return IRQ_HANDLED;
0680 }
0681 
0682 static const struct i2c_algorithm mxs_i2c_algo = {
0683     .master_xfer = mxs_i2c_xfer,
0684     .functionality = mxs_i2c_func,
0685 };
0686 
0687 static const struct i2c_adapter_quirks mxs_i2c_quirks = {
0688     .flags = I2C_AQ_NO_ZERO_LEN,
0689 };
0690 
0691 static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, uint32_t speed)
0692 {
0693     /* The I2C block clock runs at 24MHz */
0694     const uint32_t clk = 24000000;
0695     uint32_t divider;
0696     uint16_t high_count, low_count, rcv_count, xmit_count;
0697     uint32_t bus_free, leadin;
0698     struct device *dev = i2c->dev;
0699 
0700     divider = DIV_ROUND_UP(clk, speed);
0701 
0702     if (divider < 25) {
0703         /*
0704          * limit the divider, so that min(low_count, high_count)
0705          * is >= 1
0706          */
0707         divider = 25;
0708         dev_warn(dev,
0709             "Speed too high (%u.%03u kHz), using %u.%03u kHz\n",
0710             speed / 1000, speed % 1000,
0711             clk / divider / 1000, clk / divider % 1000);
0712     } else if (divider > 1897) {
0713         /*
0714          * limit the divider, so that max(low_count, high_count)
0715          * cannot exceed 1023
0716          */
0717         divider = 1897;
0718         dev_warn(dev,
0719             "Speed too low (%u.%03u kHz), using %u.%03u kHz\n",
0720             speed / 1000, speed % 1000,
0721             clk / divider / 1000, clk / divider % 1000);
0722     }
0723 
0724     /*
0725      * The I2C spec specifies the following timing data:
0726      *                          standard mode  fast mode Bitfield name
0727      * tLOW (SCL LOW period)     4700 ns        1300 ns
0728      * tHIGH (SCL HIGH period)   4000 ns         600 ns
0729      * tSU;DAT (data setup time)  250 ns         100 ns
0730      * tHD;STA (START hold time) 4000 ns         600 ns
0731      * tBUF (bus free time)      4700 ns        1300 ns
0732      *
0733      * The hardware (of the i.MX28 at least) seems to add 2 additional
0734      * clock cycles to the low_count and 7 cycles to the high_count.
0735      * This is compensated for by subtracting the respective constants
0736      * from the values written to the timing registers.
0737      */
0738     if (speed > I2C_MAX_STANDARD_MODE_FREQ) {
0739         /* fast mode */
0740         low_count = DIV_ROUND_CLOSEST(divider * 13, (13 + 6));
0741         high_count = DIV_ROUND_CLOSEST(divider * 6, (13 + 6));
0742         leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000);
0743         bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000);
0744     } else {
0745         /* normal mode */
0746         low_count = DIV_ROUND_CLOSEST(divider * 47, (47 + 40));
0747         high_count = DIV_ROUND_CLOSEST(divider * 40, (47 + 40));
0748         leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
0749         bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000);
0750     }
0751     rcv_count = high_count * 3 / 8;
0752     xmit_count = low_count * 3 / 8;
0753 
0754     dev_dbg(dev,
0755         "speed=%u(actual %u) divider=%u low=%u high=%u xmit=%u rcv=%u leadin=%u bus_free=%u\n",
0756         speed, clk / divider, divider, low_count, high_count,
0757         xmit_count, rcv_count, leadin, bus_free);
0758 
0759     low_count -= 2;
0760     high_count -= 7;
0761     i2c->timing0 = (high_count << 16) | rcv_count;
0762     i2c->timing1 = (low_count << 16) | xmit_count;
0763     i2c->timing2 = (bus_free << 16 | leadin);
0764 }
0765 
0766 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
0767 {
0768     uint32_t speed;
0769     struct device *dev = i2c->dev;
0770     struct device_node *node = dev->of_node;
0771     int ret;
0772 
0773     ret = of_property_read_u32(node, "clock-frequency", &speed);
0774     if (ret) {
0775         dev_warn(dev, "No I2C speed selected, using 100kHz\n");
0776         speed = I2C_MAX_STANDARD_MODE_FREQ;
0777     }
0778 
0779     mxs_i2c_derive_timing(i2c, speed);
0780 
0781     return 0;
0782 }
0783 
0784 static const struct of_device_id mxs_i2c_dt_ids[] = {
0785     { .compatible = "fsl,imx23-i2c", .data = (void *)MXS_I2C_V1, },
0786     { .compatible = "fsl,imx28-i2c", .data = (void *)MXS_I2C_V2, },
0787     { /* sentinel */ }
0788 };
0789 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
0790 
0791 static int mxs_i2c_probe(struct platform_device *pdev)
0792 {
0793     struct device *dev = &pdev->dev;
0794     struct mxs_i2c_dev *i2c;
0795     struct i2c_adapter *adap;
0796     int err, irq;
0797 
0798     i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
0799     if (!i2c)
0800         return -ENOMEM;
0801 
0802     i2c->dev_type = (uintptr_t)of_device_get_match_data(&pdev->dev);
0803 
0804     i2c->regs = devm_platform_ioremap_resource(pdev, 0);
0805     if (IS_ERR(i2c->regs))
0806         return PTR_ERR(i2c->regs);
0807 
0808     irq = platform_get_irq(pdev, 0);
0809     if (irq < 0)
0810         return irq;
0811 
0812     err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
0813     if (err)
0814         return err;
0815 
0816     i2c->dev = dev;
0817 
0818     init_completion(&i2c->cmd_complete);
0819 
0820     if (dev->of_node) {
0821         err = mxs_i2c_get_ofdata(i2c);
0822         if (err)
0823             return err;
0824     }
0825 
0826     /* Setup the DMA */
0827     i2c->dmach = dma_request_chan(dev, "rx-tx");
0828     if (IS_ERR(i2c->dmach)) {
0829         dev_err(dev, "Failed to request dma\n");
0830         return PTR_ERR(i2c->dmach);
0831     }
0832 
0833     platform_set_drvdata(pdev, i2c);
0834 
0835     /* Do reset to enforce correct startup after pinmuxing */
0836     err = mxs_i2c_reset(i2c);
0837     if (err)
0838         return err;
0839 
0840     adap = &i2c->adapter;
0841     strscpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
0842     adap->owner = THIS_MODULE;
0843     adap->algo = &mxs_i2c_algo;
0844     adap->quirks = &mxs_i2c_quirks;
0845     adap->dev.parent = dev;
0846     adap->nr = pdev->id;
0847     adap->dev.of_node = pdev->dev.of_node;
0848     i2c_set_adapdata(adap, i2c);
0849     err = i2c_add_numbered_adapter(adap);
0850     if (err) {
0851         writel(MXS_I2C_CTRL0_SFTRST,
0852                 i2c->regs + MXS_I2C_CTRL0_SET);
0853         return err;
0854     }
0855 
0856     return 0;
0857 }
0858 
0859 static int mxs_i2c_remove(struct platform_device *pdev)
0860 {
0861     struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
0862 
0863     i2c_del_adapter(&i2c->adapter);
0864 
0865     if (i2c->dmach)
0866         dma_release_channel(i2c->dmach);
0867 
0868     writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
0869 
0870     return 0;
0871 }
0872 
0873 static struct platform_driver mxs_i2c_driver = {
0874     .driver = {
0875            .name = DRIVER_NAME,
0876            .of_match_table = mxs_i2c_dt_ids,
0877            },
0878     .probe = mxs_i2c_probe,
0879     .remove = mxs_i2c_remove,
0880 };
0881 
0882 static int __init mxs_i2c_init(void)
0883 {
0884     return platform_driver_register(&mxs_i2c_driver);
0885 }
0886 subsys_initcall(mxs_i2c_init);
0887 
0888 static void __exit mxs_i2c_exit(void)
0889 {
0890     platform_driver_unregister(&mxs_i2c_driver);
0891 }
0892 module_exit(mxs_i2c_exit);
0893 
0894 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
0895 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
0896 MODULE_DESCRIPTION("MXS I2C Bus Driver");
0897 MODULE_LICENSE("GPL");
0898 MODULE_ALIAS("platform:" DRIVER_NAME);
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