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0001 /*
0002  * Driver for the i2c controller on the Marvell line of host bridges
0003  * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
0004  *
0005  * Author: Mark A. Greer <mgreer@mvista.com>
0006  *
0007  * 2005 (c) MontaVista, Software, Inc.  This file is licensed under
0008  * the terms of the GNU General Public License version 2.  This program
0009  * is licensed "as is" without any warranty of any kind, whether express
0010  * or implied.
0011  */
0012 #include <linux/kernel.h>
0013 #include <linux/slab.h>
0014 #include <linux/module.h>
0015 #include <linux/spinlock.h>
0016 #include <linux/i2c.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/mv643xx_i2c.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/pinctrl/consumer.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/reset.h>
0023 #include <linux/io.h>
0024 #include <linux/of.h>
0025 #include <linux/of_device.h>
0026 #include <linux/of_irq.h>
0027 #include <linux/clk.h>
0028 #include <linux/err.h>
0029 #include <linux/delay.h>
0030 
0031 #define MV64XXX_I2C_ADDR_ADDR(val)          ((val & 0x7f) << 1)
0032 #define MV64XXX_I2C_BAUD_DIV_N(val)         (val & 0x7)
0033 #define MV64XXX_I2C_BAUD_DIV_M(val)         ((val & 0xf) << 3)
0034 
0035 #define MV64XXX_I2C_REG_CONTROL_ACK         BIT(2)
0036 #define MV64XXX_I2C_REG_CONTROL_IFLG            BIT(3)
0037 #define MV64XXX_I2C_REG_CONTROL_STOP            BIT(4)
0038 #define MV64XXX_I2C_REG_CONTROL_START           BIT(5)
0039 #define MV64XXX_I2C_REG_CONTROL_TWSIEN          BIT(6)
0040 #define MV64XXX_I2C_REG_CONTROL_INTEN           BIT(7)
0041 
0042 /* Ctlr status values */
0043 #define MV64XXX_I2C_STATUS_BUS_ERR          0x00
0044 #define MV64XXX_I2C_STATUS_MAST_START           0x08
0045 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START        0x10
0046 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK     0x18
0047 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK      0x20
0048 #define MV64XXX_I2C_STATUS_MAST_WR_ACK          0x28
0049 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK       0x30
0050 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB        0x38
0051 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK     0x40
0052 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK      0x48
0053 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK     0x50
0054 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK      0x58
0055 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK       0xd0
0056 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK    0xd8
0057 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK       0xe0
0058 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK    0xe8
0059 #define MV64XXX_I2C_STATUS_NO_STATUS            0xf8
0060 
0061 /* Register defines (I2C bridge) */
0062 #define MV64XXX_I2C_REG_TX_DATA_LO          0xc0
0063 #define MV64XXX_I2C_REG_TX_DATA_HI          0xc4
0064 #define MV64XXX_I2C_REG_RX_DATA_LO          0xc8
0065 #define MV64XXX_I2C_REG_RX_DATA_HI          0xcc
0066 #define MV64XXX_I2C_REG_BRIDGE_CONTROL          0xd0
0067 #define MV64XXX_I2C_REG_BRIDGE_STATUS           0xd4
0068 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE       0xd8
0069 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK        0xdC
0070 #define MV64XXX_I2C_REG_BRIDGE_TIMING           0xe0
0071 
0072 /* Bridge Control values */
0073 #define MV64XXX_I2C_BRIDGE_CONTROL_WR           BIT(0)
0074 #define MV64XXX_I2C_BRIDGE_CONTROL_RD           BIT(1)
0075 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT       2
0076 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT     BIT(12)
0077 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT    13
0078 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT    16
0079 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE       BIT(19)
0080 #define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START   BIT(20)
0081 
0082 /* Bridge Status values */
0083 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR         BIT(0)
0084 
0085 /* Driver states */
0086 enum {
0087     MV64XXX_I2C_STATE_INVALID,
0088     MV64XXX_I2C_STATE_IDLE,
0089     MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
0090     MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
0091     MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
0092     MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
0093     MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
0094     MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
0095 };
0096 
0097 /* Driver actions */
0098 enum {
0099     MV64XXX_I2C_ACTION_INVALID,
0100     MV64XXX_I2C_ACTION_CONTINUE,
0101     MV64XXX_I2C_ACTION_SEND_RESTART,
0102     MV64XXX_I2C_ACTION_SEND_ADDR_1,
0103     MV64XXX_I2C_ACTION_SEND_ADDR_2,
0104     MV64XXX_I2C_ACTION_SEND_DATA,
0105     MV64XXX_I2C_ACTION_RCV_DATA,
0106     MV64XXX_I2C_ACTION_RCV_DATA_STOP,
0107     MV64XXX_I2C_ACTION_SEND_STOP,
0108 };
0109 
0110 struct mv64xxx_i2c_regs {
0111     u8  addr;
0112     u8  ext_addr;
0113     u8  data;
0114     u8  control;
0115     u8  status;
0116     u8  clock;
0117     u8  soft_reset;
0118 };
0119 
0120 struct mv64xxx_i2c_data {
0121     struct i2c_msg      *msgs;
0122     int         num_msgs;
0123     int         irq;
0124     u32         state;
0125     u32         action;
0126     u32         aborting;
0127     u32         cntl_bits;
0128     void __iomem        *reg_base;
0129     struct mv64xxx_i2c_regs reg_offsets;
0130     u32         addr1;
0131     u32         addr2;
0132     u32         bytes_left;
0133     u32         byte_posn;
0134     u32         send_stop;
0135     u32         block;
0136     int         rc;
0137     u32         freq_m;
0138     u32         freq_n;
0139     struct clk              *clk;
0140     struct clk              *reg_clk;
0141     wait_queue_head_t   waitq;
0142     spinlock_t      lock;
0143     struct i2c_msg      *msg;
0144     struct i2c_adapter  adapter;
0145     bool            offload_enabled;
0146 /* 5us delay in order to avoid repeated start timing violation */
0147     bool            errata_delay;
0148     struct reset_control    *rstc;
0149     bool            irq_clear_inverted;
0150     /* Clk div is 2 to the power n, not 2 to the power n + 1 */
0151     bool            clk_n_base_0;
0152     struct i2c_bus_recovery_info    rinfo;
0153     bool            atomic;
0154 };
0155 
0156 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
0157     .addr       = 0x00,
0158     .ext_addr   = 0x10,
0159     .data       = 0x04,
0160     .control    = 0x08,
0161     .status     = 0x0c,
0162     .clock      = 0x0c,
0163     .soft_reset = 0x1c,
0164 };
0165 
0166 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
0167     .addr       = 0x00,
0168     .ext_addr   = 0x04,
0169     .data       = 0x08,
0170     .control    = 0x0c,
0171     .status     = 0x10,
0172     .clock      = 0x14,
0173     .soft_reset = 0x18,
0174 };
0175 
0176 static void
0177 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
0178     struct i2c_msg *msg)
0179 {
0180     u32 dir = 0;
0181 
0182     drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
0183                   MV64XXX_I2C_REG_CONTROL_TWSIEN;
0184 
0185     if (!drv_data->atomic)
0186         drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_INTEN;
0187 
0188     if (msg->flags & I2C_M_RD)
0189         dir = 1;
0190 
0191     if (msg->flags & I2C_M_TEN) {
0192         drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
0193         drv_data->addr2 = (u32)msg->addr & 0xff;
0194     } else {
0195         drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
0196         drv_data->addr2 = 0;
0197     }
0198 }
0199 
0200 /*
0201  *****************************************************************************
0202  *
0203  *  Finite State Machine & Interrupt Routines
0204  *
0205  *****************************************************************************
0206  */
0207 
0208 /* Reset hardware and initialize FSM */
0209 static void
0210 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
0211 {
0212     if (drv_data->offload_enabled) {
0213         writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
0214         writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
0215         writel(0, drv_data->reg_base +
0216             MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
0217         writel(0, drv_data->reg_base +
0218             MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
0219     }
0220 
0221     writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
0222     writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
0223         drv_data->reg_base + drv_data->reg_offsets.clock);
0224     writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
0225     writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
0226     writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
0227         drv_data->reg_base + drv_data->reg_offsets.control);
0228 
0229     if (drv_data->errata_delay)
0230         udelay(5);
0231 
0232     drv_data->state = MV64XXX_I2C_STATE_IDLE;
0233 }
0234 
0235 static void
0236 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
0237 {
0238     /*
0239      * If state is idle, then this is likely the remnants of an old
0240      * operation that driver has given up on or the user has killed.
0241      * If so, issue the stop condition and go to idle.
0242      */
0243     if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
0244         drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
0245         return;
0246     }
0247 
0248     /* The status from the ctlr [mostly] tells us what to do next */
0249     switch (status) {
0250     /* Start condition interrupt */
0251     case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
0252     case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
0253         drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
0254         drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
0255         break;
0256 
0257     /* Performing a write */
0258     case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
0259         if (drv_data->msg->flags & I2C_M_TEN) {
0260             drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
0261             drv_data->state =
0262                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
0263             break;
0264         }
0265         fallthrough;
0266     case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
0267     case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
0268         if ((drv_data->bytes_left == 0)
0269                 || (drv_data->aborting
0270                     && (drv_data->byte_posn != 0))) {
0271             if (drv_data->send_stop || drv_data->aborting) {
0272                 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
0273                 drv_data->state = MV64XXX_I2C_STATE_IDLE;
0274             } else {
0275                 drv_data->action =
0276                     MV64XXX_I2C_ACTION_SEND_RESTART;
0277                 drv_data->state =
0278                     MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
0279             }
0280         } else {
0281             drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
0282             drv_data->state =
0283                 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
0284             drv_data->bytes_left--;
0285         }
0286         break;
0287 
0288     /* Performing a read */
0289     case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
0290         if (drv_data->msg->flags & I2C_M_TEN) {
0291             drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
0292             drv_data->state =
0293                 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
0294             break;
0295         }
0296         fallthrough;
0297     case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
0298         if (drv_data->bytes_left == 0) {
0299             drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
0300             drv_data->state = MV64XXX_I2C_STATE_IDLE;
0301             break;
0302         }
0303         fallthrough;
0304     case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
0305         if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
0306             drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
0307         else {
0308             drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
0309             drv_data->bytes_left--;
0310         }
0311         drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
0312 
0313         if ((drv_data->bytes_left == 1) || drv_data->aborting)
0314             drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
0315         break;
0316 
0317     case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
0318         drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
0319         drv_data->state = MV64XXX_I2C_STATE_IDLE;
0320         break;
0321 
0322     case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
0323     case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
0324     case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
0325         /* Doesn't seem to be a device at other end */
0326         drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
0327         drv_data->state = MV64XXX_I2C_STATE_IDLE;
0328         drv_data->rc = -ENXIO;
0329         break;
0330 
0331     default:
0332         dev_err(&drv_data->adapter.dev,
0333             "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
0334             "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
0335              drv_data->state, status, drv_data->msg->addr,
0336              drv_data->msg->flags);
0337         drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
0338         mv64xxx_i2c_hw_init(drv_data);
0339         i2c_recover_bus(&drv_data->adapter);
0340         drv_data->rc = -EAGAIN;
0341     }
0342 }
0343 
0344 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
0345 {
0346     drv_data->msg = drv_data->msgs;
0347     drv_data->byte_posn = 0;
0348     drv_data->bytes_left = drv_data->msg->len;
0349     drv_data->aborting = 0;
0350     drv_data->rc = 0;
0351 
0352     mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
0353     writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
0354            drv_data->reg_base + drv_data->reg_offsets.control);
0355 }
0356 
0357 static void
0358 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
0359 {
0360     switch(drv_data->action) {
0361     case MV64XXX_I2C_ACTION_SEND_RESTART:
0362         /* We should only get here if we have further messages */
0363         BUG_ON(drv_data->num_msgs == 0);
0364 
0365         drv_data->msgs++;
0366         drv_data->num_msgs--;
0367         mv64xxx_i2c_send_start(drv_data);
0368 
0369         if (drv_data->errata_delay)
0370             udelay(5);
0371 
0372         /*
0373          * We're never at the start of the message here, and by this
0374          * time it's already too late to do any protocol mangling.
0375          * Thankfully, do not advertise support for that feature.
0376          */
0377         drv_data->send_stop = drv_data->num_msgs == 1;
0378         break;
0379 
0380     case MV64XXX_I2C_ACTION_CONTINUE:
0381         writel(drv_data->cntl_bits,
0382             drv_data->reg_base + drv_data->reg_offsets.control);
0383         break;
0384 
0385     case MV64XXX_I2C_ACTION_SEND_ADDR_1:
0386         writel(drv_data->addr1,
0387             drv_data->reg_base + drv_data->reg_offsets.data);
0388         writel(drv_data->cntl_bits,
0389             drv_data->reg_base + drv_data->reg_offsets.control);
0390         break;
0391 
0392     case MV64XXX_I2C_ACTION_SEND_ADDR_2:
0393         writel(drv_data->addr2,
0394             drv_data->reg_base + drv_data->reg_offsets.data);
0395         writel(drv_data->cntl_bits,
0396             drv_data->reg_base + drv_data->reg_offsets.control);
0397         break;
0398 
0399     case MV64XXX_I2C_ACTION_SEND_DATA:
0400         writel(drv_data->msg->buf[drv_data->byte_posn++],
0401             drv_data->reg_base + drv_data->reg_offsets.data);
0402         writel(drv_data->cntl_bits,
0403             drv_data->reg_base + drv_data->reg_offsets.control);
0404         break;
0405 
0406     case MV64XXX_I2C_ACTION_RCV_DATA:
0407         drv_data->msg->buf[drv_data->byte_posn++] =
0408             readl(drv_data->reg_base + drv_data->reg_offsets.data);
0409         writel(drv_data->cntl_bits,
0410             drv_data->reg_base + drv_data->reg_offsets.control);
0411         break;
0412 
0413     case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
0414         drv_data->msg->buf[drv_data->byte_posn++] =
0415             readl(drv_data->reg_base + drv_data->reg_offsets.data);
0416         if (!drv_data->atomic)
0417             drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
0418         writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
0419             drv_data->reg_base + drv_data->reg_offsets.control);
0420         drv_data->block = 0;
0421         if (drv_data->errata_delay)
0422             udelay(5);
0423 
0424         wake_up(&drv_data->waitq);
0425         break;
0426 
0427     case MV64XXX_I2C_ACTION_INVALID:
0428     default:
0429         dev_err(&drv_data->adapter.dev,
0430             "mv64xxx_i2c_do_action: Invalid action: %d\n",
0431             drv_data->action);
0432         drv_data->rc = -EIO;
0433         fallthrough;
0434     case MV64XXX_I2C_ACTION_SEND_STOP:
0435         if (!drv_data->atomic)
0436             drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
0437         writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
0438             drv_data->reg_base + drv_data->reg_offsets.control);
0439         drv_data->block = 0;
0440         wake_up(&drv_data->waitq);
0441         break;
0442     }
0443 }
0444 
0445 static void
0446 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
0447                  struct i2c_msg *msg)
0448 {
0449     u32 buf[2];
0450 
0451     buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
0452     buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
0453 
0454     memcpy(msg->buf, buf, msg->len);
0455 }
0456 
0457 static int
0458 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
0459 {
0460     u32 cause, status;
0461 
0462     cause = readl(drv_data->reg_base +
0463               MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
0464     if (!cause)
0465         return IRQ_NONE;
0466 
0467     status = readl(drv_data->reg_base +
0468                MV64XXX_I2C_REG_BRIDGE_STATUS);
0469 
0470     if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
0471         drv_data->rc = -EIO;
0472         goto out;
0473     }
0474 
0475     drv_data->rc = 0;
0476 
0477     /*
0478      * Transaction is a one message read transaction, read data
0479      * for this message.
0480      */
0481     if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
0482         mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
0483         drv_data->msgs++;
0484         drv_data->num_msgs--;
0485     }
0486     /*
0487      * Transaction is a two messages write/read transaction, read
0488      * data for the second (read) message.
0489      */
0490     else if (drv_data->num_msgs == 2 &&
0491          !(drv_data->msgs[0].flags & I2C_M_RD) &&
0492          drv_data->msgs[1].flags & I2C_M_RD) {
0493         mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
0494         drv_data->msgs += 2;
0495         drv_data->num_msgs -= 2;
0496     }
0497 
0498 out:
0499     writel(0, drv_data->reg_base +  MV64XXX_I2C_REG_BRIDGE_CONTROL);
0500     writel(0, drv_data->reg_base +
0501            MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
0502     drv_data->block = 0;
0503 
0504     wake_up(&drv_data->waitq);
0505 
0506     return IRQ_HANDLED;
0507 }
0508 
0509 static irqreturn_t
0510 mv64xxx_i2c_intr(int irq, void *dev_id)
0511 {
0512     struct mv64xxx_i2c_data *drv_data = dev_id;
0513     u32     status;
0514     irqreturn_t rc = IRQ_NONE;
0515 
0516     spin_lock(&drv_data->lock);
0517 
0518     if (drv_data->offload_enabled)
0519         rc = mv64xxx_i2c_intr_offload(drv_data);
0520 
0521     while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
0522                         MV64XXX_I2C_REG_CONTROL_IFLG) {
0523         status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
0524         mv64xxx_i2c_fsm(drv_data, status);
0525         mv64xxx_i2c_do_action(drv_data);
0526 
0527         if (drv_data->irq_clear_inverted)
0528             writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
0529                    drv_data->reg_base + drv_data->reg_offsets.control);
0530 
0531         rc = IRQ_HANDLED;
0532     }
0533     spin_unlock(&drv_data->lock);
0534 
0535     return rc;
0536 }
0537 
0538 /*
0539  *****************************************************************************
0540  *
0541  *  I2C Msg Execution Routines
0542  *
0543  *****************************************************************************
0544  */
0545 static void
0546 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
0547 {
0548     long        time_left;
0549     unsigned long   flags;
0550     char        abort = 0;
0551 
0552     time_left = wait_event_timeout(drv_data->waitq,
0553         !drv_data->block, drv_data->adapter.timeout);
0554 
0555     spin_lock_irqsave(&drv_data->lock, flags);
0556     if (!time_left) { /* Timed out */
0557         drv_data->rc = -ETIMEDOUT;
0558         abort = 1;
0559     } else if (time_left < 0) { /* Interrupted/Error */
0560         drv_data->rc = time_left; /* errno value */
0561         abort = 1;
0562     }
0563 
0564     if (abort && drv_data->block) {
0565         drv_data->aborting = 1;
0566         spin_unlock_irqrestore(&drv_data->lock, flags);
0567 
0568         time_left = wait_event_timeout(drv_data->waitq,
0569             !drv_data->block, drv_data->adapter.timeout);
0570 
0571         if ((time_left <= 0) && drv_data->block) {
0572             drv_data->state = MV64XXX_I2C_STATE_IDLE;
0573             dev_err(&drv_data->adapter.dev,
0574                 "mv64xxx: I2C bus locked, block: %d, "
0575                 "time_left: %d\n", drv_data->block,
0576                 (int)time_left);
0577             mv64xxx_i2c_hw_init(drv_data);
0578             i2c_recover_bus(&drv_data->adapter);
0579         }
0580     } else
0581         spin_unlock_irqrestore(&drv_data->lock, flags);
0582 }
0583 
0584 static void mv64xxx_i2c_wait_polling(struct mv64xxx_i2c_data *drv_data)
0585 {
0586     ktime_t timeout = ktime_add_ms(ktime_get(), drv_data->adapter.timeout);
0587 
0588     while (READ_ONCE(drv_data->block) &&
0589            ktime_compare(ktime_get(), timeout) < 0) {
0590         udelay(5);
0591         mv64xxx_i2c_intr(0, drv_data);
0592     }
0593 }
0594 
0595 static int
0596 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
0597                 int is_last)
0598 {
0599     unsigned long   flags;
0600 
0601     spin_lock_irqsave(&drv_data->lock, flags);
0602 
0603     drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
0604 
0605     drv_data->send_stop = is_last;
0606     drv_data->block = 1;
0607     mv64xxx_i2c_send_start(drv_data);
0608     spin_unlock_irqrestore(&drv_data->lock, flags);
0609 
0610     if (!drv_data->atomic)
0611         mv64xxx_i2c_wait_for_completion(drv_data);
0612     else
0613         mv64xxx_i2c_wait_polling(drv_data);
0614 
0615     return drv_data->rc;
0616 }
0617 
0618 static void
0619 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
0620 {
0621     struct i2c_msg *msg = drv_data->msgs;
0622     u32 buf[2];
0623 
0624     memcpy(buf, msg->buf, msg->len);
0625 
0626     writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
0627     writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
0628 }
0629 
0630 static int
0631 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
0632 {
0633     struct i2c_msg *msgs = drv_data->msgs;
0634     int num = drv_data->num_msgs;
0635     unsigned long ctrl_reg;
0636     unsigned long flags;
0637 
0638     spin_lock_irqsave(&drv_data->lock, flags);
0639 
0640     /* Build transaction */
0641     ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
0642         (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
0643 
0644     if (msgs[0].flags & I2C_M_TEN)
0645         ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
0646 
0647     /* Single write message transaction */
0648     if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
0649         size_t len = msgs[0].len - 1;
0650 
0651         ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
0652             (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
0653         mv64xxx_i2c_prepare_tx(drv_data);
0654     }
0655     /* Single read message transaction */
0656     else if (num == 1 && msgs[0].flags & I2C_M_RD) {
0657         size_t len = msgs[0].len - 1;
0658 
0659         ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
0660             (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
0661     }
0662     /*
0663      * Transaction with one write and one read message. This is
0664      * guaranteed by the mv64xx_i2c_can_offload() checks.
0665      */
0666     else if (num == 2) {
0667         size_t lentx = msgs[0].len - 1;
0668         size_t lenrx = msgs[1].len - 1;
0669 
0670         ctrl_reg |=
0671             MV64XXX_I2C_BRIDGE_CONTROL_RD |
0672             MV64XXX_I2C_BRIDGE_CONTROL_WR |
0673             (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
0674             (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
0675             MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
0676         mv64xxx_i2c_prepare_tx(drv_data);
0677     }
0678 
0679     /* Execute transaction */
0680     drv_data->block = 1;
0681     writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
0682     spin_unlock_irqrestore(&drv_data->lock, flags);
0683 
0684     mv64xxx_i2c_wait_for_completion(drv_data);
0685 
0686     return drv_data->rc;
0687 }
0688 
0689 static bool
0690 mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
0691 {
0692     return msg->len <= 8 && msg->len >= 1;
0693 }
0694 
0695 static bool
0696 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
0697 {
0698     struct i2c_msg *msgs = drv_data->msgs;
0699     int num = drv_data->num_msgs;
0700 
0701     if (!drv_data->offload_enabled)
0702         return false;
0703 
0704     /*
0705      * We can offload a transaction consisting of a single
0706      * message, as long as the message has a length between 1 and
0707      * 8 bytes.
0708      */
0709     if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
0710         return true;
0711 
0712     /*
0713      * We can offload a transaction consisting of two messages, if
0714      * the first is a write and a second is a read, and both have
0715      * a length between 1 and 8 bytes.
0716      */
0717     if (num == 2 &&
0718         mv64xxx_i2c_valid_offload_sz(msgs) &&
0719         mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
0720         !(msgs[0].flags & I2C_M_RD) &&
0721         msgs[1].flags & I2C_M_RD)
0722         return true;
0723 
0724     return false;
0725 }
0726 
0727 /*
0728  *****************************************************************************
0729  *
0730  *  I2C Core Support Routines (Interface to higher level I2C code)
0731  *
0732  *****************************************************************************
0733  */
0734 static u32
0735 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
0736 {
0737     return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
0738 }
0739 
0740 static int
0741 mv64xxx_i2c_xfer_core(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
0742 {
0743     struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
0744     int rc, ret = num;
0745 
0746     rc = pm_runtime_resume_and_get(&adap->dev);
0747     if (rc)
0748         return rc;
0749 
0750     BUG_ON(drv_data->msgs != NULL);
0751     drv_data->msgs = msgs;
0752     drv_data->num_msgs = num;
0753 
0754     if (mv64xxx_i2c_can_offload(drv_data) && !drv_data->atomic)
0755         rc = mv64xxx_i2c_offload_xfer(drv_data);
0756     else
0757         rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
0758 
0759     if (rc < 0)
0760         ret = rc;
0761 
0762     drv_data->num_msgs = 0;
0763     drv_data->msgs = NULL;
0764 
0765     pm_runtime_mark_last_busy(&adap->dev);
0766     pm_runtime_put_autosuspend(&adap->dev);
0767 
0768     return ret;
0769 }
0770 
0771 static int
0772 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
0773 {
0774     struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
0775 
0776     drv_data->atomic = 0;
0777     return mv64xxx_i2c_xfer_core(adap, msgs, num);
0778 }
0779 
0780 static int mv64xxx_i2c_xfer_atomic(struct i2c_adapter *adap,
0781                    struct i2c_msg msgs[], int num)
0782 {
0783     struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
0784 
0785     drv_data->atomic = 1;
0786     return mv64xxx_i2c_xfer_core(adap, msgs, num);
0787 }
0788 
0789 static const struct i2c_algorithm mv64xxx_i2c_algo = {
0790     .master_xfer = mv64xxx_i2c_xfer,
0791     .master_xfer_atomic = mv64xxx_i2c_xfer_atomic,
0792     .functionality = mv64xxx_i2c_functionality,
0793 };
0794 
0795 /*
0796  *****************************************************************************
0797  *
0798  *  Driver Interface & Early Init Routines
0799  *
0800  *****************************************************************************
0801  */
0802 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
0803     { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
0804     { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
0805     { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
0806     { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
0807     { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
0808     {}
0809 };
0810 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
0811 
0812 #ifdef CONFIG_OF
0813 static int
0814 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
0815           const int tclk, const int n, const int m)
0816 {
0817     if (drv_data->clk_n_base_0)
0818         return tclk / (10 * (m + 1) * (1 << n));
0819     else
0820         return tclk / (10 * (m + 1) * (2 << n));
0821 }
0822 
0823 static bool
0824 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
0825               const u32 req_freq, const u32 tclk)
0826 {
0827     int freq, delta, best_delta = INT_MAX;
0828     int m, n;
0829 
0830     for (n = 0; n <= 7; n++)
0831         for (m = 0; m <= 15; m++) {
0832             freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
0833             delta = req_freq - freq;
0834             if (delta >= 0 && delta < best_delta) {
0835                 drv_data->freq_m = m;
0836                 drv_data->freq_n = n;
0837                 best_delta = delta;
0838             }
0839             if (best_delta == 0)
0840                 return true;
0841         }
0842     if (best_delta == INT_MAX)
0843         return false;
0844     return true;
0845 }
0846 
0847 static int
0848 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
0849           struct device *dev)
0850 {
0851     const struct of_device_id *device;
0852     struct device_node *np = dev->of_node;
0853     u32 bus_freq, tclk;
0854     int rc = 0;
0855 
0856     /* CLK is mandatory when using DT to describe the i2c bus. We
0857      * need to know tclk in order to calculate bus clock
0858      * factors.
0859      */
0860     if (!drv_data->clk) {
0861         rc = -ENODEV;
0862         goto out;
0863     }
0864     tclk = clk_get_rate(drv_data->clk);
0865 
0866     if (of_property_read_u32(np, "clock-frequency", &bus_freq))
0867         bus_freq = I2C_MAX_STANDARD_MODE_FREQ; /* 100kHz by default */
0868 
0869     if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
0870         of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
0871         drv_data->clk_n_base_0 = true;
0872 
0873     if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
0874         rc = -EINVAL;
0875         goto out;
0876     }
0877 
0878     drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
0879     if (IS_ERR(drv_data->rstc)) {
0880         rc = PTR_ERR(drv_data->rstc);
0881         goto out;
0882     }
0883 
0884     /* Its not yet defined how timeouts will be specified in device tree.
0885      * So hard code the value to 1 second.
0886      */
0887     drv_data->adapter.timeout = HZ;
0888 
0889     device = of_match_device(mv64xxx_i2c_of_match_table, dev);
0890     if (!device)
0891         return -ENODEV;
0892 
0893     memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
0894 
0895     /*
0896      * For controllers embedded in new SoCs activate the
0897      * Transaction Generator support and the errata fix.
0898      */
0899     if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
0900         drv_data->offload_enabled = true;
0901         /* The delay is only needed in standard mode (100kHz) */
0902         if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
0903             drv_data->errata_delay = true;
0904     }
0905 
0906     if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
0907         drv_data->offload_enabled = false;
0908         /* The delay is only needed in standard mode (100kHz) */
0909         if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
0910             drv_data->errata_delay = true;
0911     }
0912 
0913     if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
0914         drv_data->irq_clear_inverted = true;
0915 
0916 out:
0917     return rc;
0918 }
0919 #else /* CONFIG_OF */
0920 static int
0921 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
0922           struct device *dev)
0923 {
0924     return -ENODEV;
0925 }
0926 #endif /* CONFIG_OF */
0927 
0928 static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
0929                       struct device *dev)
0930 {
0931     struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo;
0932 
0933     rinfo->pinctrl = devm_pinctrl_get(dev);
0934     if (IS_ERR(rinfo->pinctrl)) {
0935         if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
0936             return -EPROBE_DEFER;
0937         dev_info(dev, "can't get pinctrl, bus recovery not supported\n");
0938         return PTR_ERR(rinfo->pinctrl);
0939     } else if (!rinfo->pinctrl) {
0940         return -ENODEV;
0941     }
0942 
0943     drv_data->adapter.bus_recovery_info = rinfo;
0944     return 0;
0945 }
0946 
0947 static int
0948 mv64xxx_i2c_runtime_suspend(struct device *dev)
0949 {
0950     struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
0951 
0952     reset_control_assert(drv_data->rstc);
0953     clk_disable_unprepare(drv_data->reg_clk);
0954     clk_disable_unprepare(drv_data->clk);
0955 
0956     return 0;
0957 }
0958 
0959 static int
0960 mv64xxx_i2c_runtime_resume(struct device *dev)
0961 {
0962     struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
0963 
0964     clk_prepare_enable(drv_data->clk);
0965     clk_prepare_enable(drv_data->reg_clk);
0966     reset_control_reset(drv_data->rstc);
0967 
0968     mv64xxx_i2c_hw_init(drv_data);
0969 
0970     return 0;
0971 }
0972 
0973 static int
0974 mv64xxx_i2c_probe(struct platform_device *pd)
0975 {
0976     struct mv64xxx_i2c_data     *drv_data;
0977     struct mv64xxx_i2c_pdata    *pdata = dev_get_platdata(&pd->dev);
0978     int rc;
0979 
0980     if ((!pdata && !pd->dev.of_node))
0981         return -ENODEV;
0982 
0983     drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
0984                 GFP_KERNEL);
0985     if (!drv_data)
0986         return -ENOMEM;
0987 
0988     drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
0989     if (IS_ERR(drv_data->reg_base))
0990         return PTR_ERR(drv_data->reg_base);
0991 
0992     strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
0993         sizeof(drv_data->adapter.name));
0994 
0995     init_waitqueue_head(&drv_data->waitq);
0996     spin_lock_init(&drv_data->lock);
0997 
0998     /* Not all platforms have clocks */
0999     drv_data->clk = devm_clk_get(&pd->dev, NULL);
1000     if (IS_ERR(drv_data->clk)) {
1001         if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
1002             return -EPROBE_DEFER;
1003         drv_data->clk = NULL;
1004     }
1005 
1006     drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
1007     if (IS_ERR(drv_data->reg_clk)) {
1008         if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
1009             return -EPROBE_DEFER;
1010         drv_data->reg_clk = NULL;
1011     }
1012 
1013     drv_data->irq = platform_get_irq(pd, 0);
1014     if (drv_data->irq < 0)
1015         return drv_data->irq;
1016 
1017     if (pdata) {
1018         drv_data->freq_m = pdata->freq_m;
1019         drv_data->freq_n = pdata->freq_n;
1020         drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
1021         drv_data->offload_enabled = false;
1022         memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
1023     } else if (pd->dev.of_node) {
1024         rc = mv64xxx_of_config(drv_data, &pd->dev);
1025         if (rc)
1026             return rc;
1027     }
1028 
1029     rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
1030     if (rc == -EPROBE_DEFER)
1031         return rc;
1032 
1033     drv_data->adapter.dev.parent = &pd->dev;
1034     drv_data->adapter.algo = &mv64xxx_i2c_algo;
1035     drv_data->adapter.owner = THIS_MODULE;
1036     drv_data->adapter.class = I2C_CLASS_DEPRECATED;
1037     drv_data->adapter.nr = pd->id;
1038     drv_data->adapter.dev.of_node = pd->dev.of_node;
1039     platform_set_drvdata(pd, drv_data);
1040     i2c_set_adapdata(&drv_data->adapter, drv_data);
1041 
1042     pm_runtime_set_autosuspend_delay(&pd->dev, MSEC_PER_SEC);
1043     pm_runtime_use_autosuspend(&pd->dev);
1044     pm_runtime_enable(&pd->dev);
1045     if (!pm_runtime_enabled(&pd->dev)) {
1046         rc = mv64xxx_i2c_runtime_resume(&pd->dev);
1047         if (rc)
1048             goto exit_disable_pm;
1049     }
1050 
1051     rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
1052              MV64XXX_I2C_CTLR_NAME, drv_data);
1053     if (rc) {
1054         dev_err(&drv_data->adapter.dev,
1055             "mv64xxx: Can't register intr handler irq%d: %d\n",
1056             drv_data->irq, rc);
1057         goto exit_disable_pm;
1058     } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
1059         dev_err(&drv_data->adapter.dev,
1060             "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1061         goto exit_free_irq;
1062     }
1063 
1064     return 0;
1065 
1066 exit_free_irq:
1067     free_irq(drv_data->irq, drv_data);
1068 exit_disable_pm:
1069     pm_runtime_disable(&pd->dev);
1070     if (!pm_runtime_status_suspended(&pd->dev))
1071         mv64xxx_i2c_runtime_suspend(&pd->dev);
1072 
1073     return rc;
1074 }
1075 
1076 static int
1077 mv64xxx_i2c_remove(struct platform_device *pd)
1078 {
1079     struct mv64xxx_i2c_data     *drv_data = platform_get_drvdata(pd);
1080 
1081     i2c_del_adapter(&drv_data->adapter);
1082     free_irq(drv_data->irq, drv_data);
1083     pm_runtime_disable(&pd->dev);
1084     if (!pm_runtime_status_suspended(&pd->dev))
1085         mv64xxx_i2c_runtime_suspend(&pd->dev);
1086 
1087     return 0;
1088 }
1089 
1090 static const struct dev_pm_ops mv64xxx_i2c_pm_ops = {
1091     SET_RUNTIME_PM_OPS(mv64xxx_i2c_runtime_suspend,
1092                mv64xxx_i2c_runtime_resume, NULL)
1093     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1094                       pm_runtime_force_resume)
1095 };
1096 
1097 static struct platform_driver mv64xxx_i2c_driver = {
1098     .probe  = mv64xxx_i2c_probe,
1099     .remove = mv64xxx_i2c_remove,
1100     .driver = {
1101         .name   = MV64XXX_I2C_CTLR_NAME,
1102         .pm     = &mv64xxx_i2c_pm_ops,
1103         .of_match_table = mv64xxx_i2c_of_match_table,
1104     },
1105 };
1106 
1107 module_platform_driver(mv64xxx_i2c_driver);
1108 
1109 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1110 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1111 MODULE_LICENSE("GPL");
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