i2c/busses/i2c-mt7621.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * drivers/i2c/busses/i2c-mt7621.c
0004  *
0005  * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
0006  * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
0007  * Copyright (C) 2018 Jan Breuer <jan.breuer@jaybee.cz>
0008  *
0009  * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
0010  * (C) 2014 Sittisak <sittisaks@hotmail.com>
0011  */
0012
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/i2c.h>
0016 #include <linux/io.h>
0017 #include <linux/iopoll.h>
0018 #include <linux/module.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/reset.h>
0021
0022 #define REG_SM0CFG2_REG     0x28
0023 #define REG_SM0CTL0_REG     0x40
0024 #define REG_SM0CTL1_REG     0x44
0025 #define REG_SM0D0_REG       0x50
0026 #define REG_SM0D1_REG       0x54
0027 #define REG_PINTEN_REG      0x5c
0028 #define REG_PINTST_REG      0x60
0029 #define REG_PINTCL_REG      0x64
0030
0031 /* REG_SM0CFG2_REG */
0032 #define SM0CFG2_IS_AUTOMODE BIT(0)
0033
0034 /* REG_SM0CTL0_REG */
0035 #define SM0CTL0_ODRAIN      BIT(31)
0036 #define SM0CTL0_CLK_DIV_MASK    (0x7ff << 16)
0037 #define SM0CTL0_CLK_DIV_MAX 0x7ff
0038 #define SM0CTL0_CS_STATUS       BIT(4)
0039 #define SM0CTL0_SCL_STATE       BIT(3)
0040 #define SM0CTL0_SDA_STATE       BIT(2)
0041 #define SM0CTL0_EN              BIT(1)
0042 #define SM0CTL0_SCL_STRETCH     BIT(0)
0043
0044 /* REG_SM0CTL1_REG */
0045 #define SM0CTL1_ACK_MASK    (0xff << 16)
0046 #define SM0CTL1_PGLEN_MASK  (0x7 << 8)
0047 #define SM0CTL1_PGLEN(x)    ((((x) - 1) << 8) & SM0CTL1_PGLEN_MASK)
0048 #define SM0CTL1_READ        (5 << 4)
0049 #define SM0CTL1_READ_LAST   (4 << 4)
0050 #define SM0CTL1_STOP        (3 << 4)
0051 #define SM0CTL1_WRITE       (2 << 4)
0052 #define SM0CTL1_START       (1 << 4)
0053 #define SM0CTL1_MODE_MASK   (0x7 << 4)
0054 #define SM0CTL1_TRI     BIT(0)
0055
0056 /* timeout waiting for I2C devices to respond */
0057 #define TIMEOUT_MS      1000
0058
0059 struct mtk_i2c {
0060     void __iomem *base;
0061     struct device *dev;
0062     struct i2c_adapter adap;
0063     u32 bus_freq;
0064     u32 clk_div;
0065     u32 flags;
0066     struct clk *clk;
0067 };
0068
0069 static int mtk_i2c_wait_idle(struct mtk_i2c *i2c)
0070 {
0071     int ret;
0072     u32 val;
0073
0074     ret = readl_relaxed_poll_timeout(i2c->base + REG_SM0CTL1_REG,
0075                      val, !(val & SM0CTL1_TRI),
0076                      10, TIMEOUT_MS * 1000);
0077     if (ret)
0078         dev_dbg(i2c->dev, "idle err(%d)\n", ret);
0079
0080     return ret;
0081 }
0082
0083 static void mtk_i2c_reset(struct mtk_i2c *i2c)
0084 {
0085     int ret;
0086
0087     ret = device_reset(i2c->adap.dev.parent);
0088     if (ret)
0089         dev_err(i2c->dev, "I2C reset failed!\n");
0090
0091     /*
0092      * Don't set SM0CTL0_ODRAIN as its bit meaning is inverted. To
0093      * configure open-drain mode, this bit needs to be cleared.
0094      */
0095     iowrite32(((i2c->clk_div << 16) & SM0CTL0_CLK_DIV_MASK) | SM0CTL0_EN |
0096           SM0CTL0_SCL_STRETCH, i2c->base + REG_SM0CTL0_REG);
0097     iowrite32(0, i2c->base + REG_SM0CFG2_REG);
0098 }
0099
0100 static void mtk_i2c_dump_reg(struct mtk_i2c *i2c)
0101 {
0102     dev_dbg(i2c->dev,
0103         "SM0CFG2 %08x, SM0CTL0 %08x, SM0CTL1 %08x, SM0D0 %08x, SM0D1 %08x\n",
0104         ioread32(i2c->base + REG_SM0CFG2_REG),
0105         ioread32(i2c->base + REG_SM0CTL0_REG),
0106         ioread32(i2c->base + REG_SM0CTL1_REG),
0107         ioread32(i2c->base + REG_SM0D0_REG),
0108         ioread32(i2c->base + REG_SM0D1_REG));
0109 }
0110
0111 static int mtk_i2c_check_ack(struct mtk_i2c *i2c, u32 expected)
0112 {
0113     u32 ack = readl_relaxed(i2c->base + REG_SM0CTL1_REG);
0114     u32 ack_expected = (expected << 16) & SM0CTL1_ACK_MASK;
0115
0116     return ((ack & ack_expected) == ack_expected) ? 0 : -ENXIO;
0117 }
0118
0119 static int mtk_i2c_master_start(struct mtk_i2c *i2c)
0120 {
0121     iowrite32(SM0CTL1_START | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
0122     return mtk_i2c_wait_idle(i2c);
0123 }
0124
0125 static int mtk_i2c_master_stop(struct mtk_i2c *i2c)
0126 {
0127     iowrite32(SM0CTL1_STOP | SM0CTL1_TRI, i2c->base + REG_SM0CTL1_REG);
0128     return mtk_i2c_wait_idle(i2c);
0129 }
0130
0131 static int mtk_i2c_master_cmd(struct mtk_i2c *i2c, u32 cmd, int page_len)
0132 {
0133     iowrite32(cmd | SM0CTL1_TRI | SM0CTL1_PGLEN(page_len),
0134           i2c->base + REG_SM0CTL1_REG);
0135     return mtk_i2c_wait_idle(i2c);
0136 }
0137
0138 static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
0139                    int num)
0140 {
0141     struct mtk_i2c *i2c;
0142     struct i2c_msg *pmsg;
0143     u16 addr;
0144     int i, j, ret, len, page_len;
0145     u32 cmd;
0146     u32 data[2];
0147
0148     i2c = i2c_get_adapdata(adap);
0149
0150     for (i = 0; i < num; i++) {
0151         pmsg = &msgs[i];
0152
0153         /* wait hardware idle */
0154         ret = mtk_i2c_wait_idle(i2c);
0155         if (ret)
0156             goto err_timeout;
0157
0158         /* start sequence */
0159         ret = mtk_i2c_master_start(i2c);
0160         if (ret)
0161             goto err_timeout;
0162
0163         /* write address */
0164         if (pmsg->flags & I2C_M_TEN) {
0165             /* 10 bits address */
0166             addr = 0xf0 | ((pmsg->addr >> 7) & 0x06);
0167             addr |= (pmsg->addr & 0xff) << 8;
0168             if (pmsg->flags & I2C_M_RD)
0169                 addr |= 1;
0170             iowrite32(addr, i2c->base + REG_SM0D0_REG);
0171             ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 2);
0172             if (ret)
0173                 goto err_timeout;
0174         } else {
0175             /* 7 bits address */
0176             addr = i2c_8bit_addr_from_msg(pmsg);
0177             iowrite32(addr, i2c->base + REG_SM0D0_REG);
0178             ret = mtk_i2c_master_cmd(i2c, SM0CTL1_WRITE, 1);
0179             if (ret)
0180                 goto err_timeout;
0181         }
0182
0183         /* check address ACK */
0184         if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
0185             ret = mtk_i2c_check_ack(i2c, BIT(0));
0186             if (ret)
0187                 goto err_ack;
0188         }
0189
0190         /* transfer data */
0191         for (len = pmsg->len, j = 0; len > 0; len -= 8, j += 8) {
0192             page_len = (len >= 8) ? 8 : len;
0193
0194             if (pmsg->flags & I2C_M_RD) {
0195                 cmd = (len > 8) ?
0196                     SM0CTL1_READ : SM0CTL1_READ_LAST;
0197             } else {
0198                 memcpy(data, &pmsg->buf[j], page_len);
0199                 iowrite32(data[0], i2c->base + REG_SM0D0_REG);
0200                 iowrite32(data[1], i2c->base + REG_SM0D1_REG);
0201                 cmd = SM0CTL1_WRITE;
0202             }
0203
0204             ret = mtk_i2c_master_cmd(i2c, cmd, page_len);
0205             if (ret)
0206                 goto err_timeout;
0207
0208             if (pmsg->flags & I2C_M_RD) {
0209                 data[0] = ioread32(i2c->base + REG_SM0D0_REG);
0210                 data[1] = ioread32(i2c->base + REG_SM0D1_REG);
0211                 memcpy(&pmsg->buf[j], data, page_len);
0212             } else {
0213                 if (!(pmsg->flags & I2C_M_IGNORE_NAK)) {
0214                     ret = mtk_i2c_check_ack(i2c,
0215                                 (1 << page_len)
0216                                 - 1);
0217                     if (ret)
0218                         goto err_ack;
0219                 }
0220             }
0221         }
0222     }
0223
0224     ret = mtk_i2c_master_stop(i2c);
0225     if (ret)
0226         goto err_timeout;
0227
0228     /* the return value is number of executed messages */
0229     return i;
0230
0231 err_ack:
0232     ret = mtk_i2c_master_stop(i2c);
0233     if (ret)
0234         goto err_timeout;
0235     return -ENXIO;
0236
0237 err_timeout:
0238     mtk_i2c_dump_reg(i2c);
0239     mtk_i2c_reset(i2c);
0240     return ret;
0241 }
0242
0243 static u32 mtk_i2c_func(struct i2c_adapter *a)
0244 {
0245     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
0246 }
0247
0248 static const struct i2c_algorithm mtk_i2c_algo = {
0249     .master_xfer    = mtk_i2c_master_xfer,
0250     .functionality  = mtk_i2c_func,
0251 };
0252
0253 static const struct of_device_id i2c_mtk_dt_ids[] = {
0254     { .compatible = "mediatek,mt7621-i2c" },
0255     { /* sentinel */ }
0256 };
0257
0258 MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids);
0259
0260 static void mtk_i2c_init(struct mtk_i2c *i2c)
0261 {
0262     i2c->clk_div = clk_get_rate(i2c->clk) / i2c->bus_freq - 1;
0263     if (i2c->clk_div < 99)
0264         i2c->clk_div = 99;
0265     if (i2c->clk_div > SM0CTL0_CLK_DIV_MAX)
0266         i2c->clk_div = SM0CTL0_CLK_DIV_MAX;
0267
0268     mtk_i2c_reset(i2c);
0269 }
0270
0271 static int mtk_i2c_probe(struct platform_device *pdev)
0272 {
0273     struct mtk_i2c *i2c;
0274     struct i2c_adapter *adap;
0275     int ret;
0276
0277     i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL);
0278     if (!i2c)
0279         return -ENOMEM;
0280
0281     i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
0282     if (IS_ERR(i2c->base))
0283         return PTR_ERR(i2c->base);
0284
0285     i2c->clk = devm_clk_get(&pdev->dev, NULL);
0286     if (IS_ERR(i2c->clk)) {
0287         dev_err(&pdev->dev, "no clock defined\n");
0288         return PTR_ERR(i2c->clk);
0289     }
0290     ret = clk_prepare_enable(i2c->clk);
0291     if (ret) {
0292         dev_err(&pdev->dev, "Unable to enable clock\n");
0293         return ret;
0294     }
0295
0296     i2c->dev = &pdev->dev;
0297
0298     if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
0299                  &i2c->bus_freq))
0300         i2c->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
0301
0302     if (i2c->bus_freq == 0) {
0303         dev_warn(i2c->dev, "clock-frequency 0 not supported\n");
0304         ret = -EINVAL;
0305         goto err_disable_clk;
0306     }
0307
0308     adap = &i2c->adap;
0309     adap->owner = THIS_MODULE;
0310     adap->algo = &mtk_i2c_algo;
0311     adap->retries = 3;
0312     adap->dev.parent = &pdev->dev;
0313     i2c_set_adapdata(adap, i2c);
0314     adap->dev.of_node = pdev->dev.of_node;
0315     strscpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
0316
0317     platform_set_drvdata(pdev, i2c);
0318
0319     mtk_i2c_init(i2c);
0320
0321     ret = i2c_add_adapter(adap);
0322     if (ret < 0)
0323         goto err_disable_clk;
0324
0325     dev_info(&pdev->dev, "clock %u kHz\n", i2c->bus_freq / 1000);
0326
0327     return 0;
0328
0329 err_disable_clk:
0330     clk_disable_unprepare(i2c->clk);
0331
0332     return ret;
0333 }
0334
0335 static int mtk_i2c_remove(struct platform_device *pdev)
0336 {
0337     struct mtk_i2c *i2c = platform_get_drvdata(pdev);
0338
0339     clk_disable_unprepare(i2c->clk);
0340     i2c_del_adapter(&i2c->adap);
0341
0342     return 0;
0343 }
0344
0345 static struct platform_driver mtk_i2c_driver = {
0346     .probe      = mtk_i2c_probe,
0347     .remove     = mtk_i2c_remove,
0348     .driver     = {
0349         .name   = "i2c-mt7621",
0350         .of_match_table = i2c_mtk_dt_ids,
0351     },
0352 };
0353
0354 module_platform_driver(mtk_i2c_driver);
0355
0356 MODULE_AUTHOR("Steven Liu");
0357 MODULE_DESCRIPTION("MT7621 I2C host driver");
0358 MODULE_LICENSE("GPL v2");
0359 MODULE_ALIAS("platform:MT7621-I2C");