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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Xudong Chen <xudong.chen@mediatek.com>
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/completion.h>
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/dma-mapping.h>
0012 #include <linux/err.h>
0013 #include <linux/errno.h>
0014 #include <linux/i2c.h>
0015 #include <linux/init.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/io.h>
0018 #include <linux/iopoll.h>
0019 #include <linux/kernel.h>
0020 #include <linux/mm.h>
0021 #include <linux/module.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_device.h>
0024 #include <linux/of_irq.h>
0025 #include <linux/platform_device.h>
0026 #include <linux/scatterlist.h>
0027 #include <linux/sched.h>
0028 #include <linux/slab.h>
0029 
0030 #define I2C_RS_TRANSFER         (1 << 4)
0031 #define I2C_ARB_LOST            (1 << 3)
0032 #define I2C_HS_NACKERR          (1 << 2)
0033 #define I2C_ACKERR          (1 << 1)
0034 #define I2C_TRANSAC_COMP        (1 << 0)
0035 #define I2C_TRANSAC_START       (1 << 0)
0036 #define I2C_RS_MUL_CNFG         (1 << 15)
0037 #define I2C_RS_MUL_TRIG         (1 << 14)
0038 #define I2C_DCM_DISABLE         0x0000
0039 #define I2C_IO_CONFIG_OPEN_DRAIN    0x0003
0040 #define I2C_IO_CONFIG_PUSH_PULL     0x0000
0041 #define I2C_SOFT_RST            0x0001
0042 #define I2C_HANDSHAKE_RST       0x0020
0043 #define I2C_FIFO_ADDR_CLR       0x0001
0044 #define I2C_DELAY_LEN           0x0002
0045 #define I2C_ST_START_CON        0x8001
0046 #define I2C_FS_START_CON        0x1800
0047 #define I2C_TIME_CLR_VALUE      0x0000
0048 #define I2C_TIME_DEFAULT_VALUE      0x0003
0049 #define I2C_WRRD_TRANAC_VALUE       0x0002
0050 #define I2C_RD_TRANAC_VALUE     0x0001
0051 #define I2C_SCL_MIS_COMP_VALUE      0x0000
0052 #define I2C_CHN_CLR_FLAG        0x0000
0053 #define I2C_RELIABILITY     0x0010
0054 #define I2C_DMAACK_ENABLE       0x0008
0055 
0056 #define I2C_DMA_CON_TX          0x0000
0057 #define I2C_DMA_CON_RX          0x0001
0058 #define I2C_DMA_ASYNC_MODE      0x0004
0059 #define I2C_DMA_SKIP_CONFIG     0x0010
0060 #define I2C_DMA_DIR_CHANGE      0x0200
0061 #define I2C_DMA_START_EN        0x0001
0062 #define I2C_DMA_INT_FLAG_NONE       0x0000
0063 #define I2C_DMA_CLR_FLAG        0x0000
0064 #define I2C_DMA_WARM_RST        0x0001
0065 #define I2C_DMA_HARD_RST        0x0002
0066 #define I2C_DMA_HANDSHAKE_RST       0x0004
0067 
0068 #define MAX_SAMPLE_CNT_DIV      8
0069 #define MAX_STEP_CNT_DIV        64
0070 #define MAX_CLOCK_DIV_8BITS     256
0071 #define MAX_CLOCK_DIV_5BITS     32
0072 #define MAX_HS_STEP_CNT_DIV     8
0073 #define I2C_STANDARD_MODE_BUFFER    (1000 / 3)
0074 #define I2C_FAST_MODE_BUFFER        (300 / 3)
0075 #define I2C_FAST_MODE_PLUS_BUFFER   (20 / 3)
0076 
0077 #define I2C_CONTROL_RS                  (0x1 << 1)
0078 #define I2C_CONTROL_DMA_EN              (0x1 << 2)
0079 #define I2C_CONTROL_CLK_EXT_EN          (0x1 << 3)
0080 #define I2C_CONTROL_DIR_CHANGE          (0x1 << 4)
0081 #define I2C_CONTROL_ACKERR_DET_EN       (0x1 << 5)
0082 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
0083 #define I2C_CONTROL_DMAACK_EN           (0x1 << 8)
0084 #define I2C_CONTROL_ASYNC_MODE          (0x1 << 9)
0085 #define I2C_CONTROL_WRAPPER             (0x1 << 0)
0086 
0087 #define I2C_DRV_NAME        "i2c-mt65xx"
0088 
0089 /**
0090  * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
0091  *
0092  * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
0093  * @I2C_MT65XX_CLK_DMA:  DMA clock for i2c via DMA
0094  * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
0095  * @I2C_MT65XX_CLK_ARB:  Arbitrator clock for i2c
0096  * @I2C_MT65XX_CLK_MAX:  Number of supported clocks
0097  */
0098 enum i2c_mt65xx_clks {
0099     I2C_MT65XX_CLK_MAIN = 0,
0100     I2C_MT65XX_CLK_DMA,
0101     I2C_MT65XX_CLK_PMIC,
0102     I2C_MT65XX_CLK_ARB,
0103     I2C_MT65XX_CLK_MAX
0104 };
0105 
0106 static const char * const i2c_mt65xx_clk_ids[I2C_MT65XX_CLK_MAX] = {
0107     "main", "dma", "pmic", "arb"
0108 };
0109 
0110 enum DMA_REGS_OFFSET {
0111     OFFSET_INT_FLAG = 0x0,
0112     OFFSET_INT_EN = 0x04,
0113     OFFSET_EN = 0x08,
0114     OFFSET_RST = 0x0c,
0115     OFFSET_CON = 0x18,
0116     OFFSET_TX_MEM_ADDR = 0x1c,
0117     OFFSET_RX_MEM_ADDR = 0x20,
0118     OFFSET_TX_LEN = 0x24,
0119     OFFSET_RX_LEN = 0x28,
0120     OFFSET_TX_4G_MODE = 0x54,
0121     OFFSET_RX_4G_MODE = 0x58,
0122 };
0123 
0124 enum i2c_trans_st_rs {
0125     I2C_TRANS_STOP = 0,
0126     I2C_TRANS_REPEATED_START,
0127 };
0128 
0129 enum mtk_trans_op {
0130     I2C_MASTER_WR = 1,
0131     I2C_MASTER_RD,
0132     I2C_MASTER_WRRD,
0133 };
0134 
0135 enum I2C_REGS_OFFSET {
0136     OFFSET_DATA_PORT,
0137     OFFSET_SLAVE_ADDR,
0138     OFFSET_INTR_MASK,
0139     OFFSET_INTR_STAT,
0140     OFFSET_CONTROL,
0141     OFFSET_TRANSFER_LEN,
0142     OFFSET_TRANSAC_LEN,
0143     OFFSET_DELAY_LEN,
0144     OFFSET_TIMING,
0145     OFFSET_START,
0146     OFFSET_EXT_CONF,
0147     OFFSET_FIFO_STAT,
0148     OFFSET_FIFO_THRESH,
0149     OFFSET_FIFO_ADDR_CLR,
0150     OFFSET_IO_CONFIG,
0151     OFFSET_RSV_DEBUG,
0152     OFFSET_HS,
0153     OFFSET_SOFTRESET,
0154     OFFSET_DCM_EN,
0155     OFFSET_MULTI_DMA,
0156     OFFSET_PATH_DIR,
0157     OFFSET_DEBUGSTAT,
0158     OFFSET_DEBUGCTRL,
0159     OFFSET_TRANSFER_LEN_AUX,
0160     OFFSET_CLOCK_DIV,
0161     OFFSET_LTIMING,
0162     OFFSET_SCL_HIGH_LOW_RATIO,
0163     OFFSET_HS_SCL_HIGH_LOW_RATIO,
0164     OFFSET_SCL_MIS_COMP_POINT,
0165     OFFSET_STA_STO_AC_TIMING,
0166     OFFSET_HS_STA_STO_AC_TIMING,
0167     OFFSET_SDA_TIMING,
0168 };
0169 
0170 static const u16 mt_i2c_regs_v1[] = {
0171     [OFFSET_DATA_PORT] = 0x0,
0172     [OFFSET_SLAVE_ADDR] = 0x4,
0173     [OFFSET_INTR_MASK] = 0x8,
0174     [OFFSET_INTR_STAT] = 0xc,
0175     [OFFSET_CONTROL] = 0x10,
0176     [OFFSET_TRANSFER_LEN] = 0x14,
0177     [OFFSET_TRANSAC_LEN] = 0x18,
0178     [OFFSET_DELAY_LEN] = 0x1c,
0179     [OFFSET_TIMING] = 0x20,
0180     [OFFSET_START] = 0x24,
0181     [OFFSET_EXT_CONF] = 0x28,
0182     [OFFSET_FIFO_STAT] = 0x30,
0183     [OFFSET_FIFO_THRESH] = 0x34,
0184     [OFFSET_FIFO_ADDR_CLR] = 0x38,
0185     [OFFSET_IO_CONFIG] = 0x40,
0186     [OFFSET_RSV_DEBUG] = 0x44,
0187     [OFFSET_HS] = 0x48,
0188     [OFFSET_SOFTRESET] = 0x50,
0189     [OFFSET_DCM_EN] = 0x54,
0190     [OFFSET_PATH_DIR] = 0x60,
0191     [OFFSET_DEBUGSTAT] = 0x64,
0192     [OFFSET_DEBUGCTRL] = 0x68,
0193     [OFFSET_TRANSFER_LEN_AUX] = 0x6c,
0194     [OFFSET_CLOCK_DIV] = 0x70,
0195     [OFFSET_SCL_HIGH_LOW_RATIO] = 0x74,
0196     [OFFSET_HS_SCL_HIGH_LOW_RATIO] = 0x78,
0197     [OFFSET_SCL_MIS_COMP_POINT] = 0x7C,
0198     [OFFSET_STA_STO_AC_TIMING] = 0x80,
0199     [OFFSET_HS_STA_STO_AC_TIMING] = 0x84,
0200     [OFFSET_SDA_TIMING] = 0x88,
0201 };
0202 
0203 static const u16 mt_i2c_regs_v2[] = {
0204     [OFFSET_DATA_PORT] = 0x0,
0205     [OFFSET_SLAVE_ADDR] = 0x4,
0206     [OFFSET_INTR_MASK] = 0x8,
0207     [OFFSET_INTR_STAT] = 0xc,
0208     [OFFSET_CONTROL] = 0x10,
0209     [OFFSET_TRANSFER_LEN] = 0x14,
0210     [OFFSET_TRANSAC_LEN] = 0x18,
0211     [OFFSET_DELAY_LEN] = 0x1c,
0212     [OFFSET_TIMING] = 0x20,
0213     [OFFSET_START] = 0x24,
0214     [OFFSET_EXT_CONF] = 0x28,
0215     [OFFSET_LTIMING] = 0x2c,
0216     [OFFSET_HS] = 0x30,
0217     [OFFSET_IO_CONFIG] = 0x34,
0218     [OFFSET_FIFO_ADDR_CLR] = 0x38,
0219     [OFFSET_SDA_TIMING] = 0x3c,
0220     [OFFSET_TRANSFER_LEN_AUX] = 0x44,
0221     [OFFSET_CLOCK_DIV] = 0x48,
0222     [OFFSET_SOFTRESET] = 0x50,
0223     [OFFSET_MULTI_DMA] = 0x8c,
0224     [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
0225     [OFFSET_DEBUGSTAT] = 0xe4,
0226     [OFFSET_DEBUGCTRL] = 0xe8,
0227     [OFFSET_FIFO_STAT] = 0xf4,
0228     [OFFSET_FIFO_THRESH] = 0xf8,
0229     [OFFSET_DCM_EN] = 0xf88,
0230 };
0231 
0232 static const u16 mt_i2c_regs_v3[] = {
0233     [OFFSET_DATA_PORT] = 0x0,
0234     [OFFSET_INTR_MASK] = 0x8,
0235     [OFFSET_INTR_STAT] = 0xc,
0236     [OFFSET_CONTROL] = 0x10,
0237     [OFFSET_TRANSFER_LEN] = 0x14,
0238     [OFFSET_TRANSAC_LEN] = 0x18,
0239     [OFFSET_DELAY_LEN] = 0x1c,
0240     [OFFSET_TIMING] = 0x20,
0241     [OFFSET_START] = 0x24,
0242     [OFFSET_EXT_CONF] = 0x28,
0243     [OFFSET_LTIMING] = 0x2c,
0244     [OFFSET_HS] = 0x30,
0245     [OFFSET_IO_CONFIG] = 0x34,
0246     [OFFSET_FIFO_ADDR_CLR] = 0x38,
0247     [OFFSET_SDA_TIMING] = 0x3c,
0248     [OFFSET_TRANSFER_LEN_AUX] = 0x44,
0249     [OFFSET_CLOCK_DIV] = 0x48,
0250     [OFFSET_SOFTRESET] = 0x50,
0251     [OFFSET_MULTI_DMA] = 0x8c,
0252     [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
0253     [OFFSET_SLAVE_ADDR] = 0x94,
0254     [OFFSET_DEBUGSTAT] = 0xe4,
0255     [OFFSET_DEBUGCTRL] = 0xe8,
0256     [OFFSET_FIFO_STAT] = 0xf4,
0257     [OFFSET_FIFO_THRESH] = 0xf8,
0258     [OFFSET_DCM_EN] = 0xf88,
0259 };
0260 
0261 struct mtk_i2c_compatible {
0262     const struct i2c_adapter_quirks *quirks;
0263     const u16 *regs;
0264     unsigned char pmic_i2c: 1;
0265     unsigned char dcm: 1;
0266     unsigned char auto_restart: 1;
0267     unsigned char aux_len_reg: 1;
0268     unsigned char timing_adjust: 1;
0269     unsigned char dma_sync: 1;
0270     unsigned char ltiming_adjust: 1;
0271     unsigned char apdma_sync: 1;
0272     unsigned char max_dma_support;
0273 };
0274 
0275 struct mtk_i2c_ac_timing {
0276     u16 htiming;
0277     u16 ltiming;
0278     u16 hs;
0279     u16 ext;
0280     u16 inter_clk_div;
0281     u16 scl_hl_ratio;
0282     u16 hs_scl_hl_ratio;
0283     u16 sta_stop;
0284     u16 hs_sta_stop;
0285     u16 sda_timing;
0286 };
0287 
0288 struct mtk_i2c {
0289     struct i2c_adapter adap;    /* i2c host adapter */
0290     struct device *dev;
0291     struct completion msg_complete;
0292     struct i2c_timings timing_info;
0293 
0294     /* set in i2c probe */
0295     void __iomem *base;     /* i2c base addr */
0296     void __iomem *pdmabase;     /* dma base address*/
0297     struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */
0298     bool have_pmic;         /* can use i2c pins from PMIC */
0299     bool use_push_pull;     /* IO config push-pull mode */
0300 
0301     u16 irq_stat;           /* interrupt status */
0302     unsigned int clk_src_div;
0303     unsigned int speed_hz;      /* The speed in transfer */
0304     enum mtk_trans_op op;
0305     u16 timing_reg;
0306     u16 high_speed_reg;
0307     u16 ltiming_reg;
0308     unsigned char auto_restart;
0309     bool ignore_restart_irq;
0310     struct mtk_i2c_ac_timing ac_timing;
0311     const struct mtk_i2c_compatible *dev_comp;
0312 };
0313 
0314 /**
0315  * struct i2c_spec_values:
0316  * @min_low_ns: min LOW period of the SCL clock
0317  * @min_su_sta_ns: min set-up time for a repeated START condition
0318  * @max_hd_dat_ns: max data hold time
0319  * @min_su_dat_ns: min data set-up time
0320  */
0321 struct i2c_spec_values {
0322     unsigned int min_low_ns;
0323     unsigned int min_su_sta_ns;
0324     unsigned int max_hd_dat_ns;
0325     unsigned int min_su_dat_ns;
0326 };
0327 
0328 static const struct i2c_spec_values standard_mode_spec = {
0329     .min_low_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
0330     .min_su_sta_ns = 4700 + I2C_STANDARD_MODE_BUFFER,
0331     .max_hd_dat_ns = 3450 - I2C_STANDARD_MODE_BUFFER,
0332     .min_su_dat_ns = 250 + I2C_STANDARD_MODE_BUFFER,
0333 };
0334 
0335 static const struct i2c_spec_values fast_mode_spec = {
0336     .min_low_ns = 1300 + I2C_FAST_MODE_BUFFER,
0337     .min_su_sta_ns = 600 + I2C_FAST_MODE_BUFFER,
0338     .max_hd_dat_ns = 900 - I2C_FAST_MODE_BUFFER,
0339     .min_su_dat_ns = 100 + I2C_FAST_MODE_BUFFER,
0340 };
0341 
0342 static const struct i2c_spec_values fast_mode_plus_spec = {
0343     .min_low_ns = 500 + I2C_FAST_MODE_PLUS_BUFFER,
0344     .min_su_sta_ns = 260 + I2C_FAST_MODE_PLUS_BUFFER,
0345     .max_hd_dat_ns = 400 - I2C_FAST_MODE_PLUS_BUFFER,
0346     .min_su_dat_ns = 50 + I2C_FAST_MODE_PLUS_BUFFER,
0347 };
0348 
0349 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
0350     .flags = I2C_AQ_COMB_WRITE_THEN_READ,
0351     .max_num_msgs = 1,
0352     .max_write_len = 255,
0353     .max_read_len = 255,
0354     .max_comb_1st_msg_len = 255,
0355     .max_comb_2nd_msg_len = 31,
0356 };
0357 
0358 static const struct i2c_adapter_quirks mt7622_i2c_quirks = {
0359     .max_num_msgs = 255,
0360 };
0361 
0362 static const struct i2c_adapter_quirks mt8183_i2c_quirks = {
0363     .flags = I2C_AQ_NO_ZERO_LEN,
0364 };
0365 
0366 static const struct mtk_i2c_compatible mt2712_compat = {
0367     .regs = mt_i2c_regs_v1,
0368     .pmic_i2c = 0,
0369     .dcm = 1,
0370     .auto_restart = 1,
0371     .aux_len_reg = 1,
0372     .timing_adjust = 1,
0373     .dma_sync = 0,
0374     .ltiming_adjust = 0,
0375     .apdma_sync = 0,
0376     .max_dma_support = 33,
0377 };
0378 
0379 static const struct mtk_i2c_compatible mt6577_compat = {
0380     .quirks = &mt6577_i2c_quirks,
0381     .regs = mt_i2c_regs_v1,
0382     .pmic_i2c = 0,
0383     .dcm = 1,
0384     .auto_restart = 0,
0385     .aux_len_reg = 0,
0386     .timing_adjust = 0,
0387     .dma_sync = 0,
0388     .ltiming_adjust = 0,
0389     .apdma_sync = 0,
0390     .max_dma_support = 32,
0391 };
0392 
0393 static const struct mtk_i2c_compatible mt6589_compat = {
0394     .quirks = &mt6577_i2c_quirks,
0395     .regs = mt_i2c_regs_v1,
0396     .pmic_i2c = 1,
0397     .dcm = 0,
0398     .auto_restart = 0,
0399     .aux_len_reg = 0,
0400     .timing_adjust = 0,
0401     .dma_sync = 0,
0402     .ltiming_adjust = 0,
0403     .apdma_sync = 0,
0404     .max_dma_support = 32,
0405 };
0406 
0407 static const struct mtk_i2c_compatible mt7622_compat = {
0408     .quirks = &mt7622_i2c_quirks,
0409     .regs = mt_i2c_regs_v1,
0410     .pmic_i2c = 0,
0411     .dcm = 1,
0412     .auto_restart = 1,
0413     .aux_len_reg = 1,
0414     .timing_adjust = 0,
0415     .dma_sync = 0,
0416     .ltiming_adjust = 0,
0417     .apdma_sync = 0,
0418     .max_dma_support = 32,
0419 };
0420 
0421 static const struct mtk_i2c_compatible mt8168_compat = {
0422     .regs = mt_i2c_regs_v1,
0423     .pmic_i2c = 0,
0424     .dcm = 1,
0425     .auto_restart = 1,
0426     .aux_len_reg = 1,
0427     .timing_adjust = 1,
0428     .dma_sync = 1,
0429     .ltiming_adjust = 0,
0430     .apdma_sync = 0,
0431     .max_dma_support = 33,
0432 };
0433 
0434 static const struct mtk_i2c_compatible mt8173_compat = {
0435     .regs = mt_i2c_regs_v1,
0436     .pmic_i2c = 0,
0437     .dcm = 1,
0438     .auto_restart = 1,
0439     .aux_len_reg = 1,
0440     .timing_adjust = 0,
0441     .dma_sync = 0,
0442     .ltiming_adjust = 0,
0443     .apdma_sync = 0,
0444     .max_dma_support = 33,
0445 };
0446 
0447 static const struct mtk_i2c_compatible mt8183_compat = {
0448     .quirks = &mt8183_i2c_quirks,
0449     .regs = mt_i2c_regs_v2,
0450     .pmic_i2c = 0,
0451     .dcm = 0,
0452     .auto_restart = 1,
0453     .aux_len_reg = 1,
0454     .timing_adjust = 1,
0455     .dma_sync = 1,
0456     .ltiming_adjust = 1,
0457     .apdma_sync = 0,
0458     .max_dma_support = 33,
0459 };
0460 
0461 static const struct mtk_i2c_compatible mt8186_compat = {
0462     .regs = mt_i2c_regs_v2,
0463     .pmic_i2c = 0,
0464     .dcm = 0,
0465     .auto_restart = 1,
0466     .aux_len_reg = 1,
0467     .timing_adjust = 1,
0468     .dma_sync = 0,
0469     .ltiming_adjust = 1,
0470     .apdma_sync = 0,
0471     .max_dma_support = 36,
0472 };
0473 
0474 static const struct mtk_i2c_compatible mt8188_compat = {
0475     .regs = mt_i2c_regs_v3,
0476     .pmic_i2c = 0,
0477     .dcm = 0,
0478     .auto_restart = 1,
0479     .aux_len_reg = 1,
0480     .timing_adjust = 1,
0481     .dma_sync = 0,
0482     .ltiming_adjust = 1,
0483     .apdma_sync = 1,
0484     .max_dma_support = 36,
0485 };
0486 
0487 static const struct mtk_i2c_compatible mt8192_compat = {
0488     .quirks = &mt8183_i2c_quirks,
0489     .regs = mt_i2c_regs_v2,
0490     .pmic_i2c = 0,
0491     .dcm = 0,
0492     .auto_restart = 1,
0493     .aux_len_reg = 1,
0494     .timing_adjust = 1,
0495     .dma_sync = 1,
0496     .ltiming_adjust = 1,
0497     .apdma_sync = 1,
0498     .max_dma_support = 36,
0499 };
0500 
0501 static const struct of_device_id mtk_i2c_of_match[] = {
0502     { .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
0503     { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
0504     { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
0505     { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
0506     { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
0507     { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
0508     { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
0509     { .compatible = "mediatek,mt8186-i2c", .data = &mt8186_compat },
0510     { .compatible = "mediatek,mt8188-i2c", .data = &mt8188_compat },
0511     { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
0512     {}
0513 };
0514 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
0515 
0516 static u16 mtk_i2c_readw(struct mtk_i2c *i2c, enum I2C_REGS_OFFSET reg)
0517 {
0518     return readw(i2c->base + i2c->dev_comp->regs[reg]);
0519 }
0520 
0521 static void mtk_i2c_writew(struct mtk_i2c *i2c, u16 val,
0522                enum I2C_REGS_OFFSET reg)
0523 {
0524     writew(val, i2c->base + i2c->dev_comp->regs[reg]);
0525 }
0526 
0527 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
0528 {
0529     u16 control_reg;
0530     u16 intr_stat_reg;
0531     u16 ext_conf_val;
0532 
0533     mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START);
0534     intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
0535     mtk_i2c_writew(i2c, intr_stat_reg, OFFSET_INTR_STAT);
0536 
0537     if (i2c->dev_comp->apdma_sync) {
0538         writel(I2C_DMA_WARM_RST, i2c->pdmabase + OFFSET_RST);
0539         udelay(10);
0540         writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
0541         udelay(10);
0542         writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_HARD_RST,
0543                i2c->pdmabase + OFFSET_RST);
0544         mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST | I2C_SOFT_RST,
0545                    OFFSET_SOFTRESET);
0546         udelay(10);
0547         writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
0548         mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
0549     } else {
0550         writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
0551         udelay(50);
0552         writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
0553         mtk_i2c_writew(i2c, I2C_SOFT_RST, OFFSET_SOFTRESET);
0554     }
0555 
0556     /* Set ioconfig */
0557     if (i2c->use_push_pull)
0558         mtk_i2c_writew(i2c, I2C_IO_CONFIG_PUSH_PULL, OFFSET_IO_CONFIG);
0559     else
0560         mtk_i2c_writew(i2c, I2C_IO_CONFIG_OPEN_DRAIN, OFFSET_IO_CONFIG);
0561 
0562     if (i2c->dev_comp->dcm)
0563         mtk_i2c_writew(i2c, I2C_DCM_DISABLE, OFFSET_DCM_EN);
0564 
0565     mtk_i2c_writew(i2c, i2c->timing_reg, OFFSET_TIMING);
0566     mtk_i2c_writew(i2c, i2c->high_speed_reg, OFFSET_HS);
0567     if (i2c->dev_comp->ltiming_adjust)
0568         mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING);
0569 
0570     if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ)
0571         ext_conf_val = I2C_ST_START_CON;
0572     else
0573         ext_conf_val = I2C_FS_START_CON;
0574 
0575     if (i2c->dev_comp->timing_adjust) {
0576         ext_conf_val = i2c->ac_timing.ext;
0577         mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div,
0578                    OFFSET_CLOCK_DIV);
0579         mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE,
0580                    OFFSET_SCL_MIS_COMP_POINT);
0581         mtk_i2c_writew(i2c, i2c->ac_timing.sda_timing,
0582                    OFFSET_SDA_TIMING);
0583 
0584         if (i2c->dev_comp->ltiming_adjust) {
0585             mtk_i2c_writew(i2c, i2c->ac_timing.htiming,
0586                        OFFSET_TIMING);
0587             mtk_i2c_writew(i2c, i2c->ac_timing.hs, OFFSET_HS);
0588             mtk_i2c_writew(i2c, i2c->ac_timing.ltiming,
0589                        OFFSET_LTIMING);
0590         } else {
0591             mtk_i2c_writew(i2c, i2c->ac_timing.scl_hl_ratio,
0592                        OFFSET_SCL_HIGH_LOW_RATIO);
0593             mtk_i2c_writew(i2c, i2c->ac_timing.hs_scl_hl_ratio,
0594                        OFFSET_HS_SCL_HIGH_LOW_RATIO);
0595             mtk_i2c_writew(i2c, i2c->ac_timing.sta_stop,
0596                        OFFSET_STA_STO_AC_TIMING);
0597             mtk_i2c_writew(i2c, i2c->ac_timing.hs_sta_stop,
0598                        OFFSET_HS_STA_STO_AC_TIMING);
0599         }
0600     }
0601     mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF);
0602 
0603     /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
0604     if (i2c->have_pmic)
0605         mtk_i2c_writew(i2c, I2C_CONTROL_WRAPPER, OFFSET_PATH_DIR);
0606 
0607     control_reg = I2C_CONTROL_ACKERR_DET_EN |
0608               I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
0609     if (i2c->dev_comp->dma_sync)
0610         control_reg |= I2C_CONTROL_DMAACK_EN | I2C_CONTROL_ASYNC_MODE;
0611 
0612     mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
0613     mtk_i2c_writew(i2c, I2C_DELAY_LEN, OFFSET_DELAY_LEN);
0614 }
0615 
0616 static const struct i2c_spec_values *mtk_i2c_get_spec(unsigned int speed)
0617 {
0618     if (speed <= I2C_MAX_STANDARD_MODE_FREQ)
0619         return &standard_mode_spec;
0620     else if (speed <= I2C_MAX_FAST_MODE_FREQ)
0621         return &fast_mode_spec;
0622     else
0623         return &fast_mode_plus_spec;
0624 }
0625 
0626 static int mtk_i2c_max_step_cnt(unsigned int target_speed)
0627 {
0628     if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ)
0629         return MAX_HS_STEP_CNT_DIV;
0630     else
0631         return MAX_STEP_CNT_DIV;
0632 }
0633 
0634 static int mtk_i2c_get_clk_div_restri(struct mtk_i2c *i2c,
0635                       unsigned int sample_cnt)
0636 {
0637     int clk_div_restri = 0;
0638 
0639     if (i2c->dev_comp->ltiming_adjust == 0)
0640         return 0;
0641 
0642     if (sample_cnt == 1) {
0643         if (i2c->ac_timing.inter_clk_div == 0)
0644             clk_div_restri = 0;
0645         else
0646             clk_div_restri = 1;
0647     } else {
0648         if (i2c->ac_timing.inter_clk_div == 0)
0649             clk_div_restri = -1;
0650         else if (i2c->ac_timing.inter_clk_div == 1)
0651             clk_div_restri = 0;
0652         else
0653             clk_div_restri = 1;
0654     }
0655 
0656     return clk_div_restri;
0657 }
0658 
0659 /*
0660  * Check and Calculate i2c ac-timing
0661  *
0662  * Hardware design:
0663  * sample_ns = (1000000000 * (sample_cnt + 1)) / clk_src
0664  * xxx_cnt_div =  spec->min_xxx_ns / sample_ns
0665  *
0666  * Sample_ns is rounded down for xxx_cnt_div would be greater
0667  * than the smallest spec.
0668  * The sda_timing is chosen as the middle value between
0669  * the largest and smallest.
0670  */
0671 static int mtk_i2c_check_ac_timing(struct mtk_i2c *i2c,
0672                    unsigned int clk_src,
0673                    unsigned int check_speed,
0674                    unsigned int step_cnt,
0675                    unsigned int sample_cnt)
0676 {
0677     const struct i2c_spec_values *spec;
0678     unsigned int su_sta_cnt, low_cnt, high_cnt, max_step_cnt;
0679     unsigned int sda_max, sda_min, clk_ns, max_sta_cnt = 0x3f;
0680     unsigned int sample_ns = div_u64(1000000000ULL * (sample_cnt + 1),
0681                      clk_src);
0682 
0683     if (!i2c->dev_comp->timing_adjust)
0684         return 0;
0685 
0686     if (i2c->dev_comp->ltiming_adjust)
0687         max_sta_cnt = 0x100;
0688 
0689     spec = mtk_i2c_get_spec(check_speed);
0690 
0691     if (i2c->dev_comp->ltiming_adjust)
0692         clk_ns = 1000000000 / clk_src;
0693     else
0694         clk_ns = sample_ns / 2;
0695 
0696     su_sta_cnt = DIV_ROUND_UP(spec->min_su_sta_ns +
0697                   i2c->timing_info.scl_int_delay_ns, clk_ns);
0698     if (su_sta_cnt > max_sta_cnt)
0699         return -1;
0700 
0701     low_cnt = DIV_ROUND_UP(spec->min_low_ns, sample_ns);
0702     max_step_cnt = mtk_i2c_max_step_cnt(check_speed);
0703     if ((2 * step_cnt) > low_cnt && low_cnt < max_step_cnt) {
0704         if (low_cnt > step_cnt) {
0705             high_cnt = 2 * step_cnt - low_cnt;
0706         } else {
0707             high_cnt = step_cnt;
0708             low_cnt = step_cnt;
0709         }
0710     } else {
0711         return -2;
0712     }
0713 
0714     sda_max = spec->max_hd_dat_ns / sample_ns;
0715     if (sda_max > low_cnt)
0716         sda_max = 0;
0717 
0718     sda_min = DIV_ROUND_UP(spec->min_su_dat_ns, sample_ns);
0719     if (sda_min < low_cnt)
0720         sda_min = 0;
0721 
0722     if (sda_min > sda_max)
0723         return -3;
0724 
0725     if (check_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
0726         if (i2c->dev_comp->ltiming_adjust) {
0727             i2c->ac_timing.hs = I2C_TIME_DEFAULT_VALUE |
0728                 (sample_cnt << 12) | (high_cnt << 8);
0729             i2c->ac_timing.ltiming &= ~GENMASK(15, 9);
0730             i2c->ac_timing.ltiming |= (sample_cnt << 12) |
0731                 (low_cnt << 9);
0732             i2c->ac_timing.ext &= ~GENMASK(7, 1);
0733             i2c->ac_timing.ext |= (su_sta_cnt << 1) | (1 << 0);
0734         } else {
0735             i2c->ac_timing.hs_scl_hl_ratio = (1 << 12) |
0736                 (high_cnt << 6) | low_cnt;
0737             i2c->ac_timing.hs_sta_stop = (su_sta_cnt << 8) |
0738                 su_sta_cnt;
0739         }
0740         i2c->ac_timing.sda_timing &= ~GENMASK(11, 6);
0741         i2c->ac_timing.sda_timing |= (1 << 12) |
0742             ((sda_max + sda_min) / 2) << 6;
0743     } else {
0744         if (i2c->dev_comp->ltiming_adjust) {
0745             i2c->ac_timing.htiming = (sample_cnt << 8) | (high_cnt);
0746             i2c->ac_timing.ltiming = (sample_cnt << 6) | (low_cnt);
0747             i2c->ac_timing.ext = (su_sta_cnt << 8) | (1 << 0);
0748         } else {
0749             i2c->ac_timing.scl_hl_ratio = (1 << 12) |
0750                 (high_cnt << 6) | low_cnt;
0751             i2c->ac_timing.sta_stop = (su_sta_cnt << 8) |
0752                 su_sta_cnt;
0753         }
0754 
0755         i2c->ac_timing.sda_timing = (1 << 12) |
0756             (sda_max + sda_min) / 2;
0757     }
0758 
0759     return 0;
0760 }
0761 
0762 /*
0763  * Calculate i2c port speed
0764  *
0765  * Hardware design:
0766  * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
0767  * clock_div: fixed in hardware, but may be various in different SoCs
0768  *
0769  * The calculation want to pick the highest bus frequency that is still
0770  * less than or equal to i2c->speed_hz. The calculation try to get
0771  * sample_cnt and step_cn
0772  */
0773 static int mtk_i2c_calculate_speed(struct mtk_i2c *i2c, unsigned int clk_src,
0774                    unsigned int target_speed,
0775                    unsigned int *timing_step_cnt,
0776                    unsigned int *timing_sample_cnt)
0777 {
0778     unsigned int step_cnt;
0779     unsigned int sample_cnt;
0780     unsigned int max_step_cnt;
0781     unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
0782     unsigned int base_step_cnt;
0783     unsigned int opt_div;
0784     unsigned int best_mul;
0785     unsigned int cnt_mul;
0786     int ret = -EINVAL;
0787     int clk_div_restri = 0;
0788 
0789     if (target_speed > I2C_MAX_HIGH_SPEED_MODE_FREQ)
0790         target_speed = I2C_MAX_HIGH_SPEED_MODE_FREQ;
0791 
0792     max_step_cnt = mtk_i2c_max_step_cnt(target_speed);
0793     base_step_cnt = max_step_cnt;
0794     /* Find the best combination */
0795     opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
0796     best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
0797 
0798     /* Search for the best pair (sample_cnt, step_cnt) with
0799      * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
0800      * 0 < step_cnt < max_step_cnt
0801      * sample_cnt * step_cnt >= opt_div
0802      * optimizing for sample_cnt * step_cnt being minimal
0803      */
0804     for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
0805         clk_div_restri = mtk_i2c_get_clk_div_restri(i2c, sample_cnt);
0806         step_cnt = DIV_ROUND_UP(opt_div + clk_div_restri, sample_cnt);
0807         cnt_mul = step_cnt * sample_cnt;
0808         if (step_cnt > max_step_cnt)
0809             continue;
0810 
0811         if (cnt_mul < best_mul) {
0812             ret = mtk_i2c_check_ac_timing(i2c, clk_src,
0813                 target_speed, step_cnt - 1, sample_cnt - 1);
0814             if (ret)
0815                 continue;
0816 
0817             best_mul = cnt_mul;
0818             base_sample_cnt = sample_cnt;
0819             base_step_cnt = step_cnt;
0820             if (best_mul == (opt_div + clk_div_restri))
0821                 break;
0822         }
0823     }
0824 
0825     if (ret)
0826         return -EINVAL;
0827 
0828     sample_cnt = base_sample_cnt;
0829     step_cnt = base_step_cnt;
0830 
0831     if ((clk_src / (2 * (sample_cnt * step_cnt - clk_div_restri))) >
0832         target_speed) {
0833         /* In this case, hardware can't support such
0834          * low i2c_bus_freq
0835          */
0836         dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
0837         return -EINVAL;
0838     }
0839 
0840     *timing_step_cnt = step_cnt - 1;
0841     *timing_sample_cnt = sample_cnt - 1;
0842 
0843     return 0;
0844 }
0845 
0846 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
0847 {
0848     unsigned int clk_src;
0849     unsigned int step_cnt;
0850     unsigned int sample_cnt;
0851     unsigned int l_step_cnt;
0852     unsigned int l_sample_cnt;
0853     unsigned int target_speed;
0854     unsigned int clk_div;
0855     unsigned int max_clk_div;
0856     int ret;
0857 
0858     target_speed = i2c->speed_hz;
0859     parent_clk /= i2c->clk_src_div;
0860 
0861     if (i2c->dev_comp->timing_adjust && i2c->dev_comp->ltiming_adjust)
0862         max_clk_div = MAX_CLOCK_DIV_5BITS;
0863     else if (i2c->dev_comp->timing_adjust)
0864         max_clk_div = MAX_CLOCK_DIV_8BITS;
0865     else
0866         max_clk_div = 1;
0867 
0868     for (clk_div = 1; clk_div <= max_clk_div; clk_div++) {
0869         clk_src = parent_clk / clk_div;
0870         i2c->ac_timing.inter_clk_div = clk_div - 1;
0871 
0872         if (target_speed > I2C_MAX_FAST_MODE_PLUS_FREQ) {
0873             /* Set master code speed register */
0874             ret = mtk_i2c_calculate_speed(i2c, clk_src,
0875                               I2C_MAX_FAST_MODE_FREQ,
0876                               &l_step_cnt,
0877                               &l_sample_cnt);
0878             if (ret < 0)
0879                 continue;
0880 
0881             i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
0882 
0883             /* Set the high speed mode register */
0884             ret = mtk_i2c_calculate_speed(i2c, clk_src,
0885                               target_speed, &step_cnt,
0886                               &sample_cnt);
0887             if (ret < 0)
0888                 continue;
0889 
0890             i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
0891                     (sample_cnt << 12) | (step_cnt << 8);
0892 
0893             if (i2c->dev_comp->ltiming_adjust)
0894                 i2c->ltiming_reg =
0895                     (l_sample_cnt << 6) | l_step_cnt |
0896                     (sample_cnt << 12) | (step_cnt << 9);
0897         } else {
0898             ret = mtk_i2c_calculate_speed(i2c, clk_src,
0899                               target_speed, &l_step_cnt,
0900                               &l_sample_cnt);
0901             if (ret < 0)
0902                 continue;
0903 
0904             i2c->timing_reg = (l_sample_cnt << 8) | l_step_cnt;
0905 
0906             /* Disable the high speed transaction */
0907             i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
0908 
0909             if (i2c->dev_comp->ltiming_adjust)
0910                 i2c->ltiming_reg =
0911                     (l_sample_cnt << 6) | l_step_cnt;
0912         }
0913 
0914         break;
0915     }
0916 
0917 
0918     return 0;
0919 }
0920 
0921 static void i2c_dump_register(struct mtk_i2c *i2c)
0922 {
0923     dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
0924         mtk_i2c_readw(i2c, OFFSET_SLAVE_ADDR),
0925         mtk_i2c_readw(i2c, OFFSET_INTR_MASK));
0926     dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
0927         mtk_i2c_readw(i2c, OFFSET_INTR_STAT),
0928         mtk_i2c_readw(i2c, OFFSET_CONTROL));
0929     dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
0930         mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN),
0931         mtk_i2c_readw(i2c, OFFSET_TRANSAC_LEN));
0932     dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
0933         mtk_i2c_readw(i2c, OFFSET_DELAY_LEN),
0934         mtk_i2c_readw(i2c, OFFSET_TIMING));
0935     dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
0936         mtk_i2c_readw(i2c, OFFSET_START),
0937         mtk_i2c_readw(i2c, OFFSET_EXT_CONF));
0938     dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
0939         mtk_i2c_readw(i2c, OFFSET_HS),
0940         mtk_i2c_readw(i2c, OFFSET_IO_CONFIG));
0941     dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
0942         mtk_i2c_readw(i2c, OFFSET_DCM_EN),
0943         mtk_i2c_readw(i2c, OFFSET_TRANSFER_LEN_AUX));
0944     dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
0945         mtk_i2c_readw(i2c, OFFSET_CLOCK_DIV),
0946         mtk_i2c_readw(i2c, OFFSET_FIFO_STAT));
0947     dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
0948         mtk_i2c_readw(i2c, OFFSET_DEBUGCTRL),
0949         mtk_i2c_readw(i2c, OFFSET_DEBUGSTAT));
0950     if (i2c->dev_comp->regs == mt_i2c_regs_v2) {
0951         dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
0952             mtk_i2c_readw(i2c, OFFSET_LTIMING),
0953             mtk_i2c_readw(i2c, OFFSET_MULTI_DMA));
0954     }
0955     dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
0956         readl(i2c->pdmabase + OFFSET_INT_FLAG),
0957         readl(i2c->pdmabase + OFFSET_INT_EN));
0958     dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
0959         readl(i2c->pdmabase + OFFSET_EN),
0960         readl(i2c->pdmabase + OFFSET_CON));
0961     dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
0962         readl(i2c->pdmabase + OFFSET_TX_MEM_ADDR),
0963         readl(i2c->pdmabase + OFFSET_RX_MEM_ADDR));
0964     dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
0965         readl(i2c->pdmabase + OFFSET_TX_LEN),
0966         readl(i2c->pdmabase + OFFSET_RX_LEN));
0967     dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
0968         readl(i2c->pdmabase + OFFSET_TX_4G_MODE),
0969         readl(i2c->pdmabase + OFFSET_RX_4G_MODE));
0970 }
0971 
0972 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
0973                    int num, int left_num)
0974 {
0975     u16 addr_reg;
0976     u16 start_reg;
0977     u16 control_reg;
0978     u16 restart_flag = 0;
0979     u16 dma_sync = 0;
0980     u32 reg_4g_mode;
0981     u32 reg_dma_reset;
0982     u8 *dma_rd_buf = NULL;
0983     u8 *dma_wr_buf = NULL;
0984     dma_addr_t rpaddr = 0;
0985     dma_addr_t wpaddr = 0;
0986     int ret;
0987 
0988     i2c->irq_stat = 0;
0989 
0990     if (i2c->auto_restart)
0991         restart_flag = I2C_RS_TRANSFER;
0992 
0993     reinit_completion(&i2c->msg_complete);
0994 
0995     if (i2c->dev_comp->apdma_sync &&
0996         i2c->op != I2C_MASTER_WRRD && num > 1) {
0997         mtk_i2c_writew(i2c, 0x00, OFFSET_DEBUGCTRL);
0998         writel(I2C_DMA_HANDSHAKE_RST | I2C_DMA_WARM_RST,
0999                i2c->pdmabase + OFFSET_RST);
1000 
1001         ret = readw_poll_timeout(i2c->pdmabase + OFFSET_RST,
1002                      reg_dma_reset,
1003                      !(reg_dma_reset & I2C_DMA_WARM_RST),
1004                      0, 100);
1005         if (ret) {
1006             dev_err(i2c->dev, "DMA warm reset timeout\n");
1007             return -ETIMEDOUT;
1008         }
1009 
1010         writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
1011         mtk_i2c_writew(i2c, I2C_HANDSHAKE_RST, OFFSET_SOFTRESET);
1012         mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_SOFTRESET);
1013         mtk_i2c_writew(i2c, I2C_RELIABILITY | I2C_DMAACK_ENABLE,
1014                    OFFSET_DEBUGCTRL);
1015     }
1016 
1017     control_reg = mtk_i2c_readw(i2c, OFFSET_CONTROL) &
1018             ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
1019     if ((i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) || (left_num >= 1))
1020         control_reg |= I2C_CONTROL_RS;
1021 
1022     if (i2c->op == I2C_MASTER_WRRD)
1023         control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
1024 
1025     mtk_i2c_writew(i2c, control_reg, OFFSET_CONTROL);
1026 
1027     addr_reg = i2c_8bit_addr_from_msg(msgs);
1028     mtk_i2c_writew(i2c, addr_reg, OFFSET_SLAVE_ADDR);
1029 
1030     /* Clear interrupt status */
1031     mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1032                 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_STAT);
1033 
1034     mtk_i2c_writew(i2c, I2C_FIFO_ADDR_CLR, OFFSET_FIFO_ADDR_CLR);
1035 
1036     /* Enable interrupt */
1037     mtk_i2c_writew(i2c, restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1038                 I2C_ARB_LOST | I2C_TRANSAC_COMP, OFFSET_INTR_MASK);
1039 
1040     /* Set transfer and transaction len */
1041     if (i2c->op == I2C_MASTER_WRRD) {
1042         if (i2c->dev_comp->aux_len_reg) {
1043             mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
1044             mtk_i2c_writew(i2c, (msgs + 1)->len,
1045                         OFFSET_TRANSFER_LEN_AUX);
1046         } else {
1047             mtk_i2c_writew(i2c, msgs->len | ((msgs + 1)->len) << 8,
1048                         OFFSET_TRANSFER_LEN);
1049         }
1050         mtk_i2c_writew(i2c, I2C_WRRD_TRANAC_VALUE, OFFSET_TRANSAC_LEN);
1051     } else {
1052         mtk_i2c_writew(i2c, msgs->len, OFFSET_TRANSFER_LEN);
1053         mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
1054     }
1055 
1056     if (i2c->dev_comp->apdma_sync) {
1057         dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
1058         if (i2c->op == I2C_MASTER_WRRD)
1059             dma_sync |= I2C_DMA_DIR_CHANGE;
1060     }
1061 
1062     /* Prepare buffer data to start transfer */
1063     if (i2c->op == I2C_MASTER_RD) {
1064         writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
1065         writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
1066 
1067         dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
1068         if (!dma_rd_buf)
1069             return -ENOMEM;
1070 
1071         rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1072                     msgs->len, DMA_FROM_DEVICE);
1073         if (dma_mapping_error(i2c->dev, rpaddr)) {
1074             i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, false);
1075 
1076             return -ENOMEM;
1077         }
1078 
1079         if (i2c->dev_comp->max_dma_support > 32) {
1080             reg_4g_mode = upper_32_bits(rpaddr);
1081             writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1082         }
1083 
1084         writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1085         writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
1086     } else if (i2c->op == I2C_MASTER_WR) {
1087         writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
1088         writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
1089 
1090         dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
1091         if (!dma_wr_buf)
1092             return -ENOMEM;
1093 
1094         wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1095                     msgs->len, DMA_TO_DEVICE);
1096         if (dma_mapping_error(i2c->dev, wpaddr)) {
1097             i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1098 
1099             return -ENOMEM;
1100         }
1101 
1102         if (i2c->dev_comp->max_dma_support > 32) {
1103             reg_4g_mode = upper_32_bits(wpaddr);
1104             writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
1105         }
1106 
1107         writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1108         writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1109     } else {
1110         writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
1111         writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
1112 
1113         dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
1114         if (!dma_wr_buf)
1115             return -ENOMEM;
1116 
1117         wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1118                     msgs->len, DMA_TO_DEVICE);
1119         if (dma_mapping_error(i2c->dev, wpaddr)) {
1120             i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1121 
1122             return -ENOMEM;
1123         }
1124 
1125         dma_rd_buf = i2c_get_dma_safe_msg_buf((msgs + 1), 1);
1126         if (!dma_rd_buf) {
1127             dma_unmap_single(i2c->dev, wpaddr,
1128                      msgs->len, DMA_TO_DEVICE);
1129 
1130             i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1131 
1132             return -ENOMEM;
1133         }
1134 
1135         rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1136                     (msgs + 1)->len,
1137                     DMA_FROM_DEVICE);
1138         if (dma_mapping_error(i2c->dev, rpaddr)) {
1139             dma_unmap_single(i2c->dev, wpaddr,
1140                      msgs->len, DMA_TO_DEVICE);
1141 
1142             i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, false);
1143             i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), false);
1144 
1145             return -ENOMEM;
1146         }
1147 
1148         if (i2c->dev_comp->max_dma_support > 32) {
1149             reg_4g_mode = upper_32_bits(wpaddr);
1150             writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
1151 
1152             reg_4g_mode = upper_32_bits(rpaddr);
1153             writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
1154         }
1155 
1156         writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
1157         writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
1158         writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
1159         writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
1160     }
1161 
1162     writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
1163 
1164     if (!i2c->auto_restart) {
1165         start_reg = I2C_TRANSAC_START;
1166     } else {
1167         start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
1168         if (left_num >= 1)
1169             start_reg |= I2C_RS_MUL_CNFG;
1170     }
1171     mtk_i2c_writew(i2c, start_reg, OFFSET_START);
1172 
1173     ret = wait_for_completion_timeout(&i2c->msg_complete,
1174                       i2c->adap.timeout);
1175 
1176     /* Clear interrupt mask */
1177     mtk_i2c_writew(i2c, ~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
1178                 I2C_ARB_LOST | I2C_TRANSAC_COMP), OFFSET_INTR_MASK);
1179 
1180     if (i2c->op == I2C_MASTER_WR) {
1181         dma_unmap_single(i2c->dev, wpaddr,
1182                  msgs->len, DMA_TO_DEVICE);
1183 
1184         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1185     } else if (i2c->op == I2C_MASTER_RD) {
1186         dma_unmap_single(i2c->dev, rpaddr,
1187                  msgs->len, DMA_FROM_DEVICE);
1188 
1189         i2c_put_dma_safe_msg_buf(dma_rd_buf, msgs, true);
1190     } else {
1191         dma_unmap_single(i2c->dev, wpaddr, msgs->len,
1192                  DMA_TO_DEVICE);
1193         dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
1194                  DMA_FROM_DEVICE);
1195 
1196         i2c_put_dma_safe_msg_buf(dma_wr_buf, msgs, true);
1197         i2c_put_dma_safe_msg_buf(dma_rd_buf, (msgs + 1), true);
1198     }
1199 
1200     if (ret == 0) {
1201         dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
1202         i2c_dump_register(i2c);
1203         mtk_i2c_init_hw(i2c);
1204         return -ETIMEDOUT;
1205     }
1206 
1207     if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
1208         dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
1209         mtk_i2c_init_hw(i2c);
1210         return -ENXIO;
1211     }
1212 
1213     return 0;
1214 }
1215 
1216 static int mtk_i2c_transfer(struct i2c_adapter *adap,
1217                 struct i2c_msg msgs[], int num)
1218 {
1219     int ret;
1220     int left_num = num;
1221     struct mtk_i2c *i2c = i2c_get_adapdata(adap);
1222 
1223     ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1224     if (ret)
1225         return ret;
1226 
1227     i2c->auto_restart = i2c->dev_comp->auto_restart;
1228 
1229     /* checking if we can skip restart and optimize using WRRD mode */
1230     if (i2c->auto_restart && num == 2) {
1231         if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
1232             msgs[0].addr == msgs[1].addr) {
1233             i2c->auto_restart = 0;
1234         }
1235     }
1236 
1237     if (i2c->auto_restart && num >= 2 &&
1238         i2c->speed_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1239         /* ignore the first restart irq after the master code,
1240          * otherwise the first transfer will be discarded.
1241          */
1242         i2c->ignore_restart_irq = true;
1243     else
1244         i2c->ignore_restart_irq = false;
1245 
1246     while (left_num--) {
1247         if (!msgs->buf) {
1248             dev_dbg(i2c->dev, "data buffer is NULL.\n");
1249             ret = -EINVAL;
1250             goto err_exit;
1251         }
1252 
1253         if (msgs->flags & I2C_M_RD)
1254             i2c->op = I2C_MASTER_RD;
1255         else
1256             i2c->op = I2C_MASTER_WR;
1257 
1258         if (!i2c->auto_restart) {
1259             if (num > 1) {
1260                 /* combined two messages into one transaction */
1261                 i2c->op = I2C_MASTER_WRRD;
1262                 left_num--;
1263             }
1264         }
1265 
1266         /* always use DMA mode. */
1267         ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
1268         if (ret < 0)
1269             goto err_exit;
1270 
1271         msgs++;
1272     }
1273     /* the return value is number of executed messages */
1274     ret = num;
1275 
1276 err_exit:
1277     clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1278     return ret;
1279 }
1280 
1281 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
1282 {
1283     struct mtk_i2c *i2c = dev_id;
1284     u16 restart_flag = 0;
1285     u16 intr_stat;
1286 
1287     if (i2c->auto_restart)
1288         restart_flag = I2C_RS_TRANSFER;
1289 
1290     intr_stat = mtk_i2c_readw(i2c, OFFSET_INTR_STAT);
1291     mtk_i2c_writew(i2c, intr_stat, OFFSET_INTR_STAT);
1292 
1293     /*
1294      * when occurs ack error, i2c controller generate two interrupts
1295      * first is the ack error interrupt, then the complete interrupt
1296      * i2c->irq_stat need keep the two interrupt value.
1297      */
1298     i2c->irq_stat |= intr_stat;
1299 
1300     if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
1301         i2c->ignore_restart_irq = false;
1302         i2c->irq_stat = 0;
1303         mtk_i2c_writew(i2c, I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG |
1304                     I2C_TRANSAC_START, OFFSET_START);
1305     } else {
1306         if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
1307             complete(&i2c->msg_complete);
1308     }
1309 
1310     return IRQ_HANDLED;
1311 }
1312 
1313 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
1314 {
1315     if (i2c_check_quirks(adap, I2C_AQ_NO_ZERO_LEN))
1316         return I2C_FUNC_I2C |
1317             (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1318     else
1319         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1320 }
1321 
1322 static const struct i2c_algorithm mtk_i2c_algorithm = {
1323     .master_xfer = mtk_i2c_transfer,
1324     .functionality = mtk_i2c_functionality,
1325 };
1326 
1327 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c)
1328 {
1329     int ret;
1330 
1331     ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
1332     if (ret < 0)
1333         i2c->speed_hz = I2C_MAX_STANDARD_MODE_FREQ;
1334 
1335     ret = of_property_read_u32(np, "clock-div", &i2c->clk_src_div);
1336     if (ret < 0)
1337         return ret;
1338 
1339     if (i2c->clk_src_div == 0)
1340         return -EINVAL;
1341 
1342     i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
1343     i2c->use_push_pull =
1344         of_property_read_bool(np, "mediatek,use-push-pull");
1345 
1346     i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true);
1347 
1348     return 0;
1349 }
1350 
1351 static int mtk_i2c_probe(struct platform_device *pdev)
1352 {
1353     int ret = 0;
1354     struct mtk_i2c *i2c;
1355     struct resource *res;
1356     int i, irq, speed_clk;
1357 
1358     i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1359     if (!i2c)
1360         return -ENOMEM;
1361 
1362     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1363     i2c->base = devm_ioremap_resource(&pdev->dev, res);
1364     if (IS_ERR(i2c->base))
1365         return PTR_ERR(i2c->base);
1366 
1367     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1368     i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
1369     if (IS_ERR(i2c->pdmabase))
1370         return PTR_ERR(i2c->pdmabase);
1371 
1372     irq = platform_get_irq(pdev, 0);
1373     if (irq < 0)
1374         return irq;
1375 
1376     init_completion(&i2c->msg_complete);
1377 
1378     i2c->dev_comp = of_device_get_match_data(&pdev->dev);
1379     i2c->adap.dev.of_node = pdev->dev.of_node;
1380     i2c->dev = &pdev->dev;
1381     i2c->adap.dev.parent = &pdev->dev;
1382     i2c->adap.owner = THIS_MODULE;
1383     i2c->adap.algo = &mtk_i2c_algorithm;
1384     i2c->adap.quirks = i2c->dev_comp->quirks;
1385     i2c->adap.timeout = 2 * HZ;
1386     i2c->adap.retries = 1;
1387     i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus");
1388     if (IS_ERR(i2c->adap.bus_regulator)) {
1389         if (PTR_ERR(i2c->adap.bus_regulator) == -ENODEV)
1390             i2c->adap.bus_regulator = NULL;
1391         else
1392             return PTR_ERR(i2c->adap.bus_regulator);
1393     }
1394 
1395     ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
1396     if (ret)
1397         return -EINVAL;
1398 
1399     if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
1400         return -EINVAL;
1401 
1402     /* Fill in clk-bulk IDs */
1403     for (i = 0; i < I2C_MT65XX_CLK_MAX; i++)
1404         i2c->clocks[i].id = i2c_mt65xx_clk_ids[i];
1405 
1406     /* Get clocks one by one, some may be optional */
1407     i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main");
1408     if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) {
1409         dev_err(&pdev->dev, "cannot get main clock\n");
1410         return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk);
1411     }
1412 
1413     i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma");
1414     if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk)) {
1415         dev_err(&pdev->dev, "cannot get dma clock\n");
1416         return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_DMA].clk);
1417     }
1418 
1419     i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb");
1420     if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
1421         return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
1422 
1423     if (i2c->have_pmic) {
1424         i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
1425         if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
1426             dev_err(&pdev->dev, "cannot get pmic clock\n");
1427             return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
1428         }
1429         speed_clk = I2C_MT65XX_CLK_PMIC;
1430     } else {
1431         i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
1432         speed_clk = I2C_MT65XX_CLK_MAIN;
1433     }
1434 
1435     strscpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
1436 
1437     ret = mtk_i2c_set_speed(i2c, clk_get_rate(i2c->clocks[speed_clk].clk));
1438     if (ret) {
1439         dev_err(&pdev->dev, "Failed to set the speed.\n");
1440         return -EINVAL;
1441     }
1442 
1443     if (i2c->dev_comp->max_dma_support > 32) {
1444         ret = dma_set_mask(&pdev->dev,
1445                 DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
1446         if (ret) {
1447             dev_err(&pdev->dev, "dma_set_mask return error.\n");
1448             return ret;
1449         }
1450     }
1451 
1452     ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1453     if (ret) {
1454         dev_err(&pdev->dev, "clock enable failed!\n");
1455         return ret;
1456     }
1457     mtk_i2c_init_hw(i2c);
1458     clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1459 
1460     ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1461                    IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE,
1462                    dev_name(&pdev->dev), i2c);
1463     if (ret < 0) {
1464         dev_err(&pdev->dev,
1465             "Request I2C IRQ %d fail\n", irq);
1466         goto err_bulk_unprepare;
1467     }
1468 
1469     i2c_set_adapdata(&i2c->adap, i2c);
1470     ret = i2c_add_adapter(&i2c->adap);
1471     if (ret)
1472         goto err_bulk_unprepare;
1473 
1474     platform_set_drvdata(pdev, i2c);
1475 
1476     return 0;
1477 
1478 err_bulk_unprepare:
1479     clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1480 
1481     return ret;
1482 }
1483 
1484 static int mtk_i2c_remove(struct platform_device *pdev)
1485 {
1486     struct mtk_i2c *i2c = platform_get_drvdata(pdev);
1487 
1488     i2c_del_adapter(&i2c->adap);
1489 
1490     clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1491 
1492     return 0;
1493 }
1494 
1495 #ifdef CONFIG_PM_SLEEP
1496 static int mtk_i2c_suspend_noirq(struct device *dev)
1497 {
1498     struct mtk_i2c *i2c = dev_get_drvdata(dev);
1499 
1500     i2c_mark_adapter_suspended(&i2c->adap);
1501     clk_bulk_unprepare(I2C_MT65XX_CLK_MAX, i2c->clocks);
1502 
1503     return 0;
1504 }
1505 
1506 static int mtk_i2c_resume_noirq(struct device *dev)
1507 {
1508     int ret;
1509     struct mtk_i2c *i2c = dev_get_drvdata(dev);
1510 
1511     ret = clk_bulk_prepare_enable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1512     if (ret) {
1513         dev_err(dev, "clock enable failed!\n");
1514         return ret;
1515     }
1516 
1517     mtk_i2c_init_hw(i2c);
1518 
1519     clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks);
1520 
1521     i2c_mark_adapter_resumed(&i2c->adap);
1522 
1523     return 0;
1524 }
1525 #endif
1526 
1527 static const struct dev_pm_ops mtk_i2c_pm = {
1528     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_i2c_suspend_noirq,
1529                       mtk_i2c_resume_noirq)
1530 };
1531 
1532 static struct platform_driver mtk_i2c_driver = {
1533     .probe = mtk_i2c_probe,
1534     .remove = mtk_i2c_remove,
1535     .driver = {
1536         .name = I2C_DRV_NAME,
1537         .pm = &mtk_i2c_pm,
1538         .of_match_table = of_match_ptr(mtk_i2c_of_match),
1539     },
1540 };
1541 
1542 module_platform_driver(mtk_i2c_driver);
1543 
1544 MODULE_LICENSE("GPL v2");
1545 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
1546 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
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