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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * This is a combined i2c adapter and algorithm driver for the
0004  * MPC107/Tsi107 PowerPC northbridge and processors that include
0005  * the same I2C unit (8240, 8245, 85xx).
0006  *
0007  * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
0008  * Copyright (C) 2021 Allied Telesis Labs
0009  */
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/sched/signal.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/property.h>
0018 #include <linux/slab.h>
0019 
0020 #include <linux/clk.h>
0021 #include <linux/io.h>
0022 #include <linux/iopoll.h>
0023 #include <linux/fsl_devices.h>
0024 #include <linux/i2c.h>
0025 #include <linux/interrupt.h>
0026 #include <linux/delay.h>
0027 
0028 #include <asm/mpc52xx.h>
0029 #include <asm/mpc85xx.h>
0030 #include <sysdev/fsl_soc.h>
0031 
0032 #define DRV_NAME "mpc-i2c"
0033 
0034 #define MPC_I2C_CLOCK_LEGACY   0
0035 #define MPC_I2C_CLOCK_PRESERVE (~0U)
0036 
0037 #define MPC_I2C_FDR   0x04
0038 #define MPC_I2C_CR    0x08
0039 #define MPC_I2C_SR    0x0c
0040 #define MPC_I2C_DR    0x10
0041 #define MPC_I2C_DFSRR 0x14
0042 
0043 #define CCR_MEN  0x80
0044 #define CCR_MIEN 0x40
0045 #define CCR_MSTA 0x20
0046 #define CCR_MTX  0x10
0047 #define CCR_TXAK 0x08
0048 #define CCR_RSTA 0x04
0049 #define CCR_RSVD 0x02
0050 
0051 #define CSR_MCF  0x80
0052 #define CSR_MAAS 0x40
0053 #define CSR_MBB  0x20
0054 #define CSR_MAL  0x10
0055 #define CSR_SRW  0x04
0056 #define CSR_MIF  0x02
0057 #define CSR_RXAK 0x01
0058 
0059 enum mpc_i2c_action {
0060     MPC_I2C_ACTION_START = 1,
0061     MPC_I2C_ACTION_RESTART,
0062     MPC_I2C_ACTION_READ_BEGIN,
0063     MPC_I2C_ACTION_READ_BYTE,
0064     MPC_I2C_ACTION_WRITE,
0065     MPC_I2C_ACTION_STOP,
0066 
0067     __MPC_I2C_ACTION_CNT
0068 };
0069 
0070 static const char * const action_str[] = {
0071     "invalid",
0072     "start",
0073     "restart",
0074     "read begin",
0075     "read",
0076     "write",
0077     "stop",
0078 };
0079 
0080 static_assert(ARRAY_SIZE(action_str) == __MPC_I2C_ACTION_CNT);
0081 
0082 struct mpc_i2c {
0083     struct device *dev;
0084     void __iomem *base;
0085     u32 interrupt;
0086     wait_queue_head_t waitq;
0087     spinlock_t lock;
0088     struct i2c_adapter adap;
0089     int irq;
0090     u32 real_clk;
0091     u8 fdr, dfsrr;
0092     struct clk *clk_per;
0093     u32 cntl_bits;
0094     enum mpc_i2c_action action;
0095     struct i2c_msg *msgs;
0096     int num_msgs;
0097     int curr_msg;
0098     u32 byte_posn;
0099     u32 block;
0100     int rc;
0101     int expect_rxack;
0102     bool has_errata_A004447;
0103 };
0104 
0105 struct mpc_i2c_divider {
0106     u16 divider;
0107     u16 fdr;    /* including dfsrr */
0108 };
0109 
0110 struct mpc_i2c_data {
0111     void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
0112 };
0113 
0114 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
0115 {
0116     writeb(x, i2c->base + MPC_I2C_CR);
0117 }
0118 
0119 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
0120  * the bus, because it wants to send ACK.
0121  * Following sequence of enabling/disabling and sending start/stop generates
0122  * the 9 pulses, each with a START then ending with STOP, so it's all OK.
0123  */
0124 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
0125 {
0126     int k;
0127     unsigned long flags;
0128 
0129     for (k = 9; k; k--) {
0130         writeccr(i2c, 0);
0131         writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */
0132         writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */
0133         readb(i2c->base + MPC_I2C_DR); /* init xfer */
0134         udelay(15); /* let it hit the bus */
0135         local_irq_save(flags); /* should not be delayed further */
0136         writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */
0137         readb(i2c->base + MPC_I2C_DR);
0138         if (k != 1)
0139             udelay(5);
0140         local_irq_restore(flags);
0141     }
0142     writeccr(i2c, CCR_MEN); /* Initiate STOP */
0143     readb(i2c->base + MPC_I2C_DR);
0144     udelay(15); /* Let STOP propagate */
0145     writeccr(i2c, 0);
0146 }
0147 
0148 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
0149 {
0150     void __iomem *addr = i2c->base + MPC_I2C_SR;
0151     u8 val;
0152 
0153     return readb_poll_timeout(addr, val, val & mask, 0, 100);
0154 }
0155 
0156 /*
0157  * Workaround for Erratum A004447. From the P2040CE Rev Q
0158  *
0159  * 1.  Set up the frequency divider and sampling rate.
0160  * 2.  I2CCR - a0h
0161  * 3.  Poll for I2CSR[MBB] to get set.
0162  * 4.  If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
0163  *     step 5. If MAL is not set, then go to step 13.
0164  * 5.  I2CCR - 00h
0165  * 6.  I2CCR - 22h
0166  * 7.  I2CCR - a2h
0167  * 8.  Poll for I2CSR[MBB] to get set.
0168  * 9.  Issue read to I2CDR.
0169  * 10. Poll for I2CSR[MIF] to be set.
0170  * 11. I2CCR - 82h
0171  * 12. Workaround complete. Skip the next steps.
0172  * 13. Issue read to I2CDR.
0173  * 14. Poll for I2CSR[MIF] to be set.
0174  * 15. I2CCR - 80h
0175  */
0176 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
0177 {
0178     int ret;
0179     u32 val;
0180 
0181     writeccr(i2c, CCR_MEN | CCR_MSTA);
0182     ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
0183     if (ret) {
0184         dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
0185         return;
0186     }
0187 
0188     val = readb(i2c->base + MPC_I2C_SR);
0189 
0190     if (val & CSR_MAL) {
0191         writeccr(i2c, 0x00);
0192         writeccr(i2c, CCR_MSTA | CCR_RSVD);
0193         writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
0194         ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
0195         if (ret) {
0196             dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
0197             return;
0198         }
0199         val = readb(i2c->base + MPC_I2C_DR);
0200         ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
0201         if (ret) {
0202             dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
0203             return;
0204         }
0205         writeccr(i2c, CCR_MEN | CCR_RSVD);
0206     } else {
0207         val = readb(i2c->base + MPC_I2C_DR);
0208         ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
0209         if (ret) {
0210             dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
0211             return;
0212         }
0213         writeccr(i2c, CCR_MEN);
0214     }
0215 }
0216 
0217 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
0218 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
0219     {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
0220     {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
0221     {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
0222     {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
0223     {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
0224     {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
0225     {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
0226     {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
0227     {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
0228     {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
0229     {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
0230     {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
0231     {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
0232     {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
0233     {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
0234     {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
0235     {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
0236     {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
0237 };
0238 
0239 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
0240                       u32 *real_clk)
0241 {
0242     struct fwnode_handle *fwnode = of_fwnode_handle(node);
0243     const struct mpc_i2c_divider *div = NULL;
0244     unsigned int pvr = mfspr(SPRN_PVR);
0245     u32 divider;
0246     int i;
0247 
0248     if (clock == MPC_I2C_CLOCK_LEGACY) {
0249         /* see below - default fdr = 0x3f -> div = 2048 */
0250         *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / 2048;
0251         return -EINVAL;
0252     }
0253 
0254     /* Determine divider value */
0255     divider = mpc5xxx_fwnode_get_bus_frequency(fwnode) / clock;
0256 
0257     /*
0258      * We want to choose an FDR/DFSR that generates an I2C bus speed that
0259      * is equal to or lower than the requested speed.
0260      */
0261     for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
0262         div = &mpc_i2c_dividers_52xx[i];
0263         /* Old MPC5200 rev A CPUs do not support the high bits */
0264         if (div->fdr & 0xc0 && pvr == 0x80822011)
0265             continue;
0266         if (div->divider >= divider)
0267             break;
0268     }
0269 
0270     *real_clk = mpc5xxx_fwnode_get_bus_frequency(fwnode) / div->divider;
0271     return (int)div->fdr;
0272 }
0273 
0274 static void mpc_i2c_setup_52xx(struct device_node *node,
0275                      struct mpc_i2c *i2c,
0276                      u32 clock)
0277 {
0278     int ret, fdr;
0279 
0280     if (clock == MPC_I2C_CLOCK_PRESERVE) {
0281         dev_dbg(i2c->dev, "using fdr %d\n",
0282             readb(i2c->base + MPC_I2C_FDR));
0283         return;
0284     }
0285 
0286     ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
0287     fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
0288 
0289     writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
0290 
0291     if (ret >= 0)
0292         dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
0293              fdr);
0294 }
0295 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
0296 static void mpc_i2c_setup_52xx(struct device_node *node,
0297                      struct mpc_i2c *i2c,
0298                      u32 clock)
0299 {
0300 }
0301 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
0302 
0303 #ifdef CONFIG_PPC_MPC512x
0304 static void mpc_i2c_setup_512x(struct device_node *node,
0305                      struct mpc_i2c *i2c,
0306                      u32 clock)
0307 {
0308     struct device_node *node_ctrl;
0309     void __iomem *ctrl;
0310     const u32 *pval;
0311     u32 idx;
0312 
0313     /* Enable I2C interrupts for mpc5121 */
0314     node_ctrl = of_find_compatible_node(NULL, NULL,
0315                         "fsl,mpc5121-i2c-ctrl");
0316     if (node_ctrl) {
0317         ctrl = of_iomap(node_ctrl, 0);
0318         if (ctrl) {
0319             /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
0320             pval = of_get_property(node, "reg", NULL);
0321             idx = (*pval & 0xff) / 0x20;
0322             setbits32(ctrl, 1 << (24 + idx * 2));
0323             iounmap(ctrl);
0324         }
0325         of_node_put(node_ctrl);
0326     }
0327 
0328     /* The clock setup for the 52xx works also fine for the 512x */
0329     mpc_i2c_setup_52xx(node, i2c, clock);
0330 }
0331 #else /* CONFIG_PPC_MPC512x */
0332 static void mpc_i2c_setup_512x(struct device_node *node,
0333                      struct mpc_i2c *i2c,
0334                      u32 clock)
0335 {
0336 }
0337 #endif /* CONFIG_PPC_MPC512x */
0338 
0339 #ifdef CONFIG_FSL_SOC
0340 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
0341     {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
0342     {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
0343     {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
0344     {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
0345     {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
0346     {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
0347     {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
0348     {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
0349     {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
0350     {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
0351     {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
0352     {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
0353     {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
0354     {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
0355     {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
0356     {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
0357     {49152, 0x011e}, {61440, 0x011f}
0358 };
0359 
0360 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
0361 {
0362     struct device_node *node;
0363     u32 __iomem *reg;
0364     u32 val = 0;
0365 
0366     node = of_find_node_by_name(NULL, "global-utilities");
0367     if (node) {
0368         const u32 *prop = of_get_property(node, "reg", NULL);
0369         if (prop) {
0370             /*
0371              * Map and check POR Device Status Register 2
0372              * (PORDEVSR2) at 0xE0014. Note than while MPC8533
0373              * and MPC8544 indicate SEC frequency ratio
0374              * configuration as bit 26 in PORDEVSR2, other MPC8xxx
0375              * parts may store it differently or may not have it
0376              * at all.
0377              */
0378             reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
0379             if (!reg)
0380                 printk(KERN_ERR
0381                        "Error: couldn't map PORDEVSR2\n");
0382             else
0383                 val = in_be32(reg) & 0x00000020; /* sec-cfg */
0384             iounmap(reg);
0385         }
0386     }
0387     of_node_put(node);
0388 
0389     return val;
0390 }
0391 
0392 static u32 mpc_i2c_get_prescaler_8xxx(void)
0393 {
0394     /*
0395      * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
0396      * may have prescaler 1, 2, or 3, depending on the power-on
0397      * configuration.
0398      */
0399     u32 prescaler = 1;
0400 
0401     /* mpc85xx */
0402     if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
0403         || pvr_version_is(PVR_VER_E500MC)
0404         || pvr_version_is(PVR_VER_E5500)
0405         || pvr_version_is(PVR_VER_E6500)) {
0406         unsigned int svr = mfspr(SPRN_SVR);
0407 
0408         if ((SVR_SOC_VER(svr) == SVR_8540)
0409             || (SVR_SOC_VER(svr) == SVR_8541)
0410             || (SVR_SOC_VER(svr) == SVR_8560)
0411             || (SVR_SOC_VER(svr) == SVR_8555)
0412             || (SVR_SOC_VER(svr) == SVR_8610))
0413             /* the above 85xx SoCs have prescaler 1 */
0414             prescaler = 1;
0415         else if ((SVR_SOC_VER(svr) == SVR_8533)
0416             || (SVR_SOC_VER(svr) == SVR_8544))
0417             /* the above 85xx SoCs have prescaler 3 or 2 */
0418             prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
0419         else
0420             /* all the other 85xx have prescaler 2 */
0421             prescaler = 2;
0422     }
0423 
0424     return prescaler;
0425 }
0426 
0427 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
0428                       u32 *real_clk)
0429 {
0430     const struct mpc_i2c_divider *div = NULL;
0431     u32 prescaler = mpc_i2c_get_prescaler_8xxx();
0432     u32 divider;
0433     int i;
0434 
0435     if (clock == MPC_I2C_CLOCK_LEGACY) {
0436         /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
0437         *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
0438         return -EINVAL;
0439     }
0440 
0441     divider = fsl_get_sys_freq() / clock / prescaler;
0442 
0443     pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
0444          fsl_get_sys_freq(), clock, divider);
0445 
0446     /*
0447      * We want to choose an FDR/DFSR that generates an I2C bus speed that
0448      * is equal to or lower than the requested speed.
0449      */
0450     for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
0451         div = &mpc_i2c_dividers_8xxx[i];
0452         if (div->divider >= divider)
0453             break;
0454     }
0455 
0456     *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
0457     return (int)div->fdr;
0458 }
0459 
0460 static void mpc_i2c_setup_8xxx(struct device_node *node,
0461                      struct mpc_i2c *i2c,
0462                      u32 clock)
0463 {
0464     int ret, fdr;
0465 
0466     if (clock == MPC_I2C_CLOCK_PRESERVE) {
0467         dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
0468             readb(i2c->base + MPC_I2C_DFSRR),
0469             readb(i2c->base + MPC_I2C_FDR));
0470         return;
0471     }
0472 
0473     ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
0474     fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
0475 
0476     writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
0477     writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
0478 
0479     if (ret >= 0)
0480         dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
0481              i2c->real_clk, fdr >> 8, fdr & 0xff);
0482 }
0483 
0484 #else /* !CONFIG_FSL_SOC */
0485 static void mpc_i2c_setup_8xxx(struct device_node *node,
0486                      struct mpc_i2c *i2c,
0487                      u32 clock)
0488 {
0489 }
0490 #endif /* CONFIG_FSL_SOC */
0491 
0492 static void mpc_i2c_finish(struct mpc_i2c *i2c, int rc)
0493 {
0494     i2c->rc = rc;
0495     i2c->block = 0;
0496     i2c->cntl_bits = CCR_MEN;
0497     writeccr(i2c, i2c->cntl_bits);
0498     wake_up(&i2c->waitq);
0499 }
0500 
0501 static void mpc_i2c_do_action(struct mpc_i2c *i2c)
0502 {
0503     struct i2c_msg *msg = NULL;
0504     int dir = 0;
0505     int recv_len = 0;
0506     u8 byte;
0507 
0508     dev_dbg(i2c->dev, "action = %s\n", action_str[i2c->action]);
0509 
0510     i2c->cntl_bits &= ~(CCR_RSTA | CCR_MTX | CCR_TXAK);
0511 
0512     if (i2c->action != MPC_I2C_ACTION_STOP) {
0513         msg = &i2c->msgs[i2c->curr_msg];
0514         if (msg->flags & I2C_M_RD)
0515             dir = 1;
0516         if (msg->flags & I2C_M_RECV_LEN)
0517             recv_len = 1;
0518     }
0519 
0520     switch (i2c->action) {
0521     case MPC_I2C_ACTION_RESTART:
0522         i2c->cntl_bits |= CCR_RSTA;
0523         fallthrough;
0524 
0525     case MPC_I2C_ACTION_START:
0526         i2c->cntl_bits |= CCR_MSTA | CCR_MTX;
0527         writeccr(i2c, i2c->cntl_bits);
0528         writeb((msg->addr << 1) | dir, i2c->base + MPC_I2C_DR);
0529         i2c->expect_rxack = 1;
0530         i2c->action = dir ? MPC_I2C_ACTION_READ_BEGIN : MPC_I2C_ACTION_WRITE;
0531         break;
0532 
0533     case MPC_I2C_ACTION_READ_BEGIN:
0534         if (msg->len) {
0535             if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN))
0536                 i2c->cntl_bits |= CCR_TXAK;
0537 
0538             writeccr(i2c, i2c->cntl_bits);
0539             /* Dummy read */
0540             readb(i2c->base + MPC_I2C_DR);
0541         }
0542         i2c->action = MPC_I2C_ACTION_READ_BYTE;
0543         break;
0544 
0545     case MPC_I2C_ACTION_READ_BYTE:
0546         if (i2c->byte_posn || !recv_len) {
0547             /* Generate Tx ACK on next to last byte */
0548             if (i2c->byte_posn == msg->len - 2)
0549                 i2c->cntl_bits |= CCR_TXAK;
0550             /* Do not generate stop on last byte */
0551             if (i2c->byte_posn == msg->len - 1)
0552                 i2c->cntl_bits |= CCR_MTX;
0553 
0554             writeccr(i2c, i2c->cntl_bits);
0555         }
0556 
0557         byte = readb(i2c->base + MPC_I2C_DR);
0558 
0559         if (i2c->byte_posn == 0 && recv_len) {
0560             if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX) {
0561                 mpc_i2c_finish(i2c, -EPROTO);
0562                 return;
0563             }
0564             msg->len += byte;
0565             /*
0566              * For block reads, generate Tx ACK here if data length
0567              * is 1 byte (total length is 2 bytes).
0568              */
0569             if (msg->len == 2) {
0570                 i2c->cntl_bits |= CCR_TXAK;
0571                 writeccr(i2c, i2c->cntl_bits);
0572             }
0573         }
0574 
0575         dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action], byte);
0576         msg->buf[i2c->byte_posn++] = byte;
0577         break;
0578 
0579     case MPC_I2C_ACTION_WRITE:
0580         dev_dbg(i2c->dev, "%s %02x\n", action_str[i2c->action],
0581             msg->buf[i2c->byte_posn]);
0582         writeb(msg->buf[i2c->byte_posn++], i2c->base + MPC_I2C_DR);
0583         i2c->expect_rxack = 1;
0584         break;
0585 
0586     case MPC_I2C_ACTION_STOP:
0587         mpc_i2c_finish(i2c, 0);
0588         break;
0589 
0590     default:
0591         WARN(1, "Unexpected action %d\n", i2c->action);
0592         break;
0593     }
0594 
0595     if (msg && msg->len == i2c->byte_posn) {
0596         i2c->curr_msg++;
0597         i2c->byte_posn = 0;
0598 
0599         if (i2c->curr_msg == i2c->num_msgs) {
0600             i2c->action = MPC_I2C_ACTION_STOP;
0601             /*
0602              * We don't get another interrupt on read so
0603              * finish the transfer now
0604              */
0605             if (dir)
0606                 mpc_i2c_finish(i2c, 0);
0607         } else {
0608             i2c->action = MPC_I2C_ACTION_RESTART;
0609         }
0610     }
0611 }
0612 
0613 static void mpc_i2c_do_intr(struct mpc_i2c *i2c, u8 status)
0614 {
0615     spin_lock(&i2c->lock);
0616 
0617     if (!(status & CSR_MCF)) {
0618         dev_dbg(i2c->dev, "unfinished\n");
0619         mpc_i2c_finish(i2c, -EIO);
0620         goto out;
0621     }
0622 
0623     if (status & CSR_MAL) {
0624         dev_dbg(i2c->dev, "arbitration lost\n");
0625         mpc_i2c_finish(i2c, -EAGAIN);
0626         goto out;
0627     }
0628 
0629     if (i2c->expect_rxack && (status & CSR_RXAK)) {
0630         dev_dbg(i2c->dev, "no Rx ACK\n");
0631         mpc_i2c_finish(i2c, -ENXIO);
0632         goto out;
0633     }
0634     i2c->expect_rxack = 0;
0635 
0636     mpc_i2c_do_action(i2c);
0637 
0638 out:
0639     spin_unlock(&i2c->lock);
0640 }
0641 
0642 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
0643 {
0644     struct mpc_i2c *i2c = dev_id;
0645     u8 status;
0646 
0647     status = readb(i2c->base + MPC_I2C_SR);
0648     if (status & CSR_MIF) {
0649         /* Wait up to 100us for transfer to properly complete */
0650         readb_poll_timeout_atomic(i2c->base + MPC_I2C_SR, status, status & CSR_MCF, 0, 100);
0651         writeb(0, i2c->base + MPC_I2C_SR);
0652         mpc_i2c_do_intr(i2c, status);
0653         return IRQ_HANDLED;
0654     }
0655     return IRQ_NONE;
0656 }
0657 
0658 static int mpc_i2c_wait_for_completion(struct mpc_i2c *i2c)
0659 {
0660     long time_left;
0661 
0662     time_left = wait_event_timeout(i2c->waitq, !i2c->block, i2c->adap.timeout);
0663     if (!time_left)
0664         return -ETIMEDOUT;
0665     if (time_left < 0)
0666         return time_left;
0667 
0668     return 0;
0669 }
0670 
0671 static int mpc_i2c_execute_msg(struct mpc_i2c *i2c)
0672 {
0673     unsigned long orig_jiffies;
0674     unsigned long flags;
0675     int ret;
0676 
0677     spin_lock_irqsave(&i2c->lock, flags);
0678 
0679     i2c->curr_msg = 0;
0680     i2c->rc = 0;
0681     i2c->byte_posn = 0;
0682     i2c->block = 1;
0683     i2c->action = MPC_I2C_ACTION_START;
0684 
0685     i2c->cntl_bits = CCR_MEN | CCR_MIEN;
0686     writeb(0, i2c->base + MPC_I2C_SR);
0687     writeccr(i2c, i2c->cntl_bits);
0688 
0689     mpc_i2c_do_action(i2c);
0690 
0691     spin_unlock_irqrestore(&i2c->lock, flags);
0692 
0693     ret = mpc_i2c_wait_for_completion(i2c);
0694     if (ret)
0695         i2c->rc = ret;
0696 
0697     if (i2c->rc == -EIO || i2c->rc == -EAGAIN || i2c->rc == -ETIMEDOUT)
0698         i2c_recover_bus(&i2c->adap);
0699 
0700     orig_jiffies = jiffies;
0701     /* Wait until STOP is seen, allow up to 1 s */
0702     while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
0703         if (time_after(jiffies, orig_jiffies + HZ)) {
0704             u8 status = readb(i2c->base + MPC_I2C_SR);
0705 
0706             dev_dbg(i2c->dev, "timeout\n");
0707             if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
0708                 writeb(status & ~CSR_MAL,
0709                        i2c->base + MPC_I2C_SR);
0710                 i2c_recover_bus(&i2c->adap);
0711             }
0712             return -EIO;
0713         }
0714         cond_resched();
0715     }
0716 
0717     return i2c->rc;
0718 }
0719 
0720 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
0721 {
0722     int rc, ret = num;
0723     struct mpc_i2c *i2c = i2c_get_adapdata(adap);
0724     int i;
0725 
0726     dev_dbg(i2c->dev, "num = %d\n", num);
0727     for (i = 0; i < num; i++)
0728         dev_dbg(i2c->dev, "  addr = %02x, flags = %02x, len = %d, %*ph\n",
0729             msgs[i].addr, msgs[i].flags, msgs[i].len,
0730             msgs[i].flags & I2C_M_RD ? 0 : msgs[i].len,
0731             msgs[i].buf);
0732 
0733     WARN_ON(i2c->msgs != NULL);
0734     i2c->msgs = msgs;
0735     i2c->num_msgs = num;
0736 
0737     rc = mpc_i2c_execute_msg(i2c);
0738     if (rc < 0)
0739         ret = rc;
0740 
0741     i2c->num_msgs = 0;
0742     i2c->msgs = NULL;
0743 
0744     return ret;
0745 }
0746 
0747 static u32 mpc_functionality(struct i2c_adapter *adap)
0748 {
0749     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
0750       | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
0751 }
0752 
0753 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
0754 {
0755     struct mpc_i2c *i2c = i2c_get_adapdata(adap);
0756 
0757     if (i2c->has_errata_A004447)
0758         mpc_i2c_fixup_A004447(i2c);
0759     else
0760         mpc_i2c_fixup(i2c);
0761 
0762     return 0;
0763 }
0764 
0765 static const struct i2c_algorithm mpc_algo = {
0766     .master_xfer = mpc_xfer,
0767     .functionality = mpc_functionality,
0768 };
0769 
0770 static struct i2c_adapter mpc_ops = {
0771     .owner = THIS_MODULE,
0772     .algo = &mpc_algo,
0773     .timeout = HZ,
0774 };
0775 
0776 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
0777     .recover_bus = fsl_i2c_bus_recovery,
0778 };
0779 
0780 static int fsl_i2c_probe(struct platform_device *op)
0781 {
0782     const struct mpc_i2c_data *data;
0783     struct mpc_i2c *i2c;
0784     const u32 *prop;
0785     u32 clock = MPC_I2C_CLOCK_LEGACY;
0786     int result = 0;
0787     int plen;
0788     struct clk *clk;
0789     int err;
0790 
0791     i2c = devm_kzalloc(&op->dev, sizeof(*i2c), GFP_KERNEL);
0792     if (!i2c)
0793         return -ENOMEM;
0794 
0795     i2c->dev = &op->dev; /* for debug and error output */
0796 
0797     init_waitqueue_head(&i2c->waitq);
0798     spin_lock_init(&i2c->lock);
0799 
0800     i2c->base = devm_platform_ioremap_resource(op, 0);
0801     if (IS_ERR(i2c->base))
0802         return PTR_ERR(i2c->base);
0803 
0804     i2c->irq = platform_get_irq(op, 0);
0805     if (i2c->irq < 0)
0806         return i2c->irq;
0807 
0808     result = devm_request_irq(&op->dev, i2c->irq, mpc_i2c_isr,
0809             IRQF_SHARED, "i2c-mpc", i2c);
0810     if (result < 0) {
0811         dev_err(i2c->dev, "failed to attach interrupt\n");
0812         return result;
0813     }
0814 
0815     /*
0816      * enable clock for the I2C peripheral (non fatal),
0817      * keep a reference upon successful allocation
0818      */
0819     clk = devm_clk_get_optional(&op->dev, NULL);
0820     if (IS_ERR(clk))
0821         return PTR_ERR(clk);
0822 
0823     err = clk_prepare_enable(clk);
0824     if (err) {
0825         dev_err(&op->dev, "failed to enable clock\n");
0826         return err;
0827     }
0828 
0829     i2c->clk_per = clk;
0830 
0831     if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
0832         clock = MPC_I2C_CLOCK_PRESERVE;
0833     } else {
0834         prop = of_get_property(op->dev.of_node, "clock-frequency",
0835                     &plen);
0836         if (prop && plen == sizeof(u32))
0837             clock = *prop;
0838     }
0839 
0840     data = device_get_match_data(&op->dev);
0841     if (data) {
0842         data->setup(op->dev.of_node, i2c, clock);
0843     } else {
0844         /* Backwards compatibility */
0845         if (of_get_property(op->dev.of_node, "dfsrr", NULL))
0846             mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
0847     }
0848 
0849     prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
0850     if (prop && plen == sizeof(u32)) {
0851         mpc_ops.timeout = *prop * HZ / 1000000;
0852         if (mpc_ops.timeout < 5)
0853             mpc_ops.timeout = 5;
0854     }
0855     dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
0856 
0857     if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
0858         i2c->has_errata_A004447 = true;
0859 
0860     i2c->adap = mpc_ops;
0861     scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
0862           "MPC adapter (%s)", of_node_full_name(op->dev.of_node));
0863     i2c->adap.dev.parent = &op->dev;
0864     i2c->adap.nr = op->id;
0865     i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
0866     i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
0867     platform_set_drvdata(op, i2c);
0868     i2c_set_adapdata(&i2c->adap, i2c);
0869 
0870     result = i2c_add_numbered_adapter(&i2c->adap);
0871     if (result)
0872         goto fail_add;
0873 
0874     return 0;
0875 
0876  fail_add:
0877     clk_disable_unprepare(i2c->clk_per);
0878 
0879     return result;
0880 };
0881 
0882 static int fsl_i2c_remove(struct platform_device *op)
0883 {
0884     struct mpc_i2c *i2c = platform_get_drvdata(op);
0885 
0886     i2c_del_adapter(&i2c->adap);
0887 
0888     clk_disable_unprepare(i2c->clk_per);
0889 
0890     return 0;
0891 };
0892 
0893 static int __maybe_unused mpc_i2c_suspend(struct device *dev)
0894 {
0895     struct mpc_i2c *i2c = dev_get_drvdata(dev);
0896 
0897     i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
0898     i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
0899 
0900     return 0;
0901 }
0902 
0903 static int __maybe_unused mpc_i2c_resume(struct device *dev)
0904 {
0905     struct mpc_i2c *i2c = dev_get_drvdata(dev);
0906 
0907     writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
0908     writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
0909 
0910     return 0;
0911 }
0912 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
0913 
0914 static const struct mpc_i2c_data mpc_i2c_data_512x = {
0915     .setup = mpc_i2c_setup_512x,
0916 };
0917 
0918 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
0919     .setup = mpc_i2c_setup_52xx,
0920 };
0921 
0922 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
0923     .setup = mpc_i2c_setup_8xxx,
0924 };
0925 
0926 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
0927     .setup = mpc_i2c_setup_8xxx,
0928 };
0929 
0930 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
0931     .setup = mpc_i2c_setup_8xxx,
0932 };
0933 
0934 static const struct of_device_id mpc_i2c_of_match[] = {
0935     {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
0936     {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
0937     {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
0938     {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
0939     {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
0940     {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
0941     {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
0942     /* Backward compatibility */
0943     {.compatible = "fsl-i2c", },
0944     {},
0945 };
0946 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
0947 
0948 /* Structure for a device driver */
0949 static struct platform_driver mpc_i2c_driver = {
0950     .probe      = fsl_i2c_probe,
0951     .remove     = fsl_i2c_remove,
0952     .driver = {
0953         .name = DRV_NAME,
0954         .of_match_table = mpc_i2c_of_match,
0955         .pm = &mpc_i2c_pm_ops,
0956     },
0957 };
0958 
0959 module_platform_driver(mpc_i2c_driver);
0960 
0961 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
0962 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
0963            "MPC824x/83xx/85xx/86xx/512x/52xx processors");
0964 MODULE_LICENSE("GPL");
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