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0001 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
0002 /*
0003  * Mellanox i2c driver
0004  *
0005  * Copyright (C) 2016-2020 Mellanox Technologies
0006  */
0007 
0008 #include <linux/delay.h>
0009 #include <linux/i2c.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/platform_data/mlxreg.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regmap.h>
0017 
0018 /* General defines */
0019 #define MLXPLAT_CPLD_LPC_I2C_BASE_ADDR  0x2000
0020 #define MLXCPLD_I2C_DEVICE_NAME     "i2c_mlxcpld"
0021 #define MLXCPLD_I2C_VALID_FLAG      (I2C_M_RECV_LEN | I2C_M_RD)
0022 #define MLXCPLD_I2C_BUS_NUM     1
0023 #define MLXCPLD_I2C_DATA_REG_SZ     36
0024 #define MLXCPLD_I2C_DATA_SZ_BIT     BIT(5)
0025 #define MLXCPLD_I2C_DATA_SZ_MASK    GENMASK(6, 5)
0026 #define MLXCPLD_I2C_SMBUS_BLK_BIT   BIT(7)
0027 #define MLXCPLD_I2C_MAX_ADDR_LEN    4
0028 #define MLXCPLD_I2C_RETR_NUM        2
0029 #define MLXCPLD_I2C_XFER_TO     500000 /* usec */
0030 #define MLXCPLD_I2C_POLL_TIME       200   /* usec */
0031 
0032 /* LPC I2C registers */
0033 #define MLXCPLD_LPCI2C_CPBLTY_REG   0x0
0034 #define MLXCPLD_LPCI2C_CTRL_REG     0x1
0035 #define MLXCPLD_LPCI2C_HALF_CYC_REG 0x4
0036 #define MLXCPLD_LPCI2C_I2C_HOLD_REG 0x5
0037 #define MLXCPLD_LPCI2C_CMD_REG      0x6
0038 #define MLXCPLD_LPCI2C_NUM_DAT_REG  0x7
0039 #define MLXCPLD_LPCI2C_NUM_ADDR_REG 0x8
0040 #define MLXCPLD_LPCI2C_STATUS_REG   0x9
0041 #define MLXCPLD_LPCI2C_DATA_REG     0xa
0042 
0043 /* LPC I2C masks and parametres */
0044 #define MLXCPLD_LPCI2C_RST_SEL_MASK 0x1
0045 #define MLXCPLD_LPCI2C_TRANS_END    0x1
0046 #define MLXCPLD_LPCI2C_STATUS_NACK  0x10
0047 #define MLXCPLD_LPCI2C_NO_IND       0
0048 #define MLXCPLD_LPCI2C_ACK_IND      1
0049 #define MLXCPLD_LPCI2C_NACK_IND     2
0050 
0051 #define MLXCPLD_I2C_FREQ_1000KHZ_SET    0x04
0052 #define MLXCPLD_I2C_FREQ_400KHZ_SET 0x0e
0053 #define MLXCPLD_I2C_FREQ_100KHZ_SET 0x42
0054 
0055 enum mlxcpld_i2c_frequency {
0056     MLXCPLD_I2C_FREQ_1000KHZ = 1,
0057     MLXCPLD_I2C_FREQ_400KHZ = 2,
0058     MLXCPLD_I2C_FREQ_100KHZ = 3,
0059 };
0060 
0061 struct  mlxcpld_i2c_curr_xfer {
0062     u8 cmd;
0063     u8 addr_width;
0064     u8 data_len;
0065     u8 msg_num;
0066     struct i2c_msg *msg;
0067 };
0068 
0069 struct mlxcpld_i2c_priv {
0070     struct i2c_adapter adap;
0071     u32 base_addr;
0072     struct mutex lock;
0073     struct  mlxcpld_i2c_curr_xfer xfer;
0074     struct device *dev;
0075     bool smbus_block;
0076     int polling_time;
0077 };
0078 
0079 static void mlxcpld_i2c_lpc_write_buf(u8 *data, u8 len, u32 addr)
0080 {
0081     int i;
0082 
0083     for (i = 0; i < len - len % 4; i += 4)
0084         outl(*(u32 *)(data + i), addr + i);
0085     for (; i < len; ++i)
0086         outb(*(data + i), addr + i);
0087 }
0088 
0089 static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr)
0090 {
0091     int i;
0092 
0093     for (i = 0; i < len - len % 4; i += 4)
0094         *(u32 *)(data + i) = inl(addr + i);
0095     for (; i < len; ++i)
0096         *(data + i) = inb(addr + i);
0097 }
0098 
0099 static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
0100                   u8 *data, u8 datalen)
0101 {
0102     u32 addr = priv->base_addr + offs;
0103 
0104     switch (datalen) {
0105     case 1:
0106         *(data) = inb(addr);
0107         break;
0108     case 2:
0109         *((u16 *)data) = inw(addr);
0110         break;
0111     case 3:
0112         *((u16 *)data) = inw(addr);
0113         *(data + 2) = inb(addr + 2);
0114         break;
0115     case 4:
0116         *((u32 *)data) = inl(addr);
0117         break;
0118     default:
0119         mlxcpld_i2c_lpc_read_buf(data, datalen, addr);
0120         break;
0121     }
0122 }
0123 
0124 static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8 offs,
0125                    u8 *data, u8 datalen)
0126 {
0127     u32 addr = priv->base_addr + offs;
0128 
0129     switch (datalen) {
0130     case 1:
0131         outb(*(data), addr);
0132         break;
0133     case 2:
0134         outw(*((u16 *)data), addr);
0135         break;
0136     case 3:
0137         outw(*((u16 *)data), addr);
0138         outb(*(data + 2), addr + 2);
0139         break;
0140     case 4:
0141         outl(*((u32 *)data), addr);
0142         break;
0143     default:
0144         mlxcpld_i2c_lpc_write_buf(data, datalen, addr);
0145         break;
0146     }
0147 }
0148 
0149 /*
0150  * Check validity of received i2c messages parameters.
0151  * Returns 0 if OK, other - in case of invalid parameters.
0152  */
0153 static int mlxcpld_i2c_check_msg_params(struct mlxcpld_i2c_priv *priv,
0154                     struct i2c_msg *msgs, int num)
0155 {
0156     int i;
0157 
0158     if (!num) {
0159         dev_err(priv->dev, "Incorrect 0 num of messages\n");
0160         return -EINVAL;
0161     }
0162 
0163     if (unlikely(msgs[0].addr > 0x7f)) {
0164         dev_err(priv->dev, "Invalid address 0x%03x\n",
0165             msgs[0].addr);
0166         return -EINVAL;
0167     }
0168 
0169     for (i = 0; i < num; ++i) {
0170         if (unlikely(!msgs[i].buf)) {
0171             dev_err(priv->dev, "Invalid buf in msg[%d]\n",
0172                 i);
0173             return -EINVAL;
0174         }
0175         if (unlikely(msgs[0].addr != msgs[i].addr)) {
0176             dev_err(priv->dev, "Invalid addr in msg[%d]\n",
0177                 i);
0178             return -EINVAL;
0179         }
0180     }
0181 
0182     return 0;
0183 }
0184 
0185 /*
0186  * Check if transfer is completed and status of operation.
0187  * Returns 0 - transfer completed (both ACK or NACK),
0188  * negative - transfer isn't finished.
0189  */
0190 static int mlxcpld_i2c_check_status(struct mlxcpld_i2c_priv *priv, int *status)
0191 {
0192     u8 val;
0193 
0194     mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
0195 
0196     if (val & MLXCPLD_LPCI2C_TRANS_END) {
0197         if (val & MLXCPLD_LPCI2C_STATUS_NACK)
0198             /*
0199              * The slave is unable to accept the data. No such
0200              * slave, command not understood, or unable to accept
0201              * any more data.
0202              */
0203             *status = MLXCPLD_LPCI2C_NACK_IND;
0204         else
0205             *status = MLXCPLD_LPCI2C_ACK_IND;
0206         return 0;
0207     }
0208     *status = MLXCPLD_LPCI2C_NO_IND;
0209 
0210     return -EIO;
0211 }
0212 
0213 static void mlxcpld_i2c_set_transf_data(struct mlxcpld_i2c_priv *priv,
0214                     struct i2c_msg *msgs, int num,
0215                     u8 comm_len)
0216 {
0217     priv->xfer.msg = msgs;
0218     priv->xfer.msg_num = num;
0219 
0220     /*
0221      * All upper layers currently are never use transfer with more than
0222      * 2 messages. Actually, it's also not so relevant in Mellanox systems
0223      * because of HW limitation. Max size of transfer is not more than 32
0224      * or 68 bytes in the current x86 LPCI2C bridge.
0225      */
0226     priv->xfer.cmd = msgs[num - 1].flags & I2C_M_RD;
0227 
0228     if (priv->xfer.cmd == I2C_M_RD && comm_len != msgs[0].len) {
0229         priv->xfer.addr_width = msgs[0].len;
0230         priv->xfer.data_len = comm_len - priv->xfer.addr_width;
0231     } else {
0232         priv->xfer.addr_width = 0;
0233         priv->xfer.data_len = comm_len;
0234     }
0235 }
0236 
0237 /* Reset CPLD LPCI2C block */
0238 static void mlxcpld_i2c_reset(struct mlxcpld_i2c_priv *priv)
0239 {
0240     u8 val;
0241 
0242     mutex_lock(&priv->lock);
0243 
0244     mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
0245     val &= ~MLXCPLD_LPCI2C_RST_SEL_MASK;
0246     mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CTRL_REG, &val, 1);
0247 
0248     mutex_unlock(&priv->lock);
0249 }
0250 
0251 /* Make sure the CPLD is ready to start transmitting. */
0252 static int mlxcpld_i2c_check_busy(struct mlxcpld_i2c_priv *priv)
0253 {
0254     u8 val;
0255 
0256     mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_STATUS_REG, &val, 1);
0257 
0258     if (val & MLXCPLD_LPCI2C_TRANS_END)
0259         return 0;
0260 
0261     return -EIO;
0262 }
0263 
0264 static int mlxcpld_i2c_wait_for_free(struct mlxcpld_i2c_priv *priv)
0265 {
0266     int timeout = 0;
0267 
0268     do {
0269         if (!mlxcpld_i2c_check_busy(priv))
0270             break;
0271         usleep_range(priv->polling_time / 2, priv->polling_time);
0272         timeout += priv->polling_time;
0273     } while (timeout <= MLXCPLD_I2C_XFER_TO);
0274 
0275     if (timeout > MLXCPLD_I2C_XFER_TO)
0276         return -ETIMEDOUT;
0277 
0278     return 0;
0279 }
0280 
0281 /*
0282  * Wait for master transfer to complete.
0283  * It puts current process to sleep until we get interrupt or timeout expires.
0284  * Returns the number of transferred or read bytes or error (<0).
0285  */
0286 static int mlxcpld_i2c_wait_for_tc(struct mlxcpld_i2c_priv *priv)
0287 {
0288     int status, i, timeout = 0;
0289     u8 datalen, val;
0290 
0291     do {
0292         usleep_range(priv->polling_time / 2, priv->polling_time);
0293         if (!mlxcpld_i2c_check_status(priv, &status))
0294             break;
0295         timeout += priv->polling_time;
0296     } while (status == 0 && timeout < MLXCPLD_I2C_XFER_TO);
0297 
0298     switch (status) {
0299     case MLXCPLD_LPCI2C_NO_IND:
0300         return -ETIMEDOUT;
0301 
0302     case MLXCPLD_LPCI2C_ACK_IND:
0303         if (priv->xfer.cmd != I2C_M_RD)
0304             return (priv->xfer.addr_width + priv->xfer.data_len);
0305 
0306         if (priv->xfer.msg_num == 1)
0307             i = 0;
0308         else
0309             i = 1;
0310 
0311         if (!priv->xfer.msg[i].buf)
0312             return -EINVAL;
0313 
0314         /*
0315          * Actual read data len will be always the same as
0316          * requested len. 0xff (line pull-up) will be returned
0317          * if slave has no data to return. Thus don't read
0318          * MLXCPLD_LPCI2C_NUM_DAT_REG reg from CPLD.  Only in case of
0319          * SMBus block read transaction data len can be different,
0320          * check this case.
0321          */
0322         mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val,
0323                       1);
0324         if (priv->smbus_block && (val & MLXCPLD_I2C_SMBUS_BLK_BIT)) {
0325             mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
0326                           &datalen, 1);
0327             if (unlikely(datalen > I2C_SMBUS_BLOCK_MAX)) {
0328                 dev_err(priv->dev, "Incorrect smbus block read message len\n");
0329                 return -EPROTO;
0330             }
0331         } else {
0332             datalen = priv->xfer.data_len;
0333         }
0334 
0335         mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_DATA_REG,
0336                       priv->xfer.msg[i].buf, datalen);
0337 
0338         return datalen;
0339 
0340     case MLXCPLD_LPCI2C_NACK_IND:
0341         return -ENXIO;
0342 
0343     default:
0344         return -EINVAL;
0345     }
0346 }
0347 
0348 static void mlxcpld_i2c_xfer_msg(struct mlxcpld_i2c_priv *priv)
0349 {
0350     int i, len = 0;
0351     u8 cmd, val;
0352 
0353     mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_DAT_REG,
0354                    &priv->xfer.data_len, 1);
0355 
0356     val = priv->xfer.addr_width;
0357     /* Notify HW about SMBus block read transaction */
0358     if (priv->smbus_block && priv->xfer.msg_num >= 2 &&
0359         priv->xfer.msg[1].len == 1 &&
0360         (priv->xfer.msg[1].flags & I2C_M_RECV_LEN) &&
0361         (priv->xfer.msg[1].flags & I2C_M_RD))
0362         val |= MLXCPLD_I2C_SMBUS_BLK_BIT;
0363 
0364     mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_NUM_ADDR_REG, &val, 1);
0365 
0366     for (i = 0; i < priv->xfer.msg_num; i++) {
0367         if ((priv->xfer.msg[i].flags & I2C_M_RD) != I2C_M_RD) {
0368             /* Don't write to CPLD buffer in read transaction */
0369             mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_DATA_REG +
0370                            len, priv->xfer.msg[i].buf,
0371                            priv->xfer.msg[i].len);
0372             len += priv->xfer.msg[i].len;
0373         }
0374     }
0375 
0376     /*
0377      * Set target slave address with command for master transfer.
0378      * It should be latest executed function before CPLD transaction.
0379      */
0380     cmd = (priv->xfer.msg[0].addr << 1) | priv->xfer.cmd;
0381     mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_CMD_REG, &cmd, 1);
0382 }
0383 
0384 /*
0385  * Generic lpc-i2c transfer.
0386  * Returns the number of processed messages or error (<0).
0387  */
0388 static int mlxcpld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
0389                 int num)
0390 {
0391     struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
0392     u8 comm_len = 0;
0393     int i, err;
0394 
0395     err = mlxcpld_i2c_check_msg_params(priv, msgs, num);
0396     if (err) {
0397         dev_err(priv->dev, "Incorrect message\n");
0398         return err;
0399     }
0400 
0401     for (i = 0; i < num; ++i)
0402         comm_len += msgs[i].len;
0403 
0404     /* Check bus state */
0405     if (mlxcpld_i2c_wait_for_free(priv)) {
0406         dev_err(priv->dev, "LPCI2C bridge is busy\n");
0407 
0408         /*
0409          * Usually it means something serious has happened.
0410          * We can not have unfinished previous transfer
0411          * so it doesn't make any sense to try to stop it.
0412          * Probably we were not able to recover from the
0413          * previous error.
0414          * The only reasonable thing - is soft reset.
0415          */
0416         mlxcpld_i2c_reset(priv);
0417         if (mlxcpld_i2c_check_busy(priv)) {
0418             dev_err(priv->dev, "LPCI2C bridge is busy after reset\n");
0419             return -EIO;
0420         }
0421     }
0422 
0423     mlxcpld_i2c_set_transf_data(priv, msgs, num, comm_len);
0424 
0425     mutex_lock(&priv->lock);
0426 
0427     /* Do real transfer. Can't fail */
0428     mlxcpld_i2c_xfer_msg(priv);
0429 
0430     /* Wait for transaction complete */
0431     err = mlxcpld_i2c_wait_for_tc(priv);
0432 
0433     mutex_unlock(&priv->lock);
0434 
0435     return err < 0 ? err : num;
0436 }
0437 
0438 static u32 mlxcpld_i2c_func(struct i2c_adapter *adap)
0439 {
0440     struct mlxcpld_i2c_priv *priv = i2c_get_adapdata(adap);
0441 
0442     if (priv->smbus_block)
0443         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
0444             I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_BLOCK_DATA;
0445     else
0446         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
0447             I2C_FUNC_SMBUS_I2C_BLOCK;
0448 }
0449 
0450 static const struct i2c_algorithm mlxcpld_i2c_algo = {
0451     .master_xfer    = mlxcpld_i2c_xfer,
0452     .functionality  = mlxcpld_i2c_func
0453 };
0454 
0455 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks = {
0456     .flags = I2C_AQ_COMB_WRITE_THEN_READ,
0457     .max_read_len = MLXCPLD_I2C_DATA_REG_SZ - MLXCPLD_I2C_MAX_ADDR_LEN,
0458     .max_write_len = MLXCPLD_I2C_DATA_REG_SZ,
0459     .max_comb_1st_msg_len = 4,
0460 };
0461 
0462 static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = {
0463     .flags = I2C_AQ_COMB_WRITE_THEN_READ,
0464     .max_read_len = MLXCPLD_I2C_DATA_REG_SZ * 2 - MLXCPLD_I2C_MAX_ADDR_LEN,
0465     .max_write_len = MLXCPLD_I2C_DATA_REG_SZ * 2,
0466     .max_comb_1st_msg_len = 4,
0467 };
0468 
0469 static struct i2c_adapter mlxcpld_i2c_adapter = {
0470     .owner          = THIS_MODULE,
0471     .name           = "i2c-mlxcpld",
0472     .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
0473     .algo           = &mlxcpld_i2c_algo,
0474     .quirks     = &mlxcpld_i2c_quirks,
0475     .retries    = MLXCPLD_I2C_RETR_NUM,
0476     .nr     = MLXCPLD_I2C_BUS_NUM,
0477 };
0478 
0479 static int
0480 mlxcpld_i2c_set_frequency(struct mlxcpld_i2c_priv *priv,
0481               struct mlxreg_core_hotplug_platform_data *pdata)
0482 {
0483     struct mlxreg_core_item *item = pdata->items;
0484     struct mlxreg_core_data *data;
0485     u32 regval;
0486     u8 freq;
0487     int err;
0488 
0489     if (!item)
0490         return 0;
0491 
0492     /* Read frequency setting. */
0493     data = item->data;
0494     err = regmap_read(pdata->regmap, data->reg, &regval);
0495     if (err)
0496         return err;
0497 
0498     /* Set frequency only if it is not 100KHz, which is default. */
0499     switch ((regval & data->mask) >> data->bit) {
0500     case MLXCPLD_I2C_FREQ_1000KHZ:
0501         freq = MLXCPLD_I2C_FREQ_1000KHZ_SET;
0502         priv->polling_time /= 4;
0503         break;
0504     case MLXCPLD_I2C_FREQ_400KHZ:
0505         freq = MLXCPLD_I2C_FREQ_400KHZ_SET;
0506         priv->polling_time /= 4;
0507         break;
0508     default:
0509         return 0;
0510     }
0511 
0512     mlxcpld_i2c_write_comm(priv, MLXCPLD_LPCI2C_HALF_CYC_REG, &freq, 1);
0513 
0514     return 0;
0515 }
0516 
0517 static int mlxcpld_i2c_probe(struct platform_device *pdev)
0518 {
0519     struct mlxreg_core_hotplug_platform_data *pdata;
0520     struct mlxcpld_i2c_priv *priv;
0521     int err;
0522     u8 val;
0523 
0524     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0525     if (!priv)
0526         return -ENOMEM;
0527 
0528     mutex_init(&priv->lock);
0529     platform_set_drvdata(pdev, priv);
0530 
0531     priv->dev = &pdev->dev;
0532     priv->base_addr = MLXPLAT_CPLD_LPC_I2C_BASE_ADDR;
0533     priv->polling_time = MLXCPLD_I2C_POLL_TIME;
0534 
0535     /* Set I2C bus frequency if platform data provides this info. */
0536     pdata = dev_get_platdata(&pdev->dev);
0537     if (pdata) {
0538         err = mlxcpld_i2c_set_frequency(priv, pdata);
0539         if (err)
0540             goto mlxcpld_i2_probe_failed;
0541     }
0542 
0543     /* Register with i2c layer */
0544     mlxcpld_i2c_adapter.timeout = usecs_to_jiffies(MLXCPLD_I2C_XFER_TO);
0545     /* Read capability register */
0546     mlxcpld_i2c_read_comm(priv, MLXCPLD_LPCI2C_CPBLTY_REG, &val, 1);
0547     /* Check support for extended transaction length */
0548     if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT)
0549         mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext;
0550     /* Check support for smbus block transaction */
0551     if (val & MLXCPLD_I2C_SMBUS_BLK_BIT)
0552         priv->smbus_block = true;
0553     if (pdev->id >= -1)
0554         mlxcpld_i2c_adapter.nr = pdev->id;
0555     priv->adap = mlxcpld_i2c_adapter;
0556     priv->adap.dev.parent = &pdev->dev;
0557     i2c_set_adapdata(&priv->adap, priv);
0558 
0559     err = i2c_add_numbered_adapter(&priv->adap);
0560     if (err)
0561         goto mlxcpld_i2_probe_failed;
0562 
0563     /* Notify caller when adapter is added. */
0564     if (pdata && pdata->completion_notify)
0565         pdata->completion_notify(pdata->handle, mlxcpld_i2c_adapter.nr);
0566 
0567     return 0;
0568 
0569 mlxcpld_i2_probe_failed:
0570     mutex_destroy(&priv->lock);
0571     return err;
0572 }
0573 
0574 static int mlxcpld_i2c_remove(struct platform_device *pdev)
0575 {
0576     struct mlxcpld_i2c_priv *priv = platform_get_drvdata(pdev);
0577 
0578     i2c_del_adapter(&priv->adap);
0579     mutex_destroy(&priv->lock);
0580 
0581     return 0;
0582 }
0583 
0584 static struct platform_driver mlxcpld_i2c_driver = {
0585     .probe      = mlxcpld_i2c_probe,
0586     .remove     = mlxcpld_i2c_remove,
0587     .driver = {
0588         .name = MLXCPLD_I2C_DEVICE_NAME,
0589     },
0590 };
0591 
0592 module_platform_driver(mlxcpld_i2c_driver);
0593 
0594 MODULE_AUTHOR("Michael Shych <michaels@mellanox.com>");
0595 MODULE_DESCRIPTION("Mellanox I2C-CPLD controller driver");
0596 MODULE_LICENSE("Dual BSD/GPL");
0597 MODULE_ALIAS("platform:i2c-mlxcpld");
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