i2c/busses/i2c-microchip-corei2c.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Microchip CoreI2C I2C controller driver
0004  *
0005  * Copyright (c) 2018-2022 Microchip Corporation. All rights reserved.
0006  *
0007  * Author: Daire McNamara <daire.mcnamara@microchip.com>
0008  * Author: Conor Dooley <conor.dooley@microchip.com>
0009  */
0010 #include <linux/clk.h>
0011 #include <linux/clkdev.h>
0012 #include <linux/err.h>
0013 #include <linux/i2c.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/io.h>
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/platform_device.h>
0019
0020 #define CORE_I2C_CTRL   (0x00)
0021 #define  CTRL_CR0   BIT(0)
0022 #define  CTRL_CR1   BIT(1)
0023 #define  CTRL_AA    BIT(2)
0024 #define  CTRL_SI    BIT(3)
0025 #define  CTRL_STO   BIT(4)
0026 #define  CTRL_STA   BIT(5)
0027 #define  CTRL_ENS1  BIT(6)
0028 #define  CTRL_CR2   BIT(7)
0029
0030 #define STATUS_BUS_ERROR            (0x00)
0031 #define STATUS_M_START_SENT         (0x08)
0032 #define STATUS_M_REPEATED_START_SENT        (0x10)
0033 #define STATUS_M_SLAW_ACK           (0x18)
0034 #define STATUS_M_SLAW_NACK          (0x20)
0035 #define STATUS_M_TX_DATA_ACK            (0x28)
0036 #define STATUS_M_TX_DATA_NACK           (0x30)
0037 #define STATUS_M_ARB_LOST           (0x38)
0038 #define STATUS_M_SLAR_ACK           (0x40)
0039 #define STATUS_M_SLAR_NACK          (0x48)
0040 #define STATUS_M_RX_DATA_ACKED          (0x50)
0041 #define STATUS_M_RX_DATA_NACKED         (0x58)
0042 #define STATUS_S_SLAW_ACKED         (0x60)
0043 #define STATUS_S_ARB_LOST_SLAW_ACKED        (0x68)
0044 #define STATUS_S_GENERAL_CALL_ACKED     (0x70)
0045 #define STATUS_S_ARB_LOST_GENERAL_CALL_ACKED    (0x78)
0046 #define STATUS_S_RX_DATA_ACKED          (0x80)
0047 #define STATUS_S_RX_DATA_NACKED         (0x88)
0048 #define STATUS_S_GENERAL_CALL_RX_DATA_ACKED (0x90)
0049 #define STATUS_S_GENERAL_CALL_RX_DATA_NACKED    (0x98)
0050 #define STATUS_S_RX_STOP            (0xA0)
0051 #define STATUS_S_SLAR_ACKED         (0xA8)
0052 #define STATUS_S_ARB_LOST_SLAR_ACKED        (0xB0)
0053 #define STATUS_S_TX_DATA_ACK            (0xB8)
0054 #define STATUS_S_TX_DATA_NACK           (0xC0)
0055 #define STATUS_LAST_DATA_ACK            (0xC8)
0056 #define STATUS_M_SMB_MASTER_RESET       (0xD0)
0057 #define STATUS_S_SCL_LOW_TIMEOUT        (0xD8) /* 25 ms */
0058 #define STATUS_NO_STATE_INFO            (0xF8)
0059
0060 #define CORE_I2C_STATUS     (0x04)
0061 #define CORE_I2C_DATA       (0x08)
0062 #define WRITE_BIT       (0x0)
0063 #define READ_BIT        (0x1)
0064 #define SLAVE_ADDR_SHIFT    (1)
0065 #define CORE_I2C_SLAVE0_ADDR    (0x0c)
0066 #define GENERAL_CALL_BIT    (0x0)
0067 #define CORE_I2C_SMBUS      (0x10)
0068 #define SMBALERT_INT_ENB    (0x0)
0069 #define SMBSUS_INT_ENB      (0x1)
0070 #define SMBUS_ENB       (0x2)
0071 #define SMBALERT_NI_STATUS  (0x3)
0072 #define SMBALERT_NO_CTRL    (0x4)
0073 #define SMBSUS_NI_STATUS    (0x5)
0074 #define SMBSUS_NO_CTRL      (0x6)
0075 #define SMBUS_RESET     (0x7)
0076 #define CORE_I2C_FREQ       (0x14)
0077 #define CORE_I2C_GLITCHREG  (0x18)
0078 #define CORE_I2C_SLAVE1_ADDR    (0x1c)
0079
0080 #define PCLK_DIV_960    (CTRL_CR2)
0081 #define PCLK_DIV_256    (0)
0082 #define PCLK_DIV_224    (CTRL_CR0)
0083 #define PCLK_DIV_192    (CTRL_CR1)
0084 #define PCLK_DIV_160    (CTRL_CR0 | CTRL_CR1)
0085 #define PCLK_DIV_120    (CTRL_CR0 | CTRL_CR2)
0086 #define PCLK_DIV_60 (CTRL_CR1 | CTRL_CR2)
0087 #define BCLK_DIV_8  (CTRL_CR0 | CTRL_CR1 | CTRL_CR2)
0088 #define CLK_MASK    (CTRL_CR0 | CTRL_CR1 | CTRL_CR2)
0089
0090 /**
0091  * struct mchp_corei2c_dev - Microchip CoreI2C device private data
0092  *
0093  * @base:       pointer to register struct
0094  * @dev:        device reference
0095  * @i2c_clk:        clock reference for i2c input clock
0096  * @buf:        pointer to msg buffer for easier use
0097  * @msg_complete:   xfer completion object
0098  * @adapter:        core i2c abstraction
0099  * @msg_err:        error code for completed message
0100  * @bus_clk_rate:   current i2c bus clock rate
0101  * @isr_status:     cached copy of local ISR status
0102  * @msg_len:        number of bytes transferred in msg
0103  * @addr:       address of the current slave
0104  */
0105 struct mchp_corei2c_dev {
0106     void __iomem *base;
0107     struct device *dev;
0108     struct clk *i2c_clk;
0109     u8 *buf;
0110     struct completion msg_complete;
0111     struct i2c_adapter adapter;
0112     int msg_err;
0113     u32 bus_clk_rate;
0114     u32 isr_status;
0115     u16 msg_len;
0116     u8 addr;
0117 };
0118
0119 static void mchp_corei2c_core_disable(struct mchp_corei2c_dev *idev)
0120 {
0121     u8 ctrl = readb(idev->base + CORE_I2C_CTRL);
0122
0123     ctrl &= ~CTRL_ENS1;
0124     writeb(ctrl, idev->base + CORE_I2C_CTRL);
0125 }
0126
0127 static void mchp_corei2c_core_enable(struct mchp_corei2c_dev *idev)
0128 {
0129     u8 ctrl = readb(idev->base + CORE_I2C_CTRL);
0130
0131     ctrl |= CTRL_ENS1;
0132     writeb(ctrl, idev->base + CORE_I2C_CTRL);
0133 }
0134
0135 static void mchp_corei2c_reset(struct mchp_corei2c_dev *idev)
0136 {
0137     mchp_corei2c_core_disable(idev);
0138     mchp_corei2c_core_enable(idev);
0139 }
0140
0141 static inline void mchp_corei2c_stop(struct mchp_corei2c_dev *idev)
0142 {
0143     u8 ctrl = readb(idev->base + CORE_I2C_CTRL);
0144
0145     ctrl |= CTRL_STO;
0146     writeb(ctrl, idev->base + CORE_I2C_CTRL);
0147 }
0148
0149 static inline int mchp_corei2c_set_divisor(u32 rate,
0150                        struct mchp_corei2c_dev *idev)
0151 {
0152     u8 clkval, ctrl;
0153
0154     if (rate >= 960)
0155         clkval = PCLK_DIV_960;
0156     else if (rate >= 256)
0157         clkval = PCLK_DIV_256;
0158     else if (rate >= 224)
0159         clkval = PCLK_DIV_224;
0160     else if (rate >= 192)
0161         clkval = PCLK_DIV_192;
0162     else if (rate >= 160)
0163         clkval = PCLK_DIV_160;
0164     else if (rate >= 120)
0165         clkval = PCLK_DIV_120;
0166     else if (rate >= 60)
0167         clkval = PCLK_DIV_60;
0168     else if (rate >= 8)
0169         clkval = BCLK_DIV_8;
0170     else
0171         return -EINVAL;
0172
0173     ctrl = readb(idev->base + CORE_I2C_CTRL);
0174     ctrl &= ~CLK_MASK;
0175     ctrl |= clkval;
0176     writeb(ctrl, idev->base + CORE_I2C_CTRL);
0177
0178     ctrl = readb(idev->base + CORE_I2C_CTRL);
0179     if ((ctrl & CLK_MASK) != clkval)
0180         return -EIO;
0181
0182     return 0;
0183 }
0184
0185 static int mchp_corei2c_init(struct mchp_corei2c_dev *idev)
0186 {
0187     u32 clk_rate = clk_get_rate(idev->i2c_clk);
0188     u32 divisor = clk_rate / idev->bus_clk_rate;
0189     int ret;
0190
0191     ret = mchp_corei2c_set_divisor(divisor, idev);
0192     if (ret)
0193         return ret;
0194
0195     mchp_corei2c_reset(idev);
0196
0197     return 0;
0198 }
0199
0200 static void mchp_corei2c_empty_rx(struct mchp_corei2c_dev *idev)
0201 {
0202     u8 ctrl;
0203
0204     if (idev->msg_len > 0) {
0205         *idev->buf++ = readb(idev->base + CORE_I2C_DATA);
0206         idev->msg_len--;
0207     }
0208
0209     if (idev->msg_len <= 1) {
0210         ctrl = readb(idev->base + CORE_I2C_CTRL);
0211         ctrl &= ~CTRL_AA;
0212         writeb(ctrl, idev->base + CORE_I2C_CTRL);
0213     }
0214 }
0215
0216 static int mchp_corei2c_fill_tx(struct mchp_corei2c_dev *idev)
0217 {
0218     if (idev->msg_len > 0)
0219         writeb(*idev->buf++, idev->base + CORE_I2C_DATA);
0220     idev->msg_len--;
0221
0222     return 0;
0223 }
0224
0225 static irqreturn_t mchp_corei2c_handle_isr(struct mchp_corei2c_dev *idev)
0226 {
0227     u32 status = idev->isr_status;
0228     u8 ctrl;
0229     bool last_byte = false, finished = false;
0230
0231     if (!idev->buf)
0232         return IRQ_NONE;
0233
0234     switch (status) {
0235     case STATUS_M_START_SENT:
0236     case STATUS_M_REPEATED_START_SENT:
0237         ctrl = readb(idev->base + CORE_I2C_CTRL);
0238         ctrl &= ~CTRL_STA;
0239         writeb(idev->addr, idev->base + CORE_I2C_DATA);
0240         writeb(ctrl, idev->base + CORE_I2C_CTRL);
0241         if (idev->msg_len == 0)
0242             finished = true;
0243         break;
0244     case STATUS_M_ARB_LOST:
0245         idev->msg_err = -EAGAIN;
0246         finished = true;
0247         break;
0248     case STATUS_M_SLAW_ACK:
0249     case STATUS_M_TX_DATA_ACK:
0250         if (idev->msg_len > 0)
0251             mchp_corei2c_fill_tx(idev);
0252         else
0253             last_byte = true;
0254         break;
0255     case STATUS_M_TX_DATA_NACK:
0256     case STATUS_M_SLAR_NACK:
0257     case STATUS_M_SLAW_NACK:
0258         idev->msg_err = -ENXIO;
0259         last_byte = true;
0260         break;
0261     case STATUS_M_SLAR_ACK:
0262         ctrl = readb(idev->base + CORE_I2C_CTRL);
0263         if (idev->msg_len == 1u) {
0264             ctrl &= ~CTRL_AA;
0265             writeb(ctrl, idev->base + CORE_I2C_CTRL);
0266         } else {
0267             ctrl |= CTRL_AA;
0268             writeb(ctrl, idev->base + CORE_I2C_CTRL);
0269         }
0270         if (idev->msg_len < 1u)
0271             last_byte = true;
0272         break;
0273     case STATUS_M_RX_DATA_ACKED:
0274         mchp_corei2c_empty_rx(idev);
0275         break;
0276     case STATUS_M_RX_DATA_NACKED:
0277         mchp_corei2c_empty_rx(idev);
0278         if (idev->msg_len == 0)
0279             last_byte = true;
0280         break;
0281     default:
0282         break;
0283     }
0284
0285     /* On the last byte to be transmitted, send STOP */
0286     if (last_byte)
0287         mchp_corei2c_stop(idev);
0288
0289     if (last_byte || finished)
0290         complete(&idev->msg_complete);
0291
0292     return IRQ_HANDLED;
0293 }
0294
0295 static irqreturn_t mchp_corei2c_isr(int irq, void *_dev)
0296 {
0297     struct mchp_corei2c_dev *idev = _dev;
0298     irqreturn_t ret = IRQ_NONE;
0299     u8 ctrl;
0300
0301     ctrl = readb(idev->base + CORE_I2C_CTRL);
0302     if (ctrl & CTRL_SI) {
0303         idev->isr_status = readb(idev->base + CORE_I2C_STATUS);
0304         ret = mchp_corei2c_handle_isr(idev);
0305     }
0306
0307     ctrl = readb(idev->base + CORE_I2C_CTRL);
0308     ctrl &= ~CTRL_SI;
0309     writeb(ctrl, idev->base + CORE_I2C_CTRL);
0310
0311     return ret;
0312 }
0313
0314 static int mchp_corei2c_xfer_msg(struct mchp_corei2c_dev *idev,
0315                  struct i2c_msg *msg)
0316 {
0317     u8 ctrl;
0318     unsigned long time_left;
0319
0320     idev->addr = i2c_8bit_addr_from_msg(msg);
0321     idev->msg_len = msg->len;
0322     idev->buf = msg->buf;
0323     idev->msg_err = 0;
0324
0325     reinit_completion(&idev->msg_complete);
0326
0327     mchp_corei2c_core_enable(idev);
0328
0329     ctrl = readb(idev->base + CORE_I2C_CTRL);
0330     ctrl |= CTRL_STA;
0331     writeb(ctrl, idev->base + CORE_I2C_CTRL);
0332
0333     time_left = wait_for_completion_timeout(&idev->msg_complete,
0334                         idev->adapter.timeout);
0335     if (!time_left)
0336         return -ETIMEDOUT;
0337
0338     return idev->msg_err;
0339 }
0340
0341 static int mchp_corei2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
0342                  int num)
0343 {
0344     struct mchp_corei2c_dev *idev = i2c_get_adapdata(adap);
0345     int i, ret;
0346
0347     for (i = 0; i < num; i++) {
0348         ret = mchp_corei2c_xfer_msg(idev, msgs++);
0349         if (ret)
0350             return ret;
0351     }
0352
0353     return num;
0354 }
0355
0356 static u32 mchp_corei2c_func(struct i2c_adapter *adap)
0357 {
0358     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0359 }
0360
0361 static const struct i2c_algorithm mchp_corei2c_algo = {
0362     .master_xfer = mchp_corei2c_xfer,
0363     .functionality = mchp_corei2c_func,
0364 };
0365
0366 static int mchp_corei2c_probe(struct platform_device *pdev)
0367 {
0368     struct mchp_corei2c_dev *idev;
0369     struct resource *res;
0370     int irq, ret;
0371
0372     idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
0373     if (!idev)
0374         return -ENOMEM;
0375
0376     idev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0377     if (IS_ERR(idev->base))
0378         return PTR_ERR(idev->base);
0379
0380     irq = platform_get_irq(pdev, 0);
0381     if (irq <= 0)
0382         return dev_err_probe(&pdev->dev, -ENXIO,
0383                      "invalid IRQ %d for I2C controller\n", irq);
0384
0385     idev->i2c_clk = devm_clk_get(&pdev->dev, NULL);
0386     if (IS_ERR(idev->i2c_clk))
0387         return dev_err_probe(&pdev->dev, PTR_ERR(idev->i2c_clk),
0388                      "missing clock\n");
0389
0390     idev->dev = &pdev->dev;
0391     init_completion(&idev->msg_complete);
0392
0393     ret = device_property_read_u32(idev->dev, "clock-frequency",
0394                        &idev->bus_clk_rate);
0395     if (ret || !idev->bus_clk_rate) {
0396         dev_info(&pdev->dev, "default to 100kHz\n");
0397         idev->bus_clk_rate = 100000;
0398     }
0399
0400     if (idev->bus_clk_rate > 400000)
0401         return dev_err_probe(&pdev->dev, -EINVAL,
0402                      "clock-frequency too high: %d\n",
0403                      idev->bus_clk_rate);
0404
0405     /*
0406      * This driver supports both the hard peripherals & soft FPGA cores.
0407      * The hard peripherals do not have shared IRQs, but we don't have
0408      * control over what way the interrupts are wired for the soft cores.
0409      */
0410     ret = devm_request_irq(&pdev->dev, irq, mchp_corei2c_isr, IRQF_SHARED,
0411                    pdev->name, idev);
0412     if (ret)
0413         return dev_err_probe(&pdev->dev, ret,
0414                      "failed to claim irq %d\n", irq);
0415
0416     ret = clk_prepare_enable(idev->i2c_clk);
0417     if (ret)
0418         return dev_err_probe(&pdev->dev, ret,
0419                      "failed to enable clock\n");
0420
0421     ret = mchp_corei2c_init(idev);
0422     if (ret) {
0423         clk_disable_unprepare(idev->i2c_clk);
0424         return dev_err_probe(&pdev->dev, ret, "failed to program clock divider\n");
0425     }
0426
0427     i2c_set_adapdata(&idev->adapter, idev);
0428     snprintf(idev->adapter.name, sizeof(idev->adapter.name),
0429          "Microchip I2C hw bus at %08lx", (unsigned long)res->start);
0430     idev->adapter.owner = THIS_MODULE;
0431     idev->adapter.algo = &mchp_corei2c_algo;
0432     idev->adapter.dev.parent = &pdev->dev;
0433     idev->adapter.dev.of_node = pdev->dev.of_node;
0434     idev->adapter.timeout = HZ;
0435
0436     platform_set_drvdata(pdev, idev);
0437
0438     ret = i2c_add_adapter(&idev->adapter);
0439     if (ret) {
0440         clk_disable_unprepare(idev->i2c_clk);
0441         return ret;
0442     }
0443
0444     dev_info(&pdev->dev, "registered CoreI2C bus driver\n");
0445
0446     return 0;
0447 }
0448
0449 static int mchp_corei2c_remove(struct platform_device *pdev)
0450 {
0451     struct mchp_corei2c_dev *idev = platform_get_drvdata(pdev);
0452
0453     clk_disable_unprepare(idev->i2c_clk);
0454     i2c_del_adapter(&idev->adapter);
0455
0456     return 0;
0457 }
0458
0459 static const struct of_device_id mchp_corei2c_of_match[] = {
0460     { .compatible = "microchip,mpfs-i2c" },
0461     { .compatible = "microchip,corei2c-rtl-v7" },
0462     {},
0463 };
0464 MODULE_DEVICE_TABLE(of, mchp_corei2c_of_match);
0465
0466 static struct platform_driver mchp_corei2c_driver = {
0467     .probe = mchp_corei2c_probe,
0468     .remove = mchp_corei2c_remove,
0469     .driver = {
0470         .name = "microchip-corei2c",
0471         .of_match_table = mchp_corei2c_of_match,
0472     },
0473 };
0474
0475 module_platform_driver(mchp_corei2c_driver);
0476
0477 MODULE_DESCRIPTION("Microchip CoreI2C bus driver");
0478 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
0479 MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
0480 MODULE_LICENSE("GPL");