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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * I2C bus driver for Amlogic Meson SoCs
0004  *
0005  * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/clk.h>
0010 #include <linux/completion.h>
0011 #include <linux/i2c.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/iopoll.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/of_device.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/types.h>
0021 
0022 /* Meson I2C register map */
0023 #define REG_CTRL        0x00
0024 #define REG_SLAVE_ADDR      0x04
0025 #define REG_TOK_LIST0       0x08
0026 #define REG_TOK_LIST1       0x0c
0027 #define REG_TOK_WDATA0      0x10
0028 #define REG_TOK_WDATA1      0x14
0029 #define REG_TOK_RDATA0      0x18
0030 #define REG_TOK_RDATA1      0x1c
0031 
0032 /* Control register fields */
0033 #define REG_CTRL_START          BIT(0)
0034 #define REG_CTRL_ACK_IGNORE     BIT(1)
0035 #define REG_CTRL_STATUS         BIT(2)
0036 #define REG_CTRL_ERROR          BIT(3)
0037 #define REG_CTRL_CLKDIV_SHIFT       12
0038 #define REG_CTRL_CLKDIV_MASK        GENMASK(21, REG_CTRL_CLKDIV_SHIFT)
0039 #define REG_CTRL_CLKDIVEXT_SHIFT    28
0040 #define REG_CTRL_CLKDIVEXT_MASK     GENMASK(29, REG_CTRL_CLKDIVEXT_SHIFT)
0041 
0042 #define REG_SLV_ADDR_MASK       GENMASK(7, 0)
0043 #define REG_SLV_SDA_FILTER_MASK     GENMASK(10, 8)
0044 #define REG_SLV_SCL_FILTER_MASK     GENMASK(13, 11)
0045 #define REG_SLV_SCL_LOW_SHIFT       16
0046 #define REG_SLV_SCL_LOW_MASK        GENMASK(27, REG_SLV_SCL_LOW_SHIFT)
0047 #define REG_SLV_SCL_LOW_EN      BIT(28)
0048 
0049 #define I2C_TIMEOUT_MS      500
0050 #define FILTER_DELAY        15
0051 
0052 enum {
0053     TOKEN_END = 0,
0054     TOKEN_START,
0055     TOKEN_SLAVE_ADDR_WRITE,
0056     TOKEN_SLAVE_ADDR_READ,
0057     TOKEN_DATA,
0058     TOKEN_DATA_LAST,
0059     TOKEN_STOP,
0060 };
0061 
0062 enum {
0063     STATE_IDLE,
0064     STATE_READ,
0065     STATE_WRITE,
0066 };
0067 
0068 /**
0069  * struct meson_i2c - Meson I2C device private data
0070  *
0071  * @adap:   I2C adapter instance
0072  * @dev:    Pointer to device structure
0073  * @regs:   Base address of the device memory mapped registers
0074  * @clk:    Pointer to clock structure
0075  * @msg:    Pointer to the current I2C message
0076  * @state:  Current state in the driver state machine
0077  * @last:   Flag set for the last message in the transfer
0078  * @count:  Number of bytes to be sent/received in current transfer
0079  * @pos:    Current position in the send/receive buffer
0080  * @error:  Flag set when an error is received
0081  * @lock:   To avoid race conditions between irq handler and xfer code
0082  * @done:   Completion used to wait for transfer termination
0083  * @tokens: Sequence of tokens to be written to the device
0084  * @num_tokens: Number of tokens
0085  * @data:   Pointer to the controller's platform data
0086  */
0087 struct meson_i2c {
0088     struct i2c_adapter  adap;
0089     struct device       *dev;
0090     void __iomem        *regs;
0091     struct clk      *clk;
0092 
0093     struct i2c_msg      *msg;
0094     int         state;
0095     bool            last;
0096     int         count;
0097     int         pos;
0098     int         error;
0099 
0100     spinlock_t      lock;
0101     struct completion   done;
0102     u32         tokens[2];
0103     int         num_tokens;
0104 
0105     const struct meson_i2c_data *data;
0106 };
0107 
0108 struct meson_i2c_data {
0109     void (*set_clk_div)(struct meson_i2c *i2c, unsigned int freq);
0110 };
0111 
0112 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
0113                    u32 val)
0114 {
0115     u32 data;
0116 
0117     data = readl(i2c->regs + reg);
0118     data &= ~mask;
0119     data |= val & mask;
0120     writel(data, i2c->regs + reg);
0121 }
0122 
0123 static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
0124 {
0125     i2c->tokens[0] = 0;
0126     i2c->tokens[1] = 0;
0127     i2c->num_tokens = 0;
0128 }
0129 
0130 static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
0131 {
0132     if (i2c->num_tokens < 8)
0133         i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
0134     else
0135         i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
0136 
0137     i2c->num_tokens++;
0138 }
0139 
0140 static void meson_gxbb_axg_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
0141 {
0142     unsigned long clk_rate = clk_get_rate(i2c->clk);
0143     unsigned int div_h, div_l;
0144 
0145     /* According to I2C-BUS Spec 2.1, in FAST-MODE, the minimum LOW period is 1.3uS, and
0146      * minimum HIGH is least 0.6us.
0147      * For 400000 freq, the period is 2.5us. To keep within the specs, give 40% of period to
0148      * HIGH and 60% to LOW. This means HIGH at 1.0us and LOW 1.5us.
0149      * The same applies for Fast-mode plus, where LOW is 0.5us and HIGH is 0.26us.
0150      * Duty = H/(H + L) = 2/5
0151      */
0152     if (freq <= I2C_MAX_STANDARD_MODE_FREQ) {
0153         div_h = DIV_ROUND_UP(clk_rate, freq);
0154         div_l = DIV_ROUND_UP(div_h, 4);
0155         div_h = DIV_ROUND_UP(div_h, 2) - FILTER_DELAY;
0156     } else {
0157         div_h = DIV_ROUND_UP(clk_rate * 2, freq * 5) - FILTER_DELAY;
0158         div_l = DIV_ROUND_UP(clk_rate * 3, freq * 5 * 2);
0159     }
0160 
0161     /* clock divider has 12 bits */
0162     if (div_h > GENMASK(11, 0)) {
0163         dev_err(i2c->dev, "requested bus frequency too low\n");
0164         div_h = GENMASK(11, 0);
0165     }
0166     if (div_l > GENMASK(11, 0)) {
0167         dev_err(i2c->dev, "requested bus frequency too low\n");
0168         div_l = GENMASK(11, 0);
0169     }
0170 
0171     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
0172                FIELD_PREP(REG_CTRL_CLKDIV_MASK, div_h & GENMASK(9, 0)));
0173 
0174     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
0175                FIELD_PREP(REG_CTRL_CLKDIVEXT_MASK, div_h >> 10));
0176 
0177     /* set SCL low delay */
0178     meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_MASK,
0179                FIELD_PREP(REG_SLV_SCL_LOW_MASK, div_l));
0180 
0181     /* Enable HIGH/LOW mode */
0182     meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, REG_SLV_SCL_LOW_EN);
0183 
0184     dev_dbg(i2c->dev, "%s: clk %lu, freq %u, divh %u, divl %u\n", __func__,
0185         clk_rate, freq, div_h, div_l);
0186 }
0187 
0188 static void meson6_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
0189 {
0190     unsigned long clk_rate = clk_get_rate(i2c->clk);
0191     unsigned int div;
0192 
0193     div = DIV_ROUND_UP(clk_rate, freq);
0194     div -= FILTER_DELAY;
0195     div = DIV_ROUND_UP(div, 4);
0196 
0197     /* clock divider has 12 bits */
0198     if (div > GENMASK(11, 0)) {
0199         dev_err(i2c->dev, "requested bus frequency too low\n");
0200         div = GENMASK(11, 0);
0201     }
0202 
0203     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
0204                FIELD_PREP(REG_CTRL_CLKDIV_MASK, div & GENMASK(9, 0)));
0205 
0206     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
0207                FIELD_PREP(REG_CTRL_CLKDIVEXT_MASK, div >> 10));
0208 
0209     /* Disable HIGH/LOW mode */
0210     meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, 0);
0211 
0212     dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
0213         clk_rate, freq, div);
0214 }
0215 
0216 static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
0217 {
0218     u32 rdata0, rdata1;
0219     int i;
0220 
0221     rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
0222     rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
0223 
0224     dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
0225         rdata0, rdata1, len);
0226 
0227     for (i = 0; i < min(4, len); i++)
0228         *buf++ = (rdata0 >> i * 8) & 0xff;
0229 
0230     for (i = 4; i < min(8, len); i++)
0231         *buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
0232 }
0233 
0234 static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
0235 {
0236     u32 wdata0 = 0, wdata1 = 0;
0237     int i;
0238 
0239     for (i = 0; i < min(4, len); i++)
0240         wdata0 |= *buf++ << (i * 8);
0241 
0242     for (i = 4; i < min(8, len); i++)
0243         wdata1 |= *buf++ << ((i - 4) * 8);
0244 
0245     writel(wdata0, i2c->regs + REG_TOK_WDATA0);
0246     writel(wdata1, i2c->regs + REG_TOK_WDATA1);
0247 
0248     dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
0249         wdata0, wdata1, len);
0250 }
0251 
0252 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
0253 {
0254     bool write = !(i2c->msg->flags & I2C_M_RD);
0255     int i;
0256 
0257     i2c->count = min(i2c->msg->len - i2c->pos, 8);
0258 
0259     for (i = 0; i < i2c->count - 1; i++)
0260         meson_i2c_add_token(i2c, TOKEN_DATA);
0261 
0262     if (i2c->count) {
0263         if (write || i2c->pos + i2c->count < i2c->msg->len)
0264             meson_i2c_add_token(i2c, TOKEN_DATA);
0265         else
0266             meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
0267     }
0268 
0269     if (write)
0270         meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
0271 
0272     if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
0273         meson_i2c_add_token(i2c, TOKEN_STOP);
0274 
0275     writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
0276     writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
0277 }
0278 
0279 static void meson_i2c_transfer_complete(struct meson_i2c *i2c, u32 ctrl)
0280 {
0281     if (ctrl & REG_CTRL_ERROR) {
0282         /*
0283          * The bit is set when the IGNORE_NAK bit is cleared
0284          * and the device didn't respond. In this case, the
0285          * I2C controller automatically generates a STOP
0286          * condition.
0287          */
0288         dev_dbg(i2c->dev, "error bit set\n");
0289         i2c->error = -ENXIO;
0290         i2c->state = STATE_IDLE;
0291     } else {
0292         if (i2c->state == STATE_READ && i2c->count)
0293             meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos,
0294                        i2c->count);
0295 
0296         i2c->pos += i2c->count;
0297 
0298         if (i2c->pos >= i2c->msg->len)
0299             i2c->state = STATE_IDLE;
0300     }
0301 }
0302 
0303 static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
0304 {
0305     struct meson_i2c *i2c = dev_id;
0306     unsigned int ctrl;
0307 
0308     spin_lock(&i2c->lock);
0309 
0310     meson_i2c_reset_tokens(i2c);
0311     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
0312     ctrl = readl(i2c->regs + REG_CTRL);
0313 
0314     dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
0315         i2c->state, i2c->pos, i2c->count, ctrl);
0316 
0317     if (i2c->state == STATE_IDLE) {
0318         spin_unlock(&i2c->lock);
0319         return IRQ_NONE;
0320     }
0321 
0322     meson_i2c_transfer_complete(i2c, ctrl);
0323 
0324     if (i2c->state == STATE_IDLE) {
0325         complete(&i2c->done);
0326         goto out;
0327     }
0328 
0329     /* Restart the processing */
0330     meson_i2c_prepare_xfer(i2c);
0331     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
0332 out:
0333     spin_unlock(&i2c->lock);
0334 
0335     return IRQ_HANDLED;
0336 }
0337 
0338 static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
0339 {
0340     int token;
0341 
0342     token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
0343         TOKEN_SLAVE_ADDR_WRITE;
0344 
0345 
0346     meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_ADDR_MASK,
0347                FIELD_PREP(REG_SLV_ADDR_MASK, msg->addr << 1));
0348 
0349     meson_i2c_add_token(i2c, TOKEN_START);
0350     meson_i2c_add_token(i2c, token);
0351 }
0352 
0353 static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
0354                   int last, bool atomic)
0355 {
0356     unsigned long time_left, flags;
0357     int ret = 0;
0358     u32 ctrl;
0359 
0360     i2c->msg = msg;
0361     i2c->last = last;
0362     i2c->pos = 0;
0363     i2c->count = 0;
0364     i2c->error = 0;
0365 
0366     meson_i2c_reset_tokens(i2c);
0367 
0368     flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
0369     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
0370 
0371     if (!(msg->flags & I2C_M_NOSTART))
0372         meson_i2c_do_start(i2c, msg);
0373 
0374     i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
0375     meson_i2c_prepare_xfer(i2c);
0376 
0377     if (!atomic)
0378         reinit_completion(&i2c->done);
0379 
0380     /* Start the transfer */
0381     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
0382 
0383     if (atomic) {
0384         ret = readl_poll_timeout_atomic(i2c->regs + REG_CTRL, ctrl,
0385                         !(ctrl & REG_CTRL_STATUS),
0386                         10, I2C_TIMEOUT_MS * 1000);
0387     } else {
0388         time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
0389         time_left = wait_for_completion_timeout(&i2c->done, time_left);
0390 
0391         if (!time_left)
0392             ret = -ETIMEDOUT;
0393     }
0394 
0395     /*
0396      * Protect access to i2c struct and registers from interrupt
0397      * handlers triggered by a transfer terminated after the
0398      * timeout period
0399      */
0400     spin_lock_irqsave(&i2c->lock, flags);
0401 
0402     if (atomic && !ret)
0403         meson_i2c_transfer_complete(i2c, ctrl);
0404 
0405     /* Abort any active operation */
0406     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
0407 
0408     if (ret)
0409         i2c->state = STATE_IDLE;
0410 
0411     if (i2c->error)
0412         ret = i2c->error;
0413 
0414     spin_unlock_irqrestore(&i2c->lock, flags);
0415 
0416     return ret;
0417 }
0418 
0419 static int meson_i2c_xfer_messages(struct i2c_adapter *adap,
0420                    struct i2c_msg *msgs, int num, bool atomic)
0421 {
0422     struct meson_i2c *i2c = adap->algo_data;
0423     int i, ret = 0;
0424 
0425     for (i = 0; i < num; i++) {
0426         ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1, atomic);
0427         if (ret)
0428             break;
0429     }
0430 
0431     return ret ?: i;
0432 }
0433 
0434 static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
0435               int num)
0436 {
0437     return meson_i2c_xfer_messages(adap, msgs, num, false);
0438 }
0439 
0440 static int meson_i2c_xfer_atomic(struct i2c_adapter *adap,
0441                  struct i2c_msg *msgs, int num)
0442 {
0443     return meson_i2c_xfer_messages(adap, msgs, num, true);
0444 }
0445 
0446 static u32 meson_i2c_func(struct i2c_adapter *adap)
0447 {
0448     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0449 }
0450 
0451 static const struct i2c_algorithm meson_i2c_algorithm = {
0452     .master_xfer = meson_i2c_xfer,
0453     .master_xfer_atomic = meson_i2c_xfer_atomic,
0454     .functionality = meson_i2c_func,
0455 };
0456 
0457 static int meson_i2c_probe(struct platform_device *pdev)
0458 {
0459     struct device_node *np = pdev->dev.of_node;
0460     struct meson_i2c *i2c;
0461     struct i2c_timings timings;
0462     int irq, ret = 0;
0463 
0464     i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
0465     if (!i2c)
0466         return -ENOMEM;
0467 
0468     i2c_parse_fw_timings(&pdev->dev, &timings, true);
0469 
0470     i2c->dev = &pdev->dev;
0471     platform_set_drvdata(pdev, i2c);
0472 
0473     spin_lock_init(&i2c->lock);
0474     init_completion(&i2c->done);
0475 
0476     i2c->data = (const struct meson_i2c_data *)
0477         of_device_get_match_data(&pdev->dev);
0478 
0479     i2c->clk = devm_clk_get(&pdev->dev, NULL);
0480     if (IS_ERR(i2c->clk)) {
0481         dev_err(&pdev->dev, "can't get device clock\n");
0482         return PTR_ERR(i2c->clk);
0483     }
0484 
0485     i2c->regs = devm_platform_ioremap_resource(pdev, 0);
0486     if (IS_ERR(i2c->regs))
0487         return PTR_ERR(i2c->regs);
0488 
0489     irq = platform_get_irq(pdev, 0);
0490     if (irq < 0)
0491         return irq;
0492 
0493     ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
0494     if (ret < 0) {
0495         dev_err(&pdev->dev, "can't request IRQ\n");
0496         return ret;
0497     }
0498 
0499     ret = clk_prepare_enable(i2c->clk);
0500     if (ret < 0) {
0501         dev_err(&pdev->dev, "can't prepare clock\n");
0502         return ret;
0503     }
0504 
0505     strscpy(i2c->adap.name, "Meson I2C adapter",
0506         sizeof(i2c->adap.name));
0507     i2c->adap.owner = THIS_MODULE;
0508     i2c->adap.algo = &meson_i2c_algorithm;
0509     i2c->adap.dev.parent = &pdev->dev;
0510     i2c->adap.dev.of_node = np;
0511     i2c->adap.algo_data = i2c;
0512 
0513     /*
0514      * A transfer is triggered when START bit changes from 0 to 1.
0515      * Ensure that the bit is set to 0 after probe
0516      */
0517     meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
0518 
0519     /* Disable filtering */
0520     meson_i2c_set_mask(i2c, REG_SLAVE_ADDR,
0521                REG_SLV_SDA_FILTER_MASK | REG_SLV_SCL_FILTER_MASK, 0);
0522 
0523     if (!i2c->data->set_clk_div) {
0524         clk_disable_unprepare(i2c->clk);
0525         return -EINVAL;
0526     }
0527     i2c->data->set_clk_div(i2c, timings.bus_freq_hz);
0528 
0529     ret = i2c_add_adapter(&i2c->adap);
0530     if (ret < 0) {
0531         clk_disable_unprepare(i2c->clk);
0532         return ret;
0533     }
0534 
0535     return 0;
0536 }
0537 
0538 static int meson_i2c_remove(struct platform_device *pdev)
0539 {
0540     struct meson_i2c *i2c = platform_get_drvdata(pdev);
0541 
0542     i2c_del_adapter(&i2c->adap);
0543     clk_disable_unprepare(i2c->clk);
0544 
0545     return 0;
0546 }
0547 
0548 static const struct meson_i2c_data i2c_meson6_data = {
0549     .set_clk_div = meson6_i2c_set_clk_div,
0550 };
0551 
0552 static const struct meson_i2c_data i2c_gxbb_data = {
0553     .set_clk_div = meson_gxbb_axg_i2c_set_clk_div,
0554 };
0555 
0556 static const struct meson_i2c_data i2c_axg_data = {
0557     .set_clk_div = meson_gxbb_axg_i2c_set_clk_div,
0558 };
0559 
0560 static const struct of_device_id meson_i2c_match[] = {
0561     { .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data },
0562     { .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data },
0563     { .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data },
0564     {},
0565 };
0566 
0567 MODULE_DEVICE_TABLE(of, meson_i2c_match);
0568 
0569 static struct platform_driver meson_i2c_driver = {
0570     .probe   = meson_i2c_probe,
0571     .remove  = meson_i2c_remove,
0572     .driver  = {
0573         .name  = "meson-i2c",
0574         .of_match_table = meson_i2c_match,
0575     },
0576 };
0577 
0578 module_platform_driver(meson_i2c_driver);
0579 
0580 MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
0581 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
0582 MODULE_LICENSE("GPL v2");
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