i2c/busses/i2c-lpc2k.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2011 NXP Semiconductors
0004  *
0005  * Code portions referenced from the i2x-pxa and i2c-pnx drivers
0006  *
0007  * Make SMBus byte and word transactions work on LPC178x/7x
0008  * Copyright (c) 2012
0009  * Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
0010  * Anton Protopopov, Emcraft Systems, antonp@emcraft.com
0011  *
0012  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
0013  */
0014
0015 #include <linux/clk.h>
0016 #include <linux/errno.h>
0017 #include <linux/i2c.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/io.h>
0020 #include <linux/kernel.h>
0021 #include <linux/module.h>
0022 #include <linux/of.h>
0023 #include <linux/of_device.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/sched.h>
0026 #include <linux/time.h>
0027
0028 /* LPC24xx register offsets and bits */
0029 #define LPC24XX_I2CONSET    0x00
0030 #define LPC24XX_I2STAT      0x04
0031 #define LPC24XX_I2DAT       0x08
0032 #define LPC24XX_I2ADDR      0x0c
0033 #define LPC24XX_I2SCLH      0x10
0034 #define LPC24XX_I2SCLL      0x14
0035 #define LPC24XX_I2CONCLR    0x18
0036
0037 #define LPC24XX_AA      BIT(2)
0038 #define LPC24XX_SI      BIT(3)
0039 #define LPC24XX_STO     BIT(4)
0040 #define LPC24XX_STA     BIT(5)
0041 #define LPC24XX_I2EN        BIT(6)
0042
0043 #define LPC24XX_STO_AA      (LPC24XX_STO | LPC24XX_AA)
0044 #define LPC24XX_CLEAR_ALL   (LPC24XX_AA | LPC24XX_SI | LPC24XX_STO | \
0045                  LPC24XX_STA | LPC24XX_I2EN)
0046
0047 /* I2C SCL clock has different duty cycle depending on mode */
0048 #define I2C_STD_MODE_DUTY       46
0049 #define I2C_FAST_MODE_DUTY      36
0050 #define I2C_FAST_MODE_PLUS_DUTY     38
0051
0052 /*
0053  * 26 possible I2C status codes, but codes applicable only
0054  * to master are listed here and used in this driver
0055  */
0056 enum {
0057     M_BUS_ERROR     = 0x00,
0058     M_START         = 0x08,
0059     M_REPSTART      = 0x10,
0060     MX_ADDR_W_ACK       = 0x18,
0061     MX_ADDR_W_NACK      = 0x20,
0062     MX_DATA_W_ACK       = 0x28,
0063     MX_DATA_W_NACK      = 0x30,
0064     M_DATA_ARB_LOST     = 0x38,
0065     MR_ADDR_R_ACK       = 0x40,
0066     MR_ADDR_R_NACK      = 0x48,
0067     MR_DATA_R_ACK       = 0x50,
0068     MR_DATA_R_NACK      = 0x58,
0069     M_I2C_IDLE      = 0xf8,
0070 };
0071
0072 struct lpc2k_i2c {
0073     void __iomem        *base;
0074     struct clk      *clk;
0075     int         irq;
0076     wait_queue_head_t   wait;
0077     struct i2c_adapter  adap;
0078     struct i2c_msg      *msg;
0079     int         msg_idx;
0080     int         msg_status;
0081     int         is_last;
0082 };
0083
0084 static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c)
0085 {
0086     /* Will force clear all statuses */
0087     writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR);
0088     writel(0, i2c->base + LPC24XX_I2ADDR);
0089     writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET);
0090 }
0091
0092 static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c)
0093 {
0094     unsigned long timeout = jiffies + msecs_to_jiffies(1000);
0095
0096     /*
0097      * If the transfer needs to abort for some reason, we'll try to
0098      * force a stop condition to clear any pending bus conditions
0099      */
0100     writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET);
0101
0102     /* Wait for status change */
0103     while (readl(i2c->base + LPC24XX_I2STAT) != M_I2C_IDLE) {
0104         if (time_after(jiffies, timeout)) {
0105             /* Bus was not idle, try to reset adapter */
0106             i2c_lpc2k_reset(i2c);
0107             return -EBUSY;
0108         }
0109
0110         cpu_relax();
0111     }
0112
0113     return 0;
0114 }
0115
0116 static void i2c_lpc2k_pump_msg(struct lpc2k_i2c *i2c)
0117 {
0118     unsigned char data;
0119     u32 status;
0120
0121     /*
0122      * I2C in the LPC2xxx series is basically a state machine.
0123      * Just run through the steps based on the current status.
0124      */
0125     status = readl(i2c->base + LPC24XX_I2STAT);
0126
0127     switch (status) {
0128     case M_START:
0129     case M_REPSTART:
0130         /* Start bit was just sent out, send out addr and dir */
0131         data = i2c_8bit_addr_from_msg(i2c->msg);
0132
0133         writel(data, i2c->base + LPC24XX_I2DAT);
0134         writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
0135         break;
0136
0137     case MX_ADDR_W_ACK:
0138     case MX_DATA_W_ACK:
0139         /*
0140          * Address or data was sent out with an ACK. If there is more
0141          * data to send, send it now
0142          */
0143         if (i2c->msg_idx < i2c->msg->len) {
0144             writel(i2c->msg->buf[i2c->msg_idx],
0145                    i2c->base + LPC24XX_I2DAT);
0146         } else if (i2c->is_last) {
0147             /* Last message, send stop */
0148             writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
0149             writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
0150             i2c->msg_status = 0;
0151             disable_irq_nosync(i2c->irq);
0152         } else {
0153             i2c->msg_status = 0;
0154             disable_irq_nosync(i2c->irq);
0155         }
0156
0157         i2c->msg_idx++;
0158         break;
0159
0160     case MR_ADDR_R_ACK:
0161         /* Receive first byte from slave */
0162         if (i2c->msg->len == 1) {
0163             /* Last byte, return NACK */
0164             writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
0165         } else {
0166             /* Not last byte, return ACK */
0167             writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
0168         }
0169
0170         writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
0171         break;
0172
0173     case MR_DATA_R_NACK:
0174         /*
0175          * The I2C shows NACK status on reads, so we need to accept
0176          * the NACK as an ACK here. This should be ok, as the real
0177          * BACK would of been caught on the address write.
0178          */
0179     case MR_DATA_R_ACK:
0180         /* Data was received */
0181         if (i2c->msg_idx < i2c->msg->len) {
0182             i2c->msg->buf[i2c->msg_idx] =
0183                     readl(i2c->base + LPC24XX_I2DAT);
0184         }
0185
0186         /* If transfer is done, send STOP */
0187         if (i2c->msg_idx >= i2c->msg->len - 1 && i2c->is_last) {
0188             writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
0189             writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
0190             i2c->msg_status = 0;
0191         }
0192
0193         /* Message is done */
0194         if (i2c->msg_idx >= i2c->msg->len - 1) {
0195             i2c->msg_status = 0;
0196             disable_irq_nosync(i2c->irq);
0197         }
0198
0199         /*
0200          * One pre-last data input, send NACK to tell the slave that
0201          * this is going to be the last data byte to be transferred.
0202          */
0203         if (i2c->msg_idx >= i2c->msg->len - 2) {
0204             /* One byte left to receive - NACK */
0205             writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR);
0206         } else {
0207             /* More than one byte left to receive - ACK */
0208             writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET);
0209         }
0210
0211         writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR);
0212         i2c->msg_idx++;
0213         break;
0214
0215     case MX_ADDR_W_NACK:
0216     case MX_DATA_W_NACK:
0217     case MR_ADDR_R_NACK:
0218         /* NACK processing is done */
0219         writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET);
0220         i2c->msg_status = -ENXIO;
0221         disable_irq_nosync(i2c->irq);
0222         break;
0223
0224     case M_DATA_ARB_LOST:
0225         /* Arbitration lost */
0226         i2c->msg_status = -EAGAIN;
0227
0228         /* Release the I2C bus */
0229         writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR);
0230         disable_irq_nosync(i2c->irq);
0231         break;
0232
0233     default:
0234         /* Unexpected statuses */
0235         i2c->msg_status = -EIO;
0236         disable_irq_nosync(i2c->irq);
0237         break;
0238     }
0239
0240     /* Exit on failure or all bytes transferred */
0241     if (i2c->msg_status != -EBUSY)
0242         wake_up(&i2c->wait);
0243
0244     /*
0245      * If `msg_status` is zero, then `lpc2k_process_msg()`
0246      * is responsible for clearing the SI flag.
0247      */
0248     if (i2c->msg_status != 0)
0249         writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
0250 }
0251
0252 static int lpc2k_process_msg(struct lpc2k_i2c *i2c, int msgidx)
0253 {
0254     /* A new transfer is kicked off by initiating a start condition */
0255     if (!msgidx) {
0256         writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
0257     } else {
0258         /*
0259          * A multi-message I2C transfer continues where the
0260          * previous I2C transfer left off and uses the
0261          * current condition of the I2C adapter.
0262          */
0263         if (unlikely(i2c->msg->flags & I2C_M_NOSTART)) {
0264             WARN_ON(i2c->msg->len == 0);
0265
0266             if (!(i2c->msg->flags & I2C_M_RD)) {
0267                 /* Start transmit of data */
0268                 writel(i2c->msg->buf[0],
0269                        i2c->base + LPC24XX_I2DAT);
0270                 i2c->msg_idx++;
0271             }
0272         } else {
0273             /* Start or repeated start */
0274             writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET);
0275         }
0276
0277         writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR);
0278     }
0279
0280     enable_irq(i2c->irq);
0281
0282     /* Wait for transfer completion */
0283     if (wait_event_timeout(i2c->wait, i2c->msg_status != -EBUSY,
0284                    msecs_to_jiffies(1000)) == 0) {
0285         disable_irq_nosync(i2c->irq);
0286
0287         return -ETIMEDOUT;
0288     }
0289
0290     return i2c->msg_status;
0291 }
0292
0293 static int i2c_lpc2k_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
0294               int msg_num)
0295 {
0296     struct lpc2k_i2c *i2c = i2c_get_adapdata(adap);
0297     int ret, i;
0298     u32 stat;
0299
0300     /* Check for bus idle condition */
0301     stat = readl(i2c->base + LPC24XX_I2STAT);
0302     if (stat != M_I2C_IDLE) {
0303         /* Something is holding the bus, try to clear it */
0304         return i2c_lpc2k_clear_arb(i2c);
0305     }
0306
0307     /* Process a single message at a time */
0308     for (i = 0; i < msg_num; i++) {
0309         /* Save message pointer and current message data index */
0310         i2c->msg = &msgs[i];
0311         i2c->msg_idx = 0;
0312         i2c->msg_status = -EBUSY;
0313         i2c->is_last = (i == (msg_num - 1));
0314
0315         ret = lpc2k_process_msg(i2c, i);
0316         if (ret)
0317             return ret;
0318     }
0319
0320     return msg_num;
0321 }
0322
0323 static irqreturn_t i2c_lpc2k_handler(int irq, void *dev_id)
0324 {
0325     struct lpc2k_i2c *i2c = dev_id;
0326
0327     if (readl(i2c->base + LPC24XX_I2CONSET) & LPC24XX_SI) {
0328         i2c_lpc2k_pump_msg(i2c);
0329         return IRQ_HANDLED;
0330     }
0331
0332     return IRQ_NONE;
0333 }
0334
0335 static u32 i2c_lpc2k_functionality(struct i2c_adapter *adap)
0336 {
0337     /* Only emulated SMBus for now */
0338     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
0339 }
0340
0341 static const struct i2c_algorithm i2c_lpc2k_algorithm = {
0342     .master_xfer    = i2c_lpc2k_xfer,
0343     .functionality  = i2c_lpc2k_functionality,
0344 };
0345
0346 static int i2c_lpc2k_probe(struct platform_device *pdev)
0347 {
0348     struct lpc2k_i2c *i2c;
0349     u32 bus_clk_rate;
0350     u32 scl_high;
0351     u32 clkrate;
0352     int ret;
0353
0354     i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
0355     if (!i2c)
0356         return -ENOMEM;
0357
0358     i2c->base = devm_platform_ioremap_resource(pdev, 0);
0359     if (IS_ERR(i2c->base))
0360         return PTR_ERR(i2c->base);
0361
0362     i2c->irq = platform_get_irq(pdev, 0);
0363     if (i2c->irq < 0)
0364         return i2c->irq;
0365
0366     init_waitqueue_head(&i2c->wait);
0367
0368     i2c->clk = devm_clk_get(&pdev->dev, NULL);
0369     if (IS_ERR(i2c->clk)) {
0370         dev_err(&pdev->dev, "error getting clock\n");
0371         return PTR_ERR(i2c->clk);
0372     }
0373
0374     ret = clk_prepare_enable(i2c->clk);
0375     if (ret) {
0376         dev_err(&pdev->dev, "unable to enable clock.\n");
0377         return ret;
0378     }
0379
0380     ret = devm_request_irq(&pdev->dev, i2c->irq, i2c_lpc2k_handler, 0,
0381                    dev_name(&pdev->dev), i2c);
0382     if (ret < 0) {
0383         dev_err(&pdev->dev, "can't request interrupt.\n");
0384         goto fail_clk;
0385     }
0386
0387     disable_irq_nosync(i2c->irq);
0388
0389     /* Place controller is a known state */
0390     i2c_lpc2k_reset(i2c);
0391
0392     ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
0393                    &bus_clk_rate);
0394     if (ret)
0395         bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
0396
0397     clkrate = clk_get_rate(i2c->clk);
0398     if (clkrate == 0) {
0399         dev_err(&pdev->dev, "can't get I2C base clock\n");
0400         ret = -EINVAL;
0401         goto fail_clk;
0402     }
0403
0404     /* Setup I2C dividers to generate clock with proper duty cycle */
0405     clkrate = clkrate / bus_clk_rate;
0406     if (bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ)
0407         scl_high = (clkrate * I2C_STD_MODE_DUTY) / 100;
0408     else if (bus_clk_rate <= I2C_MAX_FAST_MODE_FREQ)
0409         scl_high = (clkrate * I2C_FAST_MODE_DUTY) / 100;
0410     else
0411         scl_high = (clkrate * I2C_FAST_MODE_PLUS_DUTY) / 100;
0412
0413     writel(scl_high, i2c->base + LPC24XX_I2SCLH);
0414     writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL);
0415
0416     platform_set_drvdata(pdev, i2c);
0417
0418     i2c_set_adapdata(&i2c->adap, i2c);
0419     i2c->adap.owner = THIS_MODULE;
0420     strscpy(i2c->adap.name, "LPC2K I2C adapter", sizeof(i2c->adap.name));
0421     i2c->adap.algo = &i2c_lpc2k_algorithm;
0422     i2c->adap.dev.parent = &pdev->dev;
0423     i2c->adap.dev.of_node = pdev->dev.of_node;
0424
0425     ret = i2c_add_adapter(&i2c->adap);
0426     if (ret < 0)
0427         goto fail_clk;
0428
0429     dev_info(&pdev->dev, "LPC2K I2C adapter\n");
0430
0431     return 0;
0432
0433 fail_clk:
0434     clk_disable_unprepare(i2c->clk);
0435     return ret;
0436 }
0437
0438 static int i2c_lpc2k_remove(struct platform_device *dev)
0439 {
0440     struct lpc2k_i2c *i2c = platform_get_drvdata(dev);
0441
0442     i2c_del_adapter(&i2c->adap);
0443     clk_disable_unprepare(i2c->clk);
0444
0445     return 0;
0446 }
0447
0448 #ifdef CONFIG_PM
0449 static int i2c_lpc2k_suspend(struct device *dev)
0450 {
0451     struct lpc2k_i2c *i2c = dev_get_drvdata(dev);
0452
0453     clk_disable(i2c->clk);
0454
0455     return 0;
0456 }
0457
0458 static int i2c_lpc2k_resume(struct device *dev)
0459 {
0460     struct lpc2k_i2c *i2c = dev_get_drvdata(dev);
0461
0462     clk_enable(i2c->clk);
0463     i2c_lpc2k_reset(i2c);
0464
0465     return 0;
0466 }
0467
0468 static const struct dev_pm_ops i2c_lpc2k_dev_pm_ops = {
0469     .suspend_noirq = i2c_lpc2k_suspend,
0470     .resume_noirq = i2c_lpc2k_resume,
0471 };
0472
0473 #define I2C_LPC2K_DEV_PM_OPS (&i2c_lpc2k_dev_pm_ops)
0474 #else
0475 #define I2C_LPC2K_DEV_PM_OPS NULL
0476 #endif
0477
0478 static const struct of_device_id lpc2k_i2c_match[] = {
0479     { .compatible = "nxp,lpc1788-i2c" },
0480     {},
0481 };
0482 MODULE_DEVICE_TABLE(of, lpc2k_i2c_match);
0483
0484 static struct platform_driver i2c_lpc2k_driver = {
0485     .probe  = i2c_lpc2k_probe,
0486     .remove = i2c_lpc2k_remove,
0487     .driver = {
0488         .name       = "lpc2k-i2c",
0489         .pm     = I2C_LPC2K_DEV_PM_OPS,
0490         .of_match_table = lpc2k_i2c_match,
0491     },
0492 };
0493 module_platform_driver(i2c_lpc2k_driver);
0494
0495 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
0496 MODULE_DESCRIPTION("I2C driver for LPC2xxx devices");
0497 MODULE_LICENSE("GPL");
0498 MODULE_ALIAS("platform:lpc2k-i2c");