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0001 /*
0002  * This file is provided under a dual BSD/GPLv2 license.  When using or
0003  * redistributing this file, you may do so under either license.
0004  *
0005  * Copyright(c) 2012 Intel Corporation. All rights reserved.
0006  *
0007  * GPL LICENSE SUMMARY
0008  *
0009  * This program is free software; you can redistribute it and/or modify
0010  * it under the terms of version 2 of the GNU General Public License as
0011  * published by the Free Software Foundation.
0012  *
0013  * This program is distributed in the hope that it will be useful, but
0014  * WITHOUT ANY WARRANTY; without even the implied warranty of
0015  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
0016  * General Public License for more details.
0017  * The full GNU General Public License is included in this distribution
0018  * in the file called LICENSE.GPL.
0019  *
0020  * BSD LICENSE
0021  *
0022  * Redistribution and use in source and binary forms, with or without
0023  * modification, are permitted provided that the following conditions
0024  * are met:
0025  *
0026  *   * Redistributions of source code must retain the above copyright
0027  *     notice, this list of conditions and the following disclaimer.
0028  *   * Redistributions in binary form must reproduce the above copyright
0029  *     notice, this list of conditions and the following disclaimer in
0030  *     the documentation and/or other materials provided with the
0031  *     distribution.
0032  *   * Neither the name of Intel Corporation nor the names of its
0033  *     contributors may be used to endorse or promote products derived
0034  *     from this software without specific prior written permission.
0035  *
0036  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0037  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0038  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
0039  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0040  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0041  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0042  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
0043  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
0044  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0045  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
0046  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0047  */
0048 
0049 /*
0050  *  Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
0051  *  S12xx Product Family.
0052  *
0053  *  Features supported by this driver:
0054  *  Hardware PEC                     yes
0055  *  Block buffer                     yes
0056  *  Block process call transaction   yes
0057  *  Slave mode                       no
0058  */
0059 
0060 #include <linux/module.h>
0061 #include <linux/pci.h>
0062 #include <linux/kernel.h>
0063 #include <linux/stddef.h>
0064 #include <linux/completion.h>
0065 #include <linux/dma-mapping.h>
0066 #include <linux/i2c.h>
0067 #include <linux/acpi.h>
0068 #include <linux/interrupt.h>
0069 
0070 #include <linux/io-64-nonatomic-lo-hi.h>
0071 
0072 /* PCI Address Constants */
0073 #define SMBBAR      0
0074 
0075 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
0076 #define PCI_DEVICE_ID_INTEL_S1200_SMT0  0x0c59
0077 #define PCI_DEVICE_ID_INTEL_S1200_SMT1  0x0c5a
0078 #define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac
0079 #define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac
0080 #define PCI_DEVICE_ID_INTEL_EBG_SMT 0x1bff
0081 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT  0x1f15
0082 
0083 #define ISMT_DESC_ENTRIES   2   /* number of descriptor entries */
0084 #define ISMT_MAX_RETRIES    3   /* number of SMBus retries to attempt */
0085 #define ISMT_LOG_ENTRIES    3   /* number of interrupt cause log entries */
0086 
0087 /* Hardware Descriptor Constants - Control Field */
0088 #define ISMT_DESC_CWRL  0x01    /* Command/Write Length */
0089 #define ISMT_DESC_BLK   0X04    /* Perform Block Transaction */
0090 #define ISMT_DESC_FAIR  0x08    /* Set fairness flag upon successful arbit. */
0091 #define ISMT_DESC_PEC   0x10    /* Packet Error Code */
0092 #define ISMT_DESC_I2C   0x20    /* I2C Enable */
0093 #define ISMT_DESC_INT   0x40    /* Interrupt */
0094 #define ISMT_DESC_SOE   0x80    /* Stop On Error */
0095 
0096 /* Hardware Descriptor Constants - Status Field */
0097 #define ISMT_DESC_SCS   0x01    /* Success */
0098 #define ISMT_DESC_DLTO  0x04    /* Data Low Time Out */
0099 #define ISMT_DESC_NAK   0x08    /* NAK Received */
0100 #define ISMT_DESC_CRC   0x10    /* CRC Error */
0101 #define ISMT_DESC_CLTO  0x20    /* Clock Low Time Out */
0102 #define ISMT_DESC_COL   0x40    /* Collisions */
0103 #define ISMT_DESC_LPR   0x80    /* Large Packet Received */
0104 
0105 /* Macros */
0106 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
0107 
0108 /* iSMT General Register address offsets (SMBBAR + <addr>) */
0109 #define ISMT_GR_GCTRL       0x000   /* General Control */
0110 #define ISMT_GR_SMTICL      0x008   /* SMT Interrupt Cause Location */
0111 #define ISMT_GR_ERRINTMSK   0x010   /* Error Interrupt Mask */
0112 #define ISMT_GR_ERRAERMSK   0x014   /* Error AER Mask */
0113 #define ISMT_GR_ERRSTS      0x018   /* Error Status */
0114 #define ISMT_GR_ERRINFO     0x01c   /* Error Information */
0115 
0116 /* iSMT Master Registers */
0117 #define ISMT_MSTR_MDBA      0x100   /* Master Descriptor Base Address */
0118 #define ISMT_MSTR_MCTRL     0x108   /* Master Control */
0119 #define ISMT_MSTR_MSTS      0x10c   /* Master Status */
0120 #define ISMT_MSTR_MDS       0x110   /* Master Descriptor Size */
0121 #define ISMT_MSTR_RPOLICY   0x114   /* Retry Policy */
0122 
0123 /* iSMT Miscellaneous Registers */
0124 #define ISMT_SPGT   0x300   /* SMBus PHY Global Timing */
0125 
0126 /* General Control Register (GCTRL) bit definitions */
0127 #define ISMT_GCTRL_TRST 0x04    /* Target Reset */
0128 #define ISMT_GCTRL_KILL 0x08    /* Kill */
0129 #define ISMT_GCTRL_SRST 0x40    /* Soft Reset */
0130 
0131 /* Master Control Register (MCTRL) bit definitions */
0132 #define ISMT_MCTRL_SS   0x01        /* Start/Stop */
0133 #define ISMT_MCTRL_MEIE 0x10        /* Master Error Interrupt Enable */
0134 #define ISMT_MCTRL_FMHP 0x00ff0000  /* Firmware Master Head Ptr (FMHP) */
0135 
0136 /* Master Status Register (MSTS) bit definitions */
0137 #define ISMT_MSTS_HMTP  0xff0000    /* HW Master Tail Pointer (HMTP) */
0138 #define ISMT_MSTS_MIS   0x20        /* Master Interrupt Status (MIS) */
0139 #define ISMT_MSTS_MEIS  0x10        /* Master Error Int Status (MEIS) */
0140 #define ISMT_MSTS_IP    0x01        /* In Progress */
0141 
0142 /* Master Descriptor Size (MDS) bit definitions */
0143 #define ISMT_MDS_MASK   0xff    /* Master Descriptor Size mask (MDS) */
0144 
0145 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
0146 #define ISMT_SPGT_SPD_MASK  0xc0000000  /* SMBus Speed mask */
0147 #define ISMT_SPGT_SPD_80K   0x00        /* 80 kHz */
0148 #define ISMT_SPGT_SPD_100K  (0x1 << 30) /* 100 kHz */
0149 #define ISMT_SPGT_SPD_400K  (0x2U << 30)    /* 400 kHz */
0150 #define ISMT_SPGT_SPD_1M    (0x3U << 30)    /* 1 MHz */
0151 
0152 
0153 /* MSI Control Register (MSICTL) bit definitions */
0154 #define ISMT_MSICTL_MSIE    0x01    /* MSI Enable */
0155 
0156 /* iSMT Hardware Descriptor */
0157 struct ismt_desc {
0158     u8 tgtaddr_rw;  /* target address & r/w bit */
0159     u8 wr_len_cmd;  /* write length in bytes or a command */
0160     u8 rd_len;  /* read length */
0161     u8 control; /* control bits */
0162     u8 status;  /* status bits */
0163     u8 retry;   /* collision retry and retry count */
0164     u8 rxbytes; /* received bytes */
0165     u8 txbytes; /* transmitted bytes */
0166     u32 dptr_low;   /* lower 32 bit of the data pointer */
0167     u32 dptr_high;  /* upper 32 bit of the data pointer */
0168 } __packed;
0169 
0170 struct ismt_priv {
0171     struct i2c_adapter adapter;
0172     void __iomem *smba;         /* PCI BAR */
0173     struct pci_dev *pci_dev;
0174     struct ismt_desc *hw;           /* descriptor virt base addr */
0175     dma_addr_t io_rng_dma;          /* descriptor HW base addr */
0176     u8 head;                /* ring buffer head pointer */
0177     struct completion cmp;          /* interrupt completion */
0178     u8 buffer[I2C_SMBUS_BLOCK_MAX + 16];    /* temp R/W data buffer */
0179     dma_addr_t log_dma;
0180     u32 *log;
0181 };
0182 
0183 static const struct pci_device_id ismt_ids[] = {
0184     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
0185     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
0186     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) },
0187     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) },
0188     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) },
0189     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
0190     { 0, }
0191 };
0192 
0193 MODULE_DEVICE_TABLE(pci, ismt_ids);
0194 
0195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
0196 static unsigned int bus_speed;
0197 module_param(bus_speed, uint, S_IRUGO);
0198 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
0199 
0200 /**
0201  * __ismt_desc_dump() - dump the contents of a specific descriptor
0202  * @dev: the iSMT device
0203  * @desc: the iSMT hardware descriptor
0204  */
0205 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
0206 {
0207 
0208     dev_dbg(dev, "Descriptor struct:  %p\n", desc);
0209     dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
0210     dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
0211     dev_dbg(dev, "\trd_len=    0x%02X\n", desc->rd_len);
0212     dev_dbg(dev, "\tcontrol=   0x%02X\n", desc->control);
0213     dev_dbg(dev, "\tstatus=    0x%02X\n", desc->status);
0214     dev_dbg(dev, "\tretry=     0x%02X\n", desc->retry);
0215     dev_dbg(dev, "\trxbytes=   0x%02X\n", desc->rxbytes);
0216     dev_dbg(dev, "\ttxbytes=   0x%02X\n", desc->txbytes);
0217     dev_dbg(dev, "\tdptr_low=  0x%08X\n", desc->dptr_low);
0218     dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
0219 }
0220 /**
0221  * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
0222  * @priv: iSMT private data
0223  */
0224 static void ismt_desc_dump(struct ismt_priv *priv)
0225 {
0226     struct device *dev = &priv->pci_dev->dev;
0227     struct ismt_desc *desc = &priv->hw[priv->head];
0228 
0229     dev_dbg(dev, "Dump of the descriptor struct:  0x%X\n", priv->head);
0230     __ismt_desc_dump(dev, desc);
0231 }
0232 
0233 /**
0234  * ismt_gen_reg_dump() - dump the iSMT General Registers
0235  * @priv: iSMT private data
0236  */
0237 static void ismt_gen_reg_dump(struct ismt_priv *priv)
0238 {
0239     struct device *dev = &priv->pci_dev->dev;
0240 
0241     dev_dbg(dev, "Dump of the iSMT General Registers\n");
0242     dev_dbg(dev, "  GCTRL.... : (0x%p)=0x%X\n",
0243         priv->smba + ISMT_GR_GCTRL,
0244         readl(priv->smba + ISMT_GR_GCTRL));
0245     dev_dbg(dev, "  SMTICL... : (0x%p)=0x%016llX\n",
0246         priv->smba + ISMT_GR_SMTICL,
0247         (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
0248     dev_dbg(dev, "  ERRINTMSK : (0x%p)=0x%X\n",
0249         priv->smba + ISMT_GR_ERRINTMSK,
0250         readl(priv->smba + ISMT_GR_ERRINTMSK));
0251     dev_dbg(dev, "  ERRAERMSK : (0x%p)=0x%X\n",
0252         priv->smba + ISMT_GR_ERRAERMSK,
0253         readl(priv->smba + ISMT_GR_ERRAERMSK));
0254     dev_dbg(dev, "  ERRSTS... : (0x%p)=0x%X\n",
0255         priv->smba + ISMT_GR_ERRSTS,
0256         readl(priv->smba + ISMT_GR_ERRSTS));
0257     dev_dbg(dev, "  ERRINFO.. : (0x%p)=0x%X\n",
0258         priv->smba + ISMT_GR_ERRINFO,
0259         readl(priv->smba + ISMT_GR_ERRINFO));
0260 }
0261 
0262 /**
0263  * ismt_mstr_reg_dump() - dump the iSMT Master Registers
0264  * @priv: iSMT private data
0265  */
0266 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
0267 {
0268     struct device *dev = &priv->pci_dev->dev;
0269 
0270     dev_dbg(dev, "Dump of the iSMT Master Registers\n");
0271     dev_dbg(dev, "  MDBA..... : (0x%p)=0x%016llX\n",
0272         priv->smba + ISMT_MSTR_MDBA,
0273         (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
0274     dev_dbg(dev, "  MCTRL.... : (0x%p)=0x%X\n",
0275         priv->smba + ISMT_MSTR_MCTRL,
0276         readl(priv->smba + ISMT_MSTR_MCTRL));
0277     dev_dbg(dev, "  MSTS..... : (0x%p)=0x%X\n",
0278         priv->smba + ISMT_MSTR_MSTS,
0279         readl(priv->smba + ISMT_MSTR_MSTS));
0280     dev_dbg(dev, "  MDS...... : (0x%p)=0x%X\n",
0281         priv->smba + ISMT_MSTR_MDS,
0282         readl(priv->smba + ISMT_MSTR_MDS));
0283     dev_dbg(dev, "  RPOLICY.. : (0x%p)=0x%X\n",
0284         priv->smba + ISMT_MSTR_RPOLICY,
0285         readl(priv->smba + ISMT_MSTR_RPOLICY));
0286     dev_dbg(dev, "  SPGT..... : (0x%p)=0x%X\n",
0287         priv->smba + ISMT_SPGT,
0288         readl(priv->smba + ISMT_SPGT));
0289 }
0290 
0291 /**
0292  * ismt_submit_desc() - add a descriptor to the ring
0293  * @priv: iSMT private data
0294  */
0295 static void ismt_submit_desc(struct ismt_priv *priv)
0296 {
0297     uint fmhp;
0298     uint val;
0299 
0300     ismt_desc_dump(priv);
0301     ismt_gen_reg_dump(priv);
0302     ismt_mstr_reg_dump(priv);
0303 
0304     /* Set the FMHP (Firmware Master Head Pointer)*/
0305     fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
0306     val = readl(priv->smba + ISMT_MSTR_MCTRL);
0307     writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
0308            priv->smba + ISMT_MSTR_MCTRL);
0309 
0310     /* Set the start bit */
0311     val = readl(priv->smba + ISMT_MSTR_MCTRL);
0312     writel(val | ISMT_MCTRL_SS,
0313            priv->smba + ISMT_MSTR_MCTRL);
0314 }
0315 
0316 /**
0317  * ismt_process_desc() - handle the completion of the descriptor
0318  * @desc: the iSMT hardware descriptor
0319  * @data: data buffer from the upper layer
0320  * @priv: ismt_priv struct holding our dma buffer
0321  * @size: SMBus transaction type
0322  * @read_write: flag to indicate if this is a read or write
0323  */
0324 static int ismt_process_desc(const struct ismt_desc *desc,
0325                  union i2c_smbus_data *data,
0326                  struct ismt_priv *priv, int size,
0327                  char read_write)
0328 {
0329     u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
0330 
0331     dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
0332     __ismt_desc_dump(&priv->pci_dev->dev, desc);
0333     ismt_gen_reg_dump(priv);
0334     ismt_mstr_reg_dump(priv);
0335 
0336     if (desc->status & ISMT_DESC_SCS) {
0337         if (read_write == I2C_SMBUS_WRITE &&
0338             size != I2C_SMBUS_PROC_CALL &&
0339             size != I2C_SMBUS_BLOCK_PROC_CALL)
0340             return 0;
0341 
0342         switch (size) {
0343         case I2C_SMBUS_BYTE:
0344         case I2C_SMBUS_BYTE_DATA:
0345             data->byte = dma_buffer[0];
0346             break;
0347         case I2C_SMBUS_WORD_DATA:
0348         case I2C_SMBUS_PROC_CALL:
0349             data->word = dma_buffer[0] | (dma_buffer[1] << 8);
0350             break;
0351         case I2C_SMBUS_BLOCK_DATA:
0352         case I2C_SMBUS_BLOCK_PROC_CALL:
0353             if (desc->rxbytes != dma_buffer[0] + 1)
0354                 return -EMSGSIZE;
0355 
0356             memcpy(data->block, dma_buffer, desc->rxbytes);
0357             break;
0358         case I2C_SMBUS_I2C_BLOCK_DATA:
0359             memcpy(&data->block[1], dma_buffer, desc->rxbytes);
0360             data->block[0] = desc->rxbytes;
0361             break;
0362         }
0363         return 0;
0364     }
0365 
0366     if (likely(desc->status & ISMT_DESC_NAK))
0367         return -ENXIO;
0368 
0369     if (desc->status & ISMT_DESC_CRC)
0370         return -EBADMSG;
0371 
0372     if (desc->status & ISMT_DESC_COL)
0373         return -EAGAIN;
0374 
0375     if (desc->status & ISMT_DESC_LPR)
0376         return -EPROTO;
0377 
0378     if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
0379         return -ETIMEDOUT;
0380 
0381     return -EIO;
0382 }
0383 
0384 /**
0385  * ismt_access() - process an SMBus command
0386  * @adap: the i2c host adapter
0387  * @addr: address of the i2c/SMBus target
0388  * @flags: command options
0389  * @read_write: read from or write to device
0390  * @command: the i2c/SMBus command to issue
0391  * @size: SMBus transaction type
0392  * @data: read/write data buffer
0393  */
0394 static int ismt_access(struct i2c_adapter *adap, u16 addr,
0395                unsigned short flags, char read_write, u8 command,
0396                int size, union i2c_smbus_data *data)
0397 {
0398     int ret;
0399     unsigned long time_left;
0400     dma_addr_t dma_addr = 0; /* address of the data buffer */
0401     u8 dma_size = 0;
0402     enum dma_data_direction dma_direction = 0;
0403     struct ismt_desc *desc;
0404     struct ismt_priv *priv = i2c_get_adapdata(adap);
0405     struct device *dev = &priv->pci_dev->dev;
0406     u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16);
0407 
0408     desc = &priv->hw[priv->head];
0409 
0410     /* Initialize the DMA buffer */
0411     memset(priv->buffer, 0, sizeof(priv->buffer));
0412 
0413     /* Initialize the descriptor */
0414     memset(desc, 0, sizeof(struct ismt_desc));
0415     desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
0416 
0417     /* Always clear the log entries */
0418     memset(priv->log, 0, ISMT_LOG_ENTRIES * sizeof(u32));
0419 
0420     /* Initialize common control bits */
0421     if (likely(pci_dev_msi_enabled(priv->pci_dev)))
0422         desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
0423     else
0424         desc->control = ISMT_DESC_FAIR;
0425 
0426     if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
0427         && (size != I2C_SMBUS_I2C_BLOCK_DATA))
0428         desc->control |= ISMT_DESC_PEC;
0429 
0430     switch (size) {
0431     case I2C_SMBUS_QUICK:
0432         dev_dbg(dev, "I2C_SMBUS_QUICK\n");
0433         break;
0434 
0435     case I2C_SMBUS_BYTE:
0436         if (read_write == I2C_SMBUS_WRITE) {
0437             /*
0438              * Send Byte
0439              * The command field contains the write data
0440              */
0441             dev_dbg(dev, "I2C_SMBUS_BYTE:  WRITE\n");
0442             desc->control |= ISMT_DESC_CWRL;
0443             desc->wr_len_cmd = command;
0444         } else {
0445             /* Receive Byte */
0446             dev_dbg(dev, "I2C_SMBUS_BYTE:  READ\n");
0447             dma_size = 1;
0448             dma_direction = DMA_FROM_DEVICE;
0449             desc->rd_len = 1;
0450         }
0451         break;
0452 
0453     case I2C_SMBUS_BYTE_DATA:
0454         if (read_write == I2C_SMBUS_WRITE) {
0455             /*
0456              * Write Byte
0457              * Command plus 1 data byte
0458              */
0459             dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  WRITE\n");
0460             desc->wr_len_cmd = 2;
0461             dma_size = 2;
0462             dma_direction = DMA_TO_DEVICE;
0463             dma_buffer[0] = command;
0464             dma_buffer[1] = data->byte;
0465         } else {
0466             /* Read Byte */
0467             dev_dbg(dev, "I2C_SMBUS_BYTE_DATA:  READ\n");
0468             desc->control |= ISMT_DESC_CWRL;
0469             desc->wr_len_cmd = command;
0470             desc->rd_len = 1;
0471             dma_size = 1;
0472             dma_direction = DMA_FROM_DEVICE;
0473         }
0474         break;
0475 
0476     case I2C_SMBUS_WORD_DATA:
0477         if (read_write == I2C_SMBUS_WRITE) {
0478             /* Write Word */
0479             dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  WRITE\n");
0480             desc->wr_len_cmd = 3;
0481             dma_size = 3;
0482             dma_direction = DMA_TO_DEVICE;
0483             dma_buffer[0] = command;
0484             dma_buffer[1] = data->word & 0xff;
0485             dma_buffer[2] = data->word >> 8;
0486         } else {
0487             /* Read Word */
0488             dev_dbg(dev, "I2C_SMBUS_WORD_DATA:  READ\n");
0489             desc->wr_len_cmd = command;
0490             desc->control |= ISMT_DESC_CWRL;
0491             desc->rd_len = 2;
0492             dma_size = 2;
0493             dma_direction = DMA_FROM_DEVICE;
0494         }
0495         break;
0496 
0497     case I2C_SMBUS_PROC_CALL:
0498         dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
0499         desc->wr_len_cmd = 3;
0500         desc->rd_len = 2;
0501         dma_size = 3;
0502         dma_direction = DMA_BIDIRECTIONAL;
0503         dma_buffer[0] = command;
0504         dma_buffer[1] = data->word & 0xff;
0505         dma_buffer[2] = data->word >> 8;
0506         break;
0507 
0508     case I2C_SMBUS_BLOCK_DATA:
0509         if (read_write == I2C_SMBUS_WRITE) {
0510             /* Block Write */
0511             dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  WRITE\n");
0512             dma_size = data->block[0] + 1;
0513             dma_direction = DMA_TO_DEVICE;
0514             desc->wr_len_cmd = dma_size;
0515             desc->control |= ISMT_DESC_BLK;
0516             dma_buffer[0] = command;
0517             memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
0518         } else {
0519             /* Block Read */
0520             dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA:  READ\n");
0521             dma_size = I2C_SMBUS_BLOCK_MAX;
0522             dma_direction = DMA_FROM_DEVICE;
0523             desc->rd_len = dma_size;
0524             desc->wr_len_cmd = command;
0525             desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
0526         }
0527         break;
0528 
0529     case I2C_SMBUS_BLOCK_PROC_CALL:
0530         dev_dbg(dev, "I2C_SMBUS_BLOCK_PROC_CALL\n");
0531         if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
0532             return -EINVAL;
0533 
0534         dma_size = I2C_SMBUS_BLOCK_MAX;
0535         desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 1);
0536         desc->wr_len_cmd = data->block[0] + 1;
0537         desc->rd_len = dma_size;
0538         desc->control |= ISMT_DESC_BLK;
0539         dma_direction = DMA_BIDIRECTIONAL;
0540         dma_buffer[0] = command;
0541         memcpy(&dma_buffer[1], &data->block[1], data->block[0]);
0542         break;
0543 
0544     case I2C_SMBUS_I2C_BLOCK_DATA:
0545         /* Make sure the length is valid */
0546         if (data->block[0] < 1)
0547             data->block[0] = 1;
0548 
0549         if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
0550             data->block[0] = I2C_SMBUS_BLOCK_MAX;
0551 
0552         if (read_write == I2C_SMBUS_WRITE) {
0553             /* i2c Block Write */
0554             dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  WRITE\n");
0555             dma_size = data->block[0] + 1;
0556             dma_direction = DMA_TO_DEVICE;
0557             desc->wr_len_cmd = dma_size;
0558             desc->control |= ISMT_DESC_I2C;
0559             dma_buffer[0] = command;
0560             memcpy(&dma_buffer[1], &data->block[1], dma_size - 1);
0561         } else {
0562             /* i2c Block Read */
0563             dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA:  READ\n");
0564             dma_size = data->block[0];
0565             dma_direction = DMA_FROM_DEVICE;
0566             desc->rd_len = dma_size;
0567             desc->wr_len_cmd = command;
0568             desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
0569             /*
0570              * Per the "Table 15-15. I2C Commands",
0571              * in the External Design Specification (EDS),
0572              * (Document Number: 508084, Revision: 2.0),
0573              * the _rw bit must be 0
0574              */
0575             desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
0576         }
0577         break;
0578 
0579     default:
0580         dev_err(dev, "Unsupported transaction %d\n",
0581             size);
0582         return -EOPNOTSUPP;
0583     }
0584 
0585     /* map the data buffer */
0586     if (dma_size != 0) {
0587         dev_dbg(dev, " dev=%p\n", dev);
0588         dev_dbg(dev, " data=%p\n", data);
0589         dev_dbg(dev, " dma_buffer=%p\n", dma_buffer);
0590         dev_dbg(dev, " dma_size=%d\n", dma_size);
0591         dev_dbg(dev, " dma_direction=%d\n", dma_direction);
0592 
0593         dma_addr = dma_map_single(dev,
0594                       dma_buffer,
0595                       dma_size,
0596                       dma_direction);
0597 
0598         if (dma_mapping_error(dev, dma_addr)) {
0599             dev_err(dev, "Error in mapping dma buffer %p\n",
0600                 dma_buffer);
0601             return -EIO;
0602         }
0603 
0604         dev_dbg(dev, " dma_addr = %pad\n", &dma_addr);
0605 
0606         desc->dptr_low = lower_32_bits(dma_addr);
0607         desc->dptr_high = upper_32_bits(dma_addr);
0608     }
0609 
0610     reinit_completion(&priv->cmp);
0611 
0612     /* Add the descriptor */
0613     ismt_submit_desc(priv);
0614 
0615     /* Now we wait for interrupt completion, 1s */
0616     time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
0617 
0618     /* unmap the data buffer */
0619     if (dma_size != 0)
0620         dma_unmap_single(dev, dma_addr, dma_size, dma_direction);
0621 
0622     if (unlikely(!time_left)) {
0623         dev_err(dev, "completion wait timed out\n");
0624         ret = -ETIMEDOUT;
0625         goto out;
0626     }
0627 
0628     /* do any post processing of the descriptor here */
0629     ret = ismt_process_desc(desc, data, priv, size, read_write);
0630 
0631 out:
0632     /* Update the ring pointer */
0633     priv->head++;
0634     priv->head %= ISMT_DESC_ENTRIES;
0635 
0636     return ret;
0637 }
0638 
0639 /**
0640  * ismt_func() - report which i2c commands are supported by this adapter
0641  * @adap: the i2c host adapter
0642  */
0643 static u32 ismt_func(struct i2c_adapter *adap)
0644 {
0645     return I2C_FUNC_SMBUS_QUICK     |
0646            I2C_FUNC_SMBUS_BYTE      |
0647            I2C_FUNC_SMBUS_BYTE_DATA     |
0648            I2C_FUNC_SMBUS_WORD_DATA     |
0649            I2C_FUNC_SMBUS_PROC_CALL     |
0650            I2C_FUNC_SMBUS_BLOCK_PROC_CALL   |
0651            I2C_FUNC_SMBUS_BLOCK_DATA    |
0652            I2C_FUNC_SMBUS_I2C_BLOCK     |
0653            I2C_FUNC_SMBUS_PEC;
0654 }
0655 
0656 static const struct i2c_algorithm smbus_algorithm = {
0657     .smbus_xfer = ismt_access,
0658     .functionality  = ismt_func,
0659 };
0660 
0661 /**
0662  * ismt_handle_isr() - interrupt handler bottom half
0663  * @priv: iSMT private data
0664  */
0665 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
0666 {
0667     complete(&priv->cmp);
0668 
0669     return IRQ_HANDLED;
0670 }
0671 
0672 
0673 /**
0674  * ismt_do_interrupt() - IRQ interrupt handler
0675  * @vec: interrupt vector
0676  * @data: iSMT private data
0677  */
0678 static irqreturn_t ismt_do_interrupt(int vec, void *data)
0679 {
0680     u32 val;
0681     struct ismt_priv *priv = data;
0682 
0683     /*
0684      * check to see it's our interrupt, return IRQ_NONE if not ours
0685      * since we are sharing interrupt
0686      */
0687     val = readl(priv->smba + ISMT_MSTR_MSTS);
0688 
0689     if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
0690         return IRQ_NONE;
0691     else
0692         writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
0693                priv->smba + ISMT_MSTR_MSTS);
0694 
0695     return ismt_handle_isr(priv);
0696 }
0697 
0698 /**
0699  * ismt_do_msi_interrupt() - MSI interrupt handler
0700  * @vec: interrupt vector
0701  * @data: iSMT private data
0702  */
0703 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
0704 {
0705     return ismt_handle_isr(data);
0706 }
0707 
0708 /**
0709  * ismt_hw_init() - initialize the iSMT hardware
0710  * @priv: iSMT private data
0711  */
0712 static void ismt_hw_init(struct ismt_priv *priv)
0713 {
0714     u32 val;
0715     struct device *dev = &priv->pci_dev->dev;
0716 
0717     /* initialize the Master Descriptor Base Address (MDBA) */
0718     writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
0719 
0720     writeq(priv->log_dma, priv->smba + ISMT_GR_SMTICL);
0721 
0722     /* initialize the Master Control Register (MCTRL) */
0723     writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
0724 
0725     /* initialize the Master Status Register (MSTS) */
0726     writel(0, priv->smba + ISMT_MSTR_MSTS);
0727 
0728     /* initialize the Master Descriptor Size (MDS) */
0729     val = readl(priv->smba + ISMT_MSTR_MDS);
0730     writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
0731         priv->smba + ISMT_MSTR_MDS);
0732 
0733     /*
0734      * Set the SMBus speed (could use this for slow HW debuggers)
0735      */
0736 
0737     val = readl(priv->smba + ISMT_SPGT);
0738 
0739     switch (bus_speed) {
0740     case 0:
0741         break;
0742 
0743     case 80:
0744         dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
0745         writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
0746             priv->smba + ISMT_SPGT);
0747         break;
0748 
0749     case 100:
0750         dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
0751         writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
0752             priv->smba + ISMT_SPGT);
0753         break;
0754 
0755     case 400:
0756         dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
0757         writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
0758             priv->smba + ISMT_SPGT);
0759         break;
0760 
0761     case 1000:
0762         dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
0763         writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
0764             priv->smba + ISMT_SPGT);
0765         break;
0766 
0767     default:
0768         dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
0769         break;
0770     }
0771 
0772     val = readl(priv->smba + ISMT_SPGT);
0773 
0774     switch (val & ISMT_SPGT_SPD_MASK) {
0775     case ISMT_SPGT_SPD_80K:
0776         bus_speed = 80;
0777         break;
0778     case ISMT_SPGT_SPD_100K:
0779         bus_speed = 100;
0780         break;
0781     case ISMT_SPGT_SPD_400K:
0782         bus_speed = 400;
0783         break;
0784     case ISMT_SPGT_SPD_1M:
0785         bus_speed = 1000;
0786         break;
0787     }
0788     dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
0789 }
0790 
0791 /**
0792  * ismt_dev_init() - initialize the iSMT data structures
0793  * @priv: iSMT private data
0794  */
0795 static int ismt_dev_init(struct ismt_priv *priv)
0796 {
0797     /* allocate memory for the descriptor */
0798     priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
0799                        (ISMT_DESC_ENTRIES
0800                            * sizeof(struct ismt_desc)),
0801                        &priv->io_rng_dma,
0802                        GFP_KERNEL);
0803     if (!priv->hw)
0804         return -ENOMEM;
0805 
0806     priv->head = 0;
0807     init_completion(&priv->cmp);
0808 
0809     priv->log = dmam_alloc_coherent(&priv->pci_dev->dev,
0810                     ISMT_LOG_ENTRIES * sizeof(u32),
0811                     &priv->log_dma, GFP_KERNEL);
0812     if (!priv->log)
0813         return -ENOMEM;
0814 
0815     return 0;
0816 }
0817 
0818 /**
0819  * ismt_int_init() - initialize interrupts
0820  * @priv: iSMT private data
0821  */
0822 static int ismt_int_init(struct ismt_priv *priv)
0823 {
0824     int err;
0825 
0826     /* Try using MSI interrupts */
0827     err = pci_enable_msi(priv->pci_dev);
0828     if (err)
0829         goto intx;
0830 
0831     err = devm_request_irq(&priv->pci_dev->dev,
0832                    priv->pci_dev->irq,
0833                    ismt_do_msi_interrupt,
0834                    0,
0835                    "ismt-msi",
0836                    priv);
0837     if (err) {
0838         pci_disable_msi(priv->pci_dev);
0839         goto intx;
0840     }
0841 
0842     return 0;
0843 
0844     /* Try using legacy interrupts */
0845 intx:
0846     dev_warn(&priv->pci_dev->dev,
0847          "Unable to use MSI interrupts, falling back to legacy\n");
0848 
0849     err = devm_request_irq(&priv->pci_dev->dev,
0850                    priv->pci_dev->irq,
0851                    ismt_do_interrupt,
0852                    IRQF_SHARED,
0853                    "ismt-intx",
0854                    priv);
0855     if (err) {
0856         dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
0857         return err;
0858     }
0859 
0860     return 0;
0861 }
0862 
0863 static struct pci_driver ismt_driver;
0864 
0865 /**
0866  * ismt_probe() - probe for iSMT devices
0867  * @pdev: PCI-Express device
0868  * @id: PCI-Express device ID
0869  */
0870 static int
0871 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
0872 {
0873     int err;
0874     struct ismt_priv *priv;
0875     unsigned long start, len;
0876 
0877     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0878     if (!priv)
0879         return -ENOMEM;
0880 
0881     pci_set_drvdata(pdev, priv);
0882 
0883     i2c_set_adapdata(&priv->adapter, priv);
0884     priv->adapter.owner = THIS_MODULE;
0885     priv->adapter.class = I2C_CLASS_HWMON;
0886     priv->adapter.algo = &smbus_algorithm;
0887     priv->adapter.dev.parent = &pdev->dev;
0888     ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
0889     priv->adapter.retries = ISMT_MAX_RETRIES;
0890 
0891     priv->pci_dev = pdev;
0892 
0893     err = pcim_enable_device(pdev);
0894     if (err) {
0895         dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
0896             err);
0897         return err;
0898     }
0899 
0900     /* enable bus mastering */
0901     pci_set_master(pdev);
0902 
0903     /* Determine the address of the SMBus area */
0904     start = pci_resource_start(pdev, SMBBAR);
0905     len = pci_resource_len(pdev, SMBBAR);
0906     if (!start || !len) {
0907         dev_err(&pdev->dev,
0908             "SMBus base address uninitialized, upgrade BIOS\n");
0909         return -ENODEV;
0910     }
0911 
0912     snprintf(priv->adapter.name, sizeof(priv->adapter.name),
0913          "SMBus iSMT adapter at %lx", start);
0914 
0915     dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
0916     dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
0917 
0918     err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
0919     if (err) {
0920         dev_err(&pdev->dev, "ACPI resource conflict!\n");
0921         return err;
0922     }
0923 
0924     err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
0925     if (err) {
0926         dev_err(&pdev->dev,
0927             "Failed to request SMBus region 0x%lx-0x%lx\n",
0928             start, start + len);
0929         return err;
0930     }
0931 
0932     priv->smba = pcim_iomap(pdev, SMBBAR, len);
0933     if (!priv->smba) {
0934         dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
0935         return -ENODEV;
0936     }
0937 
0938     err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
0939     if (err) {
0940         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
0941         if (err) {
0942             dev_err(&pdev->dev, "dma_set_mask fail\n");
0943             return -ENODEV;
0944         }
0945     }
0946 
0947     err = ismt_dev_init(priv);
0948     if (err)
0949         return err;
0950 
0951     ismt_hw_init(priv);
0952 
0953     err = ismt_int_init(priv);
0954     if (err)
0955         return err;
0956 
0957     err = i2c_add_adapter(&priv->adapter);
0958     if (err)
0959         return -ENODEV;
0960     return 0;
0961 }
0962 
0963 /**
0964  * ismt_remove() - release driver resources
0965  * @pdev: PCI-Express device
0966  */
0967 static void ismt_remove(struct pci_dev *pdev)
0968 {
0969     struct ismt_priv *priv = pci_get_drvdata(pdev);
0970 
0971     i2c_del_adapter(&priv->adapter);
0972 }
0973 
0974 static struct pci_driver ismt_driver = {
0975     .name = "ismt_smbus",
0976     .id_table = ismt_ids,
0977     .probe = ismt_probe,
0978     .remove = ismt_remove,
0979 };
0980 
0981 module_pci_driver(ismt_driver);
0982 
0983 MODULE_LICENSE("Dual BSD/GPL");
0984 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
0985 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");
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