i2c/busses/i2c-isch.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003     i2c-isch.c - Linux kernel driver for Intel SCH chipset SMBus
0004     - Based on i2c-piix4.c
0005     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
0006     Philip Edelbrock <phil@netroedge.com>
0007     - Intel SCH support
0008     Copyright (c) 2007 - 2008 Jacob Jun Pan <jacob.jun.pan@intel.com>
0009
0010 */
0011
0012 /*
0013    Supports:
0014     Intel SCH chipsets (AF82US15W, AF82US15L, AF82UL11L)
0015    Note: we assume there can only be one device, with one SMBus interface.
0016 */
0017
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/kernel.h>
0021 #include <linux/delay.h>
0022 #include <linux/stddef.h>
0023 #include <linux/ioport.h>
0024 #include <linux/i2c.h>
0025 #include <linux/io.h>
0026
0027 /* SCH SMBus address offsets */
0028 #define SMBHSTCNT   (0 + sch_smba)
0029 #define SMBHSTSTS   (1 + sch_smba)
0030 #define SMBHSTCLK   (2 + sch_smba)
0031 #define SMBHSTADD   (4 + sch_smba) /* TSA */
0032 #define SMBHSTCMD   (5 + sch_smba)
0033 #define SMBHSTDAT0  (6 + sch_smba)
0034 #define SMBHSTDAT1  (7 + sch_smba)
0035 #define SMBBLKDAT   (0x20 + sch_smba)
0036
0037 /* Other settings */
0038 #define MAX_RETRIES 5000
0039
0040 /* I2C constants */
0041 #define SCH_QUICK       0x00
0042 #define SCH_BYTE        0x01
0043 #define SCH_BYTE_DATA       0x02
0044 #define SCH_WORD_DATA       0x03
0045 #define SCH_BLOCK_DATA      0x05
0046
0047 static unsigned short sch_smba;
0048 static struct i2c_adapter sch_adapter;
0049 static int backbone_speed = 33000; /* backbone speed in kHz */
0050 module_param(backbone_speed, int, S_IRUSR | S_IWUSR);
0051 MODULE_PARM_DESC(backbone_speed, "Backbone speed in kHz, (default = 33000)");
0052
0053 /*
0054  * Start the i2c transaction -- the i2c_access will prepare the transaction
0055  * and this function will execute it.
0056  * return 0 for success and others for failure.
0057  */
0058 static int sch_transaction(void)
0059 {
0060     int temp;
0061     int result = 0;
0062     int retries = 0;
0063
0064     dev_dbg(&sch_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
0065         "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
0066         inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
0067         inb(SMBHSTDAT1));
0068
0069     /* Make sure the SMBus host is ready to start transmitting */
0070     temp = inb(SMBHSTSTS) & 0x0f;
0071     if (temp) {
0072         /* Can not be busy since we checked it in sch_access */
0073         if (temp & 0x01) {
0074             dev_dbg(&sch_adapter.dev, "Completion (%02x). "
0075                 "Clear...\n", temp);
0076         }
0077         if (temp & 0x06) {
0078             dev_dbg(&sch_adapter.dev, "SMBus error (%02x). "
0079                 "Resetting...\n", temp);
0080         }
0081         outb(temp, SMBHSTSTS);
0082         temp = inb(SMBHSTSTS) & 0x0f;
0083         if (temp) {
0084             dev_err(&sch_adapter.dev,
0085                 "SMBus is not ready: (%02x)\n", temp);
0086             return -EAGAIN;
0087         }
0088     }
0089
0090     /* start the transaction by setting bit 4 */
0091     outb(inb(SMBHSTCNT) | 0x10, SMBHSTCNT);
0092
0093     do {
0094         usleep_range(100, 200);
0095         temp = inb(SMBHSTSTS) & 0x0f;
0096     } while ((temp & 0x08) && (retries++ < MAX_RETRIES));
0097
0098     /* If the SMBus is still busy, we give up */
0099     if (retries > MAX_RETRIES) {
0100         dev_err(&sch_adapter.dev, "SMBus Timeout!\n");
0101         result = -ETIMEDOUT;
0102     }
0103     if (temp & 0x04) {
0104         result = -EIO;
0105         dev_dbg(&sch_adapter.dev, "Bus collision! SMBus may be "
0106             "locked until next hard reset. (sorry!)\n");
0107         /* Clock stops and slave is stuck in mid-transmission */
0108     } else if (temp & 0x02) {
0109         result = -EIO;
0110         dev_err(&sch_adapter.dev, "Error: no response!\n");
0111     } else if (temp & 0x01) {
0112         dev_dbg(&sch_adapter.dev, "Post complete!\n");
0113         outb(temp, SMBHSTSTS);
0114         temp = inb(SMBHSTSTS) & 0x07;
0115         if (temp & 0x06) {
0116             /* Completion clear failed */
0117             dev_dbg(&sch_adapter.dev, "Failed reset at end of "
0118                 "transaction (%02x), Bus error!\n", temp);
0119         }
0120     } else {
0121         result = -ENXIO;
0122         dev_dbg(&sch_adapter.dev, "No such address.\n");
0123     }
0124     dev_dbg(&sch_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
0125         "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb(SMBHSTCNT),
0126         inb(SMBHSTCMD), inb(SMBHSTADD), inb(SMBHSTDAT0),
0127         inb(SMBHSTDAT1));
0128     return result;
0129 }
0130
0131 /*
0132  * This is the main access entry for i2c-sch access
0133  * adap is i2c_adapter pointer, addr is the i2c device bus address, read_write
0134  * (0 for read and 1 for write), size is i2c transaction type and data is the
0135  * union of transaction for data to be transferred or data read from bus.
0136  * return 0 for success and others for failure.
0137  */
0138 static s32 sch_access(struct i2c_adapter *adap, u16 addr,
0139          unsigned short flags, char read_write,
0140          u8 command, int size, union i2c_smbus_data *data)
0141 {
0142     int i, len, temp, rc;
0143
0144     /* Make sure the SMBus host is not busy */
0145     temp = inb(SMBHSTSTS) & 0x0f;
0146     if (temp & 0x08) {
0147         dev_dbg(&sch_adapter.dev, "SMBus busy (%02x)\n", temp);
0148         return -EAGAIN;
0149     }
0150     temp = inw(SMBHSTCLK);
0151     if (!temp) {
0152         /*
0153          * We can't determine if we have 33 or 25 MHz clock for
0154          * SMBus, so expect 33 MHz and calculate a bus clock of
0155          * 100 kHz. If we actually run at 25 MHz the bus will be
0156          * run ~75 kHz instead which should do no harm.
0157          */
0158         dev_notice(&sch_adapter.dev,
0159             "Clock divider uninitialized. Setting defaults\n");
0160         outw(backbone_speed / (4 * 100), SMBHSTCLK);
0161     }
0162
0163     dev_dbg(&sch_adapter.dev, "access size: %d %s\n", size,
0164         (read_write)?"READ":"WRITE");
0165     switch (size) {
0166     case I2C_SMBUS_QUICK:
0167         outb((addr << 1) | read_write, SMBHSTADD);
0168         size = SCH_QUICK;
0169         break;
0170     case I2C_SMBUS_BYTE:
0171         outb((addr << 1) | read_write, SMBHSTADD);
0172         if (read_write == I2C_SMBUS_WRITE)
0173             outb(command, SMBHSTCMD);
0174         size = SCH_BYTE;
0175         break;
0176     case I2C_SMBUS_BYTE_DATA:
0177         outb((addr << 1) | read_write, SMBHSTADD);
0178         outb(command, SMBHSTCMD);
0179         if (read_write == I2C_SMBUS_WRITE)
0180             outb(data->byte, SMBHSTDAT0);
0181         size = SCH_BYTE_DATA;
0182         break;
0183     case I2C_SMBUS_WORD_DATA:
0184         outb((addr << 1) | read_write, SMBHSTADD);
0185         outb(command, SMBHSTCMD);
0186         if (read_write == I2C_SMBUS_WRITE) {
0187             outb(data->word & 0xff, SMBHSTDAT0);
0188             outb((data->word & 0xff00) >> 8, SMBHSTDAT1);
0189         }
0190         size = SCH_WORD_DATA;
0191         break;
0192     case I2C_SMBUS_BLOCK_DATA:
0193         outb((addr << 1) | read_write, SMBHSTADD);
0194         outb(command, SMBHSTCMD);
0195         if (read_write == I2C_SMBUS_WRITE) {
0196             len = data->block[0];
0197             if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
0198                 return -EINVAL;
0199             outb(len, SMBHSTDAT0);
0200             for (i = 1; i <= len; i++)
0201                 outb(data->block[i], SMBBLKDAT+i-1);
0202         }
0203         size = SCH_BLOCK_DATA;
0204         break;
0205     default:
0206         dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
0207         return -EOPNOTSUPP;
0208     }
0209     dev_dbg(&sch_adapter.dev, "write size %d to 0x%04x\n", size, SMBHSTCNT);
0210     outb((inb(SMBHSTCNT) & 0xb0) | (size & 0x7), SMBHSTCNT);
0211
0212     rc = sch_transaction();
0213     if (rc) /* Error in transaction */
0214         return rc;
0215
0216     if ((read_write == I2C_SMBUS_WRITE) || (size == SCH_QUICK))
0217         return 0;
0218
0219     switch (size) {
0220     case SCH_BYTE:
0221     case SCH_BYTE_DATA:
0222         data->byte = inb(SMBHSTDAT0);
0223         break;
0224     case SCH_WORD_DATA:
0225         data->word = inb(SMBHSTDAT0) + (inb(SMBHSTDAT1) << 8);
0226         break;
0227     case SCH_BLOCK_DATA:
0228         data->block[0] = inb(SMBHSTDAT0);
0229         if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
0230             return -EPROTO;
0231         for (i = 1; i <= data->block[0]; i++)
0232             data->block[i] = inb(SMBBLKDAT+i-1);
0233         break;
0234     }
0235     return 0;
0236 }
0237
0238 static u32 sch_func(struct i2c_adapter *adapter)
0239 {
0240     return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
0241         I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
0242         I2C_FUNC_SMBUS_BLOCK_DATA;
0243 }
0244
0245 static const struct i2c_algorithm smbus_algorithm = {
0246     .smbus_xfer = sch_access,
0247     .functionality  = sch_func,
0248 };
0249
0250 static struct i2c_adapter sch_adapter = {
0251     .owner      = THIS_MODULE,
0252     .class      = I2C_CLASS_HWMON | I2C_CLASS_SPD,
0253     .algo       = &smbus_algorithm,
0254 };
0255
0256 static int smbus_sch_probe(struct platform_device *dev)
0257 {
0258     struct resource *res;
0259     int retval;
0260
0261     res = platform_get_resource(dev, IORESOURCE_IO, 0);
0262     if (!res)
0263         return -EBUSY;
0264
0265     if (!devm_request_region(&dev->dev, res->start, resource_size(res),
0266                  dev->name)) {
0267         dev_err(&dev->dev, "SMBus region 0x%x already in use!\n",
0268             sch_smba);
0269         return -EBUSY;
0270     }
0271
0272     sch_smba = res->start;
0273
0274     dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba);
0275
0276     /* set up the sysfs linkage to our parent device */
0277     sch_adapter.dev.parent = &dev->dev;
0278
0279     snprintf(sch_adapter.name, sizeof(sch_adapter.name),
0280         "SMBus SCH adapter at %04x", sch_smba);
0281
0282     retval = i2c_add_adapter(&sch_adapter);
0283     if (retval)
0284         sch_smba = 0;
0285
0286     return retval;
0287 }
0288
0289 static int smbus_sch_remove(struct platform_device *pdev)
0290 {
0291     if (sch_smba) {
0292         i2c_del_adapter(&sch_adapter);
0293         sch_smba = 0;
0294     }
0295
0296     return 0;
0297 }
0298
0299 static struct platform_driver smbus_sch_driver = {
0300     .driver = {
0301         .name = "isch_smbus",
0302     },
0303     .probe      = smbus_sch_probe,
0304     .remove     = smbus_sch_remove,
0305 };
0306
0307 module_platform_driver(smbus_sch_driver);
0308
0309 MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
0310 MODULE_DESCRIPTION("Intel SCH SMBus driver");
0311 MODULE_LICENSE("GPL");
0312 MODULE_ALIAS("platform:isch_smbus");