i2c/busses/i2c-iop3xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* ------------------------------------------------------------------------- */
0003 /* i2c-iop3xx.h algorithm driver definitions private to i2c-iop3xx.c         */
0004 /* ------------------------------------------------------------------------- */
0005 /*   Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
0006  *                      <Peter dot Milne at D hyphen TACQ dot com>
0007
0008  */
0009 /* ------------------------------------------------------------------------- */
0010
0011
0012 #ifndef I2C_IOP3XX_H
0013 #define I2C_IOP3XX_H 1
0014
0015 /*
0016  * iop321 hardware bit definitions
0017  */
0018 #define IOP3XX_ICR_FAST_MODE    0x8000  /* 1=400kBps, 0=100kBps */
0019 #define IOP3XX_ICR_UNIT_RESET   0x4000  /* 1=RESET */
0020 #define IOP3XX_ICR_SAD_IE   0x2000  /* 1=Slave Detect Interrupt Enable */
0021 #define IOP3XX_ICR_ALD_IE   0x1000  /* 1=Arb Loss Detect Interrupt Enable */
0022 #define IOP3XX_ICR_SSD_IE   0x0800  /* 1=Slave STOP Detect Interrupt Enable */
0023 #define IOP3XX_ICR_BERR_IE  0x0400  /* 1=Bus Error Interrupt Enable */
0024 #define IOP3XX_ICR_RXFULL_IE    0x0200  /* 1=Receive Full Interrupt Enable */
0025 #define IOP3XX_ICR_TXEMPTY_IE   0x0100  /* 1=Transmit Empty Interrupt Enable */
0026 #define IOP3XX_ICR_GCD      0x0080  /* 1=General Call Disable */
0027 /*
0028  * IOP3XX_ICR_GCD: 1 disables response as slave. "This bit must be set
0029  * when sending a master mode general call message from the I2C unit"
0030  */
0031 #define IOP3XX_ICR_UE       0x0040  /* 1=Unit Enable */
0032 /*
0033  * "NOTE: To avoid I2C bus integrity problems,
0034  * the user needs to ensure that the GPIO Output Data Register -
0035  * GPOD bits associated with an I2C port are cleared prior to setting
0036  * the enable bit for that I2C serial port.
0037  * The user prepares to enable I2C port 0 and
0038  * I2C port 1 by clearing GPOD bits 7:6 and GPOD bits 5:4, respectively.
0039  */
0040 #define IOP3XX_ICR_SCLEN    0x0020  /* 1=SCL enable for master mode */
0041 #define IOP3XX_ICR_MABORT   0x0010  /* 1=Send a STOP with no data
0042                      * NB TBYTE must be clear */
0043 #define IOP3XX_ICR_TBYTE    0x0008  /* 1=Send/Receive a byte. i2c clears */
0044 #define IOP3XX_ICR_NACK     0x0004  /* 1=reply with NACK */
0045 #define IOP3XX_ICR_MSTOP    0x0002  /* 1=send a STOP after next data byte */
0046 #define IOP3XX_ICR_MSTART   0x0001  /* 1=initiate a START */
0047
0048
0049 #define IOP3XX_ISR_BERRD    0x0400  /* 1=BUS ERROR Detected */
0050 #define IOP3XX_ISR_SAD      0x0200  /* 1=Slave ADdress Detected */
0051 #define IOP3XX_ISR_GCAD     0x0100  /* 1=General Call Address Detected */
0052 #define IOP3XX_ISR_RXFULL   0x0080  /* 1=Receive Full */
0053 #define IOP3XX_ISR_TXEMPTY  0x0040  /* 1=Transmit Empty */
0054 #define IOP3XX_ISR_ALD      0x0020  /* 1=Arbitration Loss Detected */
0055 #define IOP3XX_ISR_SSD      0x0010  /* 1=Slave STOP Detected */
0056 #define IOP3XX_ISR_BBUSY    0x0008  /* 1=Bus BUSY */
0057 #define IOP3XX_ISR_UNITBUSY 0x0004  /* 1=Unit Busy */
0058 #define IOP3XX_ISR_NACK     0x0002  /* 1=Unit Rx or Tx a NACK */
0059 #define IOP3XX_ISR_RXREAD   0x0001  /* 1=READ 0=WRITE (R/W bit of slave addr */
0060
0061 #define IOP3XX_ISR_CLEARBITS    0x07f0
0062
0063 #define IOP3XX_ISAR_SAMASK  0x007f
0064
0065 #define IOP3XX_IDBR_MASK    0x00ff
0066
0067 #define IOP3XX_IBMR_SCL     0x0002
0068 #define IOP3XX_IBMR_SDA     0x0001
0069
0070 #define IOP3XX_GPOD_I2C0    0x00c0  /* clear these bits to enable ch0 */
0071 #define IOP3XX_GPOD_I2C1    0x0030  /* clear these bits to enable ch1 */
0072
0073 #define MYSAR           0   /* default slave address */
0074
0075 #define I2C_ERR         321
0076 #define I2C_ERR_BERR        (I2C_ERR+0)
0077 #define I2C_ERR_ALD     (I2C_ERR+1)
0078
0079
0080 #define CR_OFFSET       0
0081 #define SR_OFFSET       0x4
0082 #define SAR_OFFSET      0x8
0083 #define DBR_OFFSET      0xc
0084 #define CCR_OFFSET      0x10
0085 #define BMR_OFFSET      0x14
0086
0087 #define IOP3XX_I2C_IO_SIZE  0x18
0088
0089 struct i2c_algo_iop3xx_data {
0090     void __iomem *ioaddr;
0091     wait_queue_head_t waitq;
0092     spinlock_t lock;
0093     u32 SR_enabled, SR_received;
0094     int id;
0095     struct gpio_desc *gpio_scl;
0096     struct gpio_desc *gpio_sda;
0097 };
0098
0099 #endif /* I2C_IOP3XX_H */