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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * drivers/i2c/busses/i2c-ibm_iic.c
0004  *
0005  * Support for the IIC peripheral on IBM PPC 4xx
0006  *
0007  * Copyright (c) 2003, 2004 Zultys Technologies.
0008  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
0009  *
0010  * Copyright (c) 2008 PIKA Technologies
0011  * Sean MacLennan <smaclennan@pikatech.com>
0012  *
0013  * Based on original work by
0014  *  Ian DaSilva  <idasilva@mvista.com>
0015  *      Armin Kuster <akuster@mvista.com>
0016  *  Matt Porter  <mporter@mvista.com>
0017  *
0018  *      Copyright 2000-2003 MontaVista Software Inc.
0019  *
0020  * Original driver version was highly leveraged from i2c-elektor.c
0021  *
0022  *      Copyright 1995-97 Simon G. Vogl
0023  *                1998-99 Hans Berglund
0024  *
0025  *      With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi>
0026  *  and even Frodo Looijaard <frodol@dds.nl>
0027  */
0028 
0029 #include <linux/module.h>
0030 #include <linux/kernel.h>
0031 #include <linux/ioport.h>
0032 #include <linux/delay.h>
0033 #include <linux/slab.h>
0034 #include <linux/interrupt.h>
0035 #include <linux/sched/signal.h>
0036 
0037 #include <asm/irq.h>
0038 #include <linux/io.h>
0039 #include <linux/i2c.h>
0040 #include <linux/of_address.h>
0041 #include <linux/of_irq.h>
0042 #include <linux/of_platform.h>
0043 
0044 #include "i2c-ibm_iic.h"
0045 
0046 #define DRIVER_VERSION "2.2"
0047 
0048 MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
0049 MODULE_LICENSE("GPL");
0050 
0051 static bool iic_force_poll;
0052 module_param(iic_force_poll, bool, 0);
0053 MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
0054 
0055 static bool iic_force_fast;
0056 module_param(iic_force_fast, bool, 0);
0057 MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)");
0058 
0059 #define DBG_LEVEL 0
0060 
0061 #ifdef DBG
0062 #undef DBG
0063 #endif
0064 
0065 #ifdef DBG2
0066 #undef DBG2
0067 #endif
0068 
0069 #if DBG_LEVEL > 0
0070 #  define DBG(f,x...)   printk(KERN_DEBUG "ibm-iic" f, ##x)
0071 #else
0072 #  define DBG(f,x...)   ((void)0)
0073 #endif
0074 #if DBG_LEVEL > 1
0075 #  define DBG2(f,x...)  DBG(f, ##x)
0076 #else
0077 #  define DBG2(f,x...)  ((void)0)
0078 #endif
0079 #if DBG_LEVEL > 2
0080 static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
0081 {
0082     volatile struct iic_regs __iomem *iic = dev->vaddr;
0083     printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
0084     printk(KERN_DEBUG
0085            "  cntl     = 0x%02x, mdcntl = 0x%02x\n"
0086            "  sts      = 0x%02x, extsts = 0x%02x\n"
0087            "  clkdiv   = 0x%02x, xfrcnt = 0x%02x\n"
0088            "  xtcntlss = 0x%02x, directcntl = 0x%02x\n",
0089         in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
0090         in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
0091         in_8(&iic->xtcntlss), in_8(&iic->directcntl));
0092 }
0093 #  define DUMP_REGS(h,dev)  dump_iic_regs((h),(dev))
0094 #else
0095 #  define DUMP_REGS(h,dev)  ((void)0)
0096 #endif
0097 
0098 /* Bus timings (in ns) for bit-banging */
0099 static struct ibm_iic_timings {
0100     unsigned int hd_sta;
0101     unsigned int su_sto;
0102     unsigned int low;
0103     unsigned int high;
0104     unsigned int buf;
0105 } timings [] = {
0106 /* Standard mode (100 KHz) */
0107 {
0108     .hd_sta = 4000,
0109     .su_sto = 4000,
0110     .low    = 4700,
0111     .high   = 4000,
0112     .buf    = 4700,
0113 },
0114 /* Fast mode (400 KHz) */
0115 {
0116     .hd_sta = 600,
0117     .su_sto = 600,
0118     .low    = 1300,
0119     .high   = 600,
0120     .buf    = 1300,
0121 }};
0122 
0123 /* Enable/disable interrupt generation */
0124 static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
0125 {
0126     out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
0127 }
0128 
0129 /*
0130  * Initialize IIC interface.
0131  */
0132 static void iic_dev_init(struct ibm_iic_private* dev)
0133 {
0134     volatile struct iic_regs __iomem *iic = dev->vaddr;
0135 
0136     DBG("%d: init\n", dev->idx);
0137 
0138     /* Clear master address */
0139     out_8(&iic->lmadr, 0);
0140     out_8(&iic->hmadr, 0);
0141 
0142     /* Clear slave address */
0143     out_8(&iic->lsadr, 0);
0144     out_8(&iic->hsadr, 0);
0145 
0146     /* Clear status & extended status */
0147     out_8(&iic->sts, STS_SCMP | STS_IRQA);
0148     out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
0149                 | EXTSTS_ICT | EXTSTS_XFRA);
0150 
0151     /* Set clock divider */
0152     out_8(&iic->clkdiv, dev->clckdiv);
0153 
0154     /* Clear transfer count */
0155     out_8(&iic->xfrcnt, 0);
0156 
0157     /* Clear extended control and status */
0158     out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
0159                 | XTCNTLSS_SWS);
0160 
0161     /* Clear control register */
0162     out_8(&iic->cntl, 0);
0163 
0164     /* Enable interrupts if possible */
0165     iic_interrupt_mode(dev, dev->irq >= 0);
0166 
0167     /* Set mode control */
0168     out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
0169                 | (dev->fast_mode ? MDCNTL_FSM : 0));
0170 
0171     DUMP_REGS("iic_init", dev);
0172 }
0173 
0174 /*
0175  * Reset IIC interface
0176  */
0177 static void iic_dev_reset(struct ibm_iic_private* dev)
0178 {
0179     volatile struct iic_regs __iomem *iic = dev->vaddr;
0180     int i;
0181     u8 dc;
0182 
0183     DBG("%d: soft reset\n", dev->idx);
0184     DUMP_REGS("reset", dev);
0185 
0186         /* Place chip in the reset state */
0187     out_8(&iic->xtcntlss, XTCNTLSS_SRST);
0188 
0189     /* Check if bus is free */
0190     dc = in_8(&iic->directcntl);
0191     if (!DIRCTNL_FREE(dc)){
0192         DBG("%d: trying to regain bus control\n", dev->idx);
0193 
0194         /* Try to set bus free state */
0195         out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
0196 
0197         /* Wait until we regain bus control */
0198         for (i = 0; i < 100; ++i){
0199             dc = in_8(&iic->directcntl);
0200             if (DIRCTNL_FREE(dc))
0201                 break;
0202 
0203             /* Toggle SCL line */
0204             dc ^= DIRCNTL_SCC;
0205             out_8(&iic->directcntl, dc);
0206             udelay(10);
0207             dc ^= DIRCNTL_SCC;
0208             out_8(&iic->directcntl, dc);
0209 
0210             /* be nice */
0211             cond_resched();
0212         }
0213     }
0214 
0215     /* Remove reset */
0216     out_8(&iic->xtcntlss, 0);
0217 
0218     /* Reinitialize interface */
0219     iic_dev_init(dev);
0220 }
0221 
0222 /*
0223  * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
0224  */
0225 
0226 /* Wait for SCL and/or SDA to be high */
0227 static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
0228 {
0229     unsigned long x = jiffies + HZ / 28 + 2;
0230     while ((in_8(&iic->directcntl) & mask) != mask){
0231         if (unlikely(time_after(jiffies, x)))
0232             return -1;
0233         cond_resched();
0234     }
0235     return 0;
0236 }
0237 
0238 static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
0239 {
0240     volatile struct iic_regs __iomem *iic = dev->vaddr;
0241     const struct ibm_iic_timings *t = &timings[dev->fast_mode ? 1 : 0];
0242     u8 mask, v, sda;
0243     int i, res;
0244 
0245     /* Only 7-bit addresses are supported */
0246     if (unlikely(p->flags & I2C_M_TEN)){
0247         DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
0248             dev->idx);
0249         return -EINVAL;
0250     }
0251 
0252     DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
0253 
0254     /* Reset IIC interface */
0255     out_8(&iic->xtcntlss, XTCNTLSS_SRST);
0256 
0257     /* Wait for bus to become free */
0258     out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
0259     if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
0260         goto err;
0261     ndelay(t->buf);
0262 
0263     /* START */
0264     out_8(&iic->directcntl, DIRCNTL_SCC);
0265     sda = 0;
0266     ndelay(t->hd_sta);
0267 
0268     /* Send address */
0269     v = i2c_8bit_addr_from_msg(p);
0270     for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
0271         out_8(&iic->directcntl, sda);
0272         ndelay(t->low / 2);
0273         sda = (v & mask) ? DIRCNTL_SDAC : 0;
0274         out_8(&iic->directcntl, sda);
0275         ndelay(t->low / 2);
0276 
0277         out_8(&iic->directcntl, DIRCNTL_SCC | sda);
0278         if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
0279             goto err;
0280         ndelay(t->high);
0281     }
0282 
0283     /* ACK */
0284     out_8(&iic->directcntl, sda);
0285     ndelay(t->low / 2);
0286     out_8(&iic->directcntl, DIRCNTL_SDAC);
0287     ndelay(t->low / 2);
0288     out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
0289     if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
0290         goto err;
0291     res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
0292     ndelay(t->high);
0293 
0294     /* STOP */
0295     out_8(&iic->directcntl, 0);
0296     ndelay(t->low);
0297     out_8(&iic->directcntl, DIRCNTL_SCC);
0298     if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
0299         goto err;
0300     ndelay(t->su_sto);
0301     out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
0302 
0303     ndelay(t->buf);
0304 
0305     DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
0306 out:
0307     /* Remove reset */
0308     out_8(&iic->xtcntlss, 0);
0309 
0310     /* Reinitialize interface */
0311     iic_dev_init(dev);
0312 
0313     return res;
0314 err:
0315     DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
0316     res = -EREMOTEIO;
0317     goto out;
0318 }
0319 
0320 /*
0321  * IIC interrupt handler
0322  */
0323 static irqreturn_t iic_handler(int irq, void *dev_id)
0324 {
0325     struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
0326     volatile struct iic_regs __iomem *iic = dev->vaddr;
0327 
0328     DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n",
0329          dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
0330 
0331     /* Acknowledge IRQ and wakeup iic_wait_for_tc */
0332     out_8(&iic->sts, STS_IRQA | STS_SCMP);
0333     wake_up_interruptible(&dev->wq);
0334 
0335     return IRQ_HANDLED;
0336 }
0337 
0338 /*
0339  * Get master transfer result and clear errors if any.
0340  * Returns the number of actually transferred bytes or error (<0)
0341  */
0342 static int iic_xfer_result(struct ibm_iic_private* dev)
0343 {
0344     volatile struct iic_regs __iomem *iic = dev->vaddr;
0345 
0346     if (unlikely(in_8(&iic->sts) & STS_ERR)){
0347         DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx,
0348             in_8(&iic->extsts));
0349 
0350         /* Clear errors and possible pending IRQs */
0351         out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
0352             EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
0353 
0354         /* Flush master data buffer */
0355         out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
0356 
0357         /* Is bus free?
0358          * If error happened during combined xfer
0359          * IIC interface is usually stuck in some strange
0360          * state, the only way out - soft reset.
0361          */
0362         if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
0363             DBG("%d: bus is stuck, resetting\n", dev->idx);
0364             iic_dev_reset(dev);
0365         }
0366         return -EREMOTEIO;
0367     }
0368     else
0369         return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
0370 }
0371 
0372 /*
0373  * Try to abort active transfer.
0374  */
0375 static void iic_abort_xfer(struct ibm_iic_private* dev)
0376 {
0377     volatile struct iic_regs __iomem *iic = dev->vaddr;
0378     unsigned long x;
0379 
0380     DBG("%d: iic_abort_xfer\n", dev->idx);
0381 
0382     out_8(&iic->cntl, CNTL_HMT);
0383 
0384     /*
0385      * Wait for the abort command to complete.
0386      * It's not worth to be optimized, just poll (timeout >= 1 tick)
0387      */
0388     x = jiffies + 2;
0389     while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
0390         if (time_after(jiffies, x)){
0391             DBG("%d: abort timeout, resetting...\n", dev->idx);
0392             iic_dev_reset(dev);
0393             return;
0394         }
0395         schedule();
0396     }
0397 
0398     /* Just to clear errors */
0399     iic_xfer_result(dev);
0400 }
0401 
0402 /*
0403  * Wait for master transfer to complete.
0404  * It puts current process to sleep until we get interrupt or timeout expires.
0405  * Returns the number of transferred bytes or error (<0)
0406  */
0407 static int iic_wait_for_tc(struct ibm_iic_private* dev){
0408 
0409     volatile struct iic_regs __iomem *iic = dev->vaddr;
0410     int ret = 0;
0411 
0412     if (dev->irq >= 0){
0413         /* Interrupt mode */
0414         ret = wait_event_interruptible_timeout(dev->wq,
0415             !(in_8(&iic->sts) & STS_PT), dev->adap.timeout);
0416 
0417         if (unlikely(ret < 0))
0418             DBG("%d: wait interrupted\n", dev->idx);
0419         else if (unlikely(in_8(&iic->sts) & STS_PT)){
0420             DBG("%d: wait timeout\n", dev->idx);
0421             ret = -ETIMEDOUT;
0422         }
0423     }
0424     else {
0425         /* Polling mode */
0426         unsigned long x = jiffies + dev->adap.timeout;
0427 
0428         while (in_8(&iic->sts) & STS_PT){
0429             if (unlikely(time_after(jiffies, x))){
0430                 DBG("%d: poll timeout\n", dev->idx);
0431                 ret = -ETIMEDOUT;
0432                 break;
0433             }
0434 
0435             if (signal_pending(current)){
0436                 DBG("%d: poll interrupted\n", dev->idx);
0437                 ret = -ERESTARTSYS;
0438                 break;
0439             }
0440             schedule();
0441         }
0442     }
0443 
0444     if (unlikely(ret < 0))
0445         iic_abort_xfer(dev);
0446     else
0447         ret = iic_xfer_result(dev);
0448 
0449     DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
0450 
0451     return ret;
0452 }
0453 
0454 /*
0455  * Low level master transfer routine
0456  */
0457 static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm,
0458               int combined_xfer)
0459 {
0460     volatile struct iic_regs __iomem *iic = dev->vaddr;
0461     char* buf = pm->buf;
0462     int i, j, loops, ret = 0;
0463     int len = pm->len;
0464 
0465     u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
0466     if (pm->flags & I2C_M_RD)
0467         cntl |= CNTL_RW;
0468 
0469     loops = (len + 3) / 4;
0470     for (i = 0; i < loops; ++i, len -= 4){
0471         int count = len > 4 ? 4 : len;
0472         u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
0473 
0474         if (!(cntl & CNTL_RW))
0475             for (j = 0; j < count; ++j)
0476                 out_8((void __iomem *)&iic->mdbuf, *buf++);
0477 
0478         if (i < loops - 1)
0479             cmd |= CNTL_CHT;
0480         else if (combined_xfer)
0481             cmd |= CNTL_RPST;
0482 
0483         DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
0484 
0485         /* Start transfer */
0486         out_8(&iic->cntl, cmd);
0487 
0488         /* Wait for completion */
0489         ret = iic_wait_for_tc(dev);
0490 
0491         if (unlikely(ret < 0))
0492             break;
0493         else if (unlikely(ret != count)){
0494             DBG("%d: xfer_bytes, requested %d, transferred %d\n",
0495                 dev->idx, count, ret);
0496 
0497             /* If it's not a last part of xfer, abort it */
0498             if (combined_xfer || (i < loops - 1))
0499                     iic_abort_xfer(dev);
0500 
0501             ret = -EREMOTEIO;
0502             break;
0503         }
0504 
0505         if (cntl & CNTL_RW)
0506             for (j = 0; j < count; ++j)
0507                 *buf++ = in_8((void __iomem *)&iic->mdbuf);
0508     }
0509 
0510     return ret > 0 ? 0 : ret;
0511 }
0512 
0513 /*
0514  * Set target slave address for master transfer
0515  */
0516 static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
0517 {
0518     volatile struct iic_regs __iomem *iic = dev->vaddr;
0519     u16 addr = msg->addr;
0520 
0521     DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx,
0522         addr, msg->flags & I2C_M_TEN ? 10 : 7);
0523 
0524     if (msg->flags & I2C_M_TEN){
0525         out_8(&iic->cntl, CNTL_AMD);
0526         out_8(&iic->lmadr, addr);
0527         out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
0528     }
0529     else {
0530         out_8(&iic->cntl, 0);
0531         out_8(&iic->lmadr, addr << 1);
0532     }
0533 }
0534 
0535 static inline int iic_invalid_address(const struct i2c_msg* p)
0536 {
0537     return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
0538 }
0539 
0540 static inline int iic_address_neq(const struct i2c_msg* p1,
0541                   const struct i2c_msg* p2)
0542 {
0543     return (p1->addr != p2->addr)
0544         || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
0545 }
0546 
0547 /*
0548  * Generic master transfer entrypoint.
0549  * Returns the number of processed messages or error (<0)
0550  */
0551 static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
0552 {
0553         struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
0554     volatile struct iic_regs __iomem *iic = dev->vaddr;
0555     int i, ret = 0;
0556 
0557     DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
0558 
0559     /* Check the sanity of the passed messages.
0560      * Uhh, generic i2c layer is more suitable place for such code...
0561      */
0562     if (unlikely(iic_invalid_address(&msgs[0]))){
0563         DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx,
0564             msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
0565         return -EINVAL;
0566     }
0567     for (i = 0; i < num; ++i){
0568         if (unlikely(msgs[i].len <= 0)){
0569             if (num == 1 && !msgs[0].len){
0570                 /* Special case for I2C_SMBUS_QUICK emulation.
0571                  * IBM IIC doesn't support 0-length transactions
0572                  * so we have to emulate them using bit-banging.
0573                  */
0574                 return iic_smbus_quick(dev, &msgs[0]);
0575             }
0576             DBG("%d: invalid len %d in msg[%d]\n", dev->idx,
0577                 msgs[i].len, i);
0578             return -EINVAL;
0579         }
0580         if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
0581             DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
0582             return -EINVAL;
0583         }
0584     }
0585 
0586     /* Check bus state */
0587     if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
0588         DBG("%d: iic_xfer, bus is not free\n", dev->idx);
0589 
0590         /* Usually it means something serious has happened.
0591          * We *cannot* have unfinished previous transfer
0592          * so it doesn't make any sense to try to stop it.
0593          * Probably we were not able to recover from the
0594          * previous error.
0595          * The only *reasonable* thing I can think of here
0596          * is soft reset.  --ebs
0597          */
0598         iic_dev_reset(dev);
0599 
0600         if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
0601             DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
0602             return -EREMOTEIO;
0603         }
0604     }
0605     else {
0606         /* Flush master data buffer (just in case) */
0607         out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
0608     }
0609 
0610     /* Load slave address */
0611     iic_address(dev, &msgs[0]);
0612 
0613     /* Do real transfer */
0614         for (i = 0; i < num && !ret; ++i)
0615         ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
0616 
0617     return ret < 0 ? ret : num;
0618 }
0619 
0620 static u32 iic_func(struct i2c_adapter *adap)
0621 {
0622     return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
0623 }
0624 
0625 static const struct i2c_algorithm iic_algo = {
0626     .master_xfer    = iic_xfer,
0627     .functionality  = iic_func
0628 };
0629 
0630 /*
0631  * Calculates IICx_CLCKDIV value for a specific OPB clock frequency
0632  */
0633 static inline u8 iic_clckdiv(unsigned int opb)
0634 {
0635     /* Compatibility kludge, should go away after all cards
0636      * are fixed to fill correct value for opbfreq.
0637      * Previous driver version used hardcoded divider value 4,
0638      * it corresponds to OPB frequency from the range (40, 50] MHz
0639      */
0640     if (!opb){
0641         printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
0642             " fix your board specific setup\n");
0643         opb = 50000000;
0644     }
0645 
0646     /* Convert to MHz */
0647     opb /= 1000000;
0648 
0649     if (opb < 20 || opb > 150){
0650         printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n",
0651             opb);
0652         opb = opb < 20 ? 20 : 150;
0653     }
0654     return (u8)((opb + 9) / 10 - 1);
0655 }
0656 
0657 static int iic_request_irq(struct platform_device *ofdev,
0658                      struct ibm_iic_private *dev)
0659 {
0660     struct device_node *np = ofdev->dev.of_node;
0661     int irq;
0662 
0663     if (iic_force_poll)
0664         return 0;
0665 
0666     irq = irq_of_parse_and_map(np, 0);
0667     if (!irq) {
0668         dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
0669         return 0;
0670     }
0671 
0672     /* Disable interrupts until we finish initialization, assumes
0673      *  level-sensitive IRQ setup...
0674      */
0675     iic_interrupt_mode(dev, 0);
0676     if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
0677         dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
0678         /* Fallback to the polling mode */
0679         return 0;
0680     }
0681 
0682     return irq;
0683 }
0684 
0685 /*
0686  * Register single IIC interface
0687  */
0688 static int iic_probe(struct platform_device *ofdev)
0689 {
0690     struct device_node *np = ofdev->dev.of_node;
0691     struct ibm_iic_private *dev;
0692     struct i2c_adapter *adap;
0693     const u32 *freq;
0694     int ret;
0695 
0696     dev = kzalloc(sizeof(*dev), GFP_KERNEL);
0697     if (!dev) {
0698         dev_err(&ofdev->dev, "failed to allocate device data\n");
0699         return -ENOMEM;
0700     }
0701 
0702     platform_set_drvdata(ofdev, dev);
0703 
0704     dev->vaddr = of_iomap(np, 0);
0705     if (dev->vaddr == NULL) {
0706         dev_err(&ofdev->dev, "failed to iomap device\n");
0707         ret = -ENXIO;
0708         goto error_cleanup;
0709     }
0710 
0711     init_waitqueue_head(&dev->wq);
0712 
0713     dev->irq = iic_request_irq(ofdev, dev);
0714     if (!dev->irq)
0715         dev_warn(&ofdev->dev, "using polling mode\n");
0716 
0717     /* Board specific settings */
0718     if (iic_force_fast || of_get_property(np, "fast-mode", NULL))
0719         dev->fast_mode = 1;
0720 
0721     freq = of_get_property(np, "clock-frequency", NULL);
0722     if (freq == NULL) {
0723         freq = of_get_property(np->parent, "clock-frequency", NULL);
0724         if (freq == NULL) {
0725             dev_err(&ofdev->dev, "Unable to get bus frequency\n");
0726             ret = -EINVAL;
0727             goto error_cleanup;
0728         }
0729     }
0730 
0731     dev->clckdiv = iic_clckdiv(*freq);
0732     dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv);
0733 
0734     /* Initialize IIC interface */
0735     iic_dev_init(dev);
0736 
0737     /* Register it with i2c layer */
0738     adap = &dev->adap;
0739     adap->dev.parent = &ofdev->dev;
0740     adap->dev.of_node = of_node_get(np);
0741     strscpy(adap->name, "IBM IIC", sizeof(adap->name));
0742     i2c_set_adapdata(adap, dev);
0743     adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
0744     adap->algo = &iic_algo;
0745     adap->timeout = HZ;
0746 
0747     ret = i2c_add_adapter(adap);
0748     if (ret  < 0)
0749         goto error_cleanup;
0750 
0751     dev_info(&ofdev->dev, "using %s mode\n",
0752          dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
0753 
0754     return 0;
0755 
0756 error_cleanup:
0757     if (dev->irq) {
0758         iic_interrupt_mode(dev, 0);
0759         free_irq(dev->irq, dev);
0760     }
0761 
0762     if (dev->vaddr)
0763         iounmap(dev->vaddr);
0764 
0765     kfree(dev);
0766     return ret;
0767 }
0768 
0769 /*
0770  * Cleanup initialized IIC interface
0771  */
0772 static int iic_remove(struct platform_device *ofdev)
0773 {
0774     struct ibm_iic_private *dev = platform_get_drvdata(ofdev);
0775 
0776     i2c_del_adapter(&dev->adap);
0777 
0778     if (dev->irq) {
0779         iic_interrupt_mode(dev, 0);
0780         free_irq(dev->irq, dev);
0781     }
0782 
0783     iounmap(dev->vaddr);
0784     kfree(dev);
0785 
0786     return 0;
0787 }
0788 
0789 static const struct of_device_id ibm_iic_match[] = {
0790     { .compatible = "ibm,iic", },
0791     {}
0792 };
0793 MODULE_DEVICE_TABLE(of, ibm_iic_match);
0794 
0795 static struct platform_driver ibm_iic_driver = {
0796     .driver = {
0797         .name = "ibm-iic",
0798         .of_match_table = ibm_iic_match,
0799     },
0800     .probe  = iic_probe,
0801     .remove = iic_remove,
0802 };
0803 
0804 module_platform_driver(ibm_iic_driver);
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