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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
0004     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
0005     <mdsxyz123@yahoo.com>
0006     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
0007     Copyright (C) 2010         Intel Corporation,
0008                                David Woodhouse <dwmw2@infradead.org>
0009 
0010 */
0011 
0012 /*
0013  * Supports the following Intel I/O Controller Hubs (ICH):
0014  *
0015  *                  I/O         Block   I2C
0016  *                  region  SMBus   Block   proc.   block
0017  * Chip name            PCI ID  size    PEC buffer  call    read
0018  * ---------------------------------------------------------------------------
0019  * 82801AA (ICH)        0x2413  16  no  no  no  no
0020  * 82801AB (ICH0)       0x2423  16  no  no  no  no
0021  * 82801BA (ICH2)       0x2443  16  no  no  no  no
0022  * 82801CA (ICH3)       0x2483  32  soft    no  no  no
0023  * 82801DB (ICH4)       0x24c3  32  hard    yes no  no
0024  * 82801E (ICH5)        0x24d3  32  hard    yes yes yes
0025  * 6300ESB          0x25a4  32  hard    yes yes yes
0026  * 82801F (ICH6)        0x266a  32  hard    yes yes yes
0027  * 6310ESB/6320ESB      0x269b  32  hard    yes yes yes
0028  * 82801G (ICH7)        0x27da  32  hard    yes yes yes
0029  * 82801H (ICH8)        0x283e  32  hard    yes yes yes
0030  * 82801I (ICH9)        0x2930  32  hard    yes yes yes
0031  * EP80579 (Tolapai)        0x5032  32  hard    yes yes yes
0032  * ICH10            0x3a30  32  hard    yes yes yes
0033  * ICH10            0x3a60  32  hard    yes yes yes
0034  * 5/3400 Series (PCH)      0x3b30  32  hard    yes yes yes
0035  * 6 Series (PCH)       0x1c22  32  hard    yes yes yes
0036  * Patsburg (PCH)       0x1d22  32  hard    yes yes yes
0037  * Patsburg (PCH) IDF       0x1d70  32  hard    yes yes yes
0038  * Patsburg (PCH) IDF       0x1d71  32  hard    yes yes yes
0039  * Patsburg (PCH) IDF       0x1d72  32  hard    yes yes yes
0040  * DH89xxCC (PCH)       0x2330  32  hard    yes yes yes
0041  * Panther Point (PCH)      0x1e22  32  hard    yes yes yes
0042  * Lynx Point (PCH)     0x8c22  32  hard    yes yes yes
0043  * Lynx Point-LP (PCH)      0x9c22  32  hard    yes yes yes
0044  * Avoton (SOC)         0x1f3c  32  hard    yes yes yes
0045  * Wellsburg (PCH)      0x8d22  32  hard    yes yes yes
0046  * Wellsburg (PCH) MS       0x8d7d  32  hard    yes yes yes
0047  * Wellsburg (PCH) MS       0x8d7e  32  hard    yes yes yes
0048  * Wellsburg (PCH) MS       0x8d7f  32  hard    yes yes yes
0049  * Coleto Creek (PCH)       0x23b0  32  hard    yes yes yes
0050  * Wildcat Point (PCH)      0x8ca2  32  hard    yes yes yes
0051  * Wildcat Point-LP (PCH)   0x9ca2  32  hard    yes yes yes
0052  * BayTrail (SOC)       0x0f12  32  hard    yes yes yes
0053  * Braswell (SOC)       0x2292  32  hard    yes yes yes
0054  * Sunrise Point-H (PCH)    0xa123  32  hard    yes yes yes
0055  * Sunrise Point-LP (PCH)   0x9d23  32  hard    yes yes yes
0056  * DNV (SOC)            0x19df  32  hard    yes yes yes
0057  * Emmitsburg (PCH)     0x1bc9  32  hard    yes yes yes
0058  * Broxton (SOC)        0x5ad4  32  hard    yes yes yes
0059  * Lewisburg (PCH)      0xa1a3  32  hard    yes yes yes
0060  * Lewisburg Supersku (PCH) 0xa223  32  hard    yes yes yes
0061  * Kaby Lake PCH-H (PCH)    0xa2a3  32  hard    yes yes yes
0062  * Gemini Lake (SOC)        0x31d4  32  hard    yes yes yes
0063  * Cannon Lake-H (PCH)      0xa323  32  hard    yes yes yes
0064  * Cannon Lake-LP (PCH)     0x9da3  32  hard    yes yes yes
0065  * Cedar Fork (PCH)     0x18df  32  hard    yes yes yes
0066  * Ice Lake-LP (PCH)        0x34a3  32  hard    yes yes yes
0067  * Ice Lake-N (PCH)     0x38a3  32  hard    yes yes yes
0068  * Comet Lake (PCH)     0x02a3  32  hard    yes yes yes
0069  * Comet Lake-H (PCH)       0x06a3  32  hard    yes yes yes
0070  * Elkhart Lake (PCH)       0x4b23  32  hard    yes yes yes
0071  * Tiger Lake-LP (PCH)      0xa0a3  32  hard    yes yes yes
0072  * Tiger Lake-H (PCH)       0x43a3  32  hard    yes yes yes
0073  * Jasper Lake (SOC)        0x4da3  32  hard    yes yes yes
0074  * Comet Lake-V (PCH)       0xa3a3  32  hard    yes yes yes
0075  * Alder Lake-S (PCH)       0x7aa3  32  hard    yes yes yes
0076  * Alder Lake-P (PCH)       0x51a3  32  hard    yes yes yes
0077  * Alder Lake-M (PCH)       0x54a3  32  hard    yes yes yes
0078  * Raptor Lake-S (PCH)      0x7a23  32  hard    yes yes yes
0079  * Meteor Lake-P (SOC)      0x7e22  32  hard    yes yes yes
0080  *
0081  * Features supported by this driver:
0082  * Software PEC             no
0083  * Hardware PEC             yes
0084  * Block buffer             yes
0085  * Block process call transaction   yes
0086  * I2C block read transaction       yes (doesn't use the block buffer)
0087  * Slave mode               no
0088  * SMBus Host Notify            yes
0089  * Interrupt processing         yes
0090  *
0091  * See the file Documentation/i2c/busses/i2c-i801.rst for details.
0092  */
0093 
0094 #define DRV_NAME    "i801_smbus"
0095 
0096 #include <linux/interrupt.h>
0097 #include <linux/module.h>
0098 #include <linux/pci.h>
0099 #include <linux/kernel.h>
0100 #include <linux/stddef.h>
0101 #include <linux/delay.h>
0102 #include <linux/ioport.h>
0103 #include <linux/init.h>
0104 #include <linux/i2c.h>
0105 #include <linux/i2c-smbus.h>
0106 #include <linux/acpi.h>
0107 #include <linux/io.h>
0108 #include <linux/dmi.h>
0109 #include <linux/slab.h>
0110 #include <linux/string.h>
0111 #include <linux/completion.h>
0112 #include <linux/err.h>
0113 #include <linux/platform_device.h>
0114 #include <linux/platform_data/itco_wdt.h>
0115 #include <linux/platform_data/x86/p2sb.h>
0116 #include <linux/pm_runtime.h>
0117 #include <linux/mutex.h>
0118 
0119 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
0120 #include <linux/gpio/machine.h>
0121 #include <linux/platform_data/i2c-mux-gpio.h>
0122 #endif
0123 
0124 /* I801 SMBus address offsets */
0125 #define SMBHSTSTS(p)    (0 + (p)->smba)
0126 #define SMBHSTCNT(p)    (2 + (p)->smba)
0127 #define SMBHSTCMD(p)    (3 + (p)->smba)
0128 #define SMBHSTADD(p)    (4 + (p)->smba)
0129 #define SMBHSTDAT0(p)   (5 + (p)->smba)
0130 #define SMBHSTDAT1(p)   (6 + (p)->smba)
0131 #define SMBBLKDAT(p)    (7 + (p)->smba)
0132 #define SMBPEC(p)   (8 + (p)->smba)     /* ICH3 and later */
0133 #define SMBAUXSTS(p)    (12 + (p)->smba)    /* ICH4 and later */
0134 #define SMBAUXCTL(p)    (13 + (p)->smba)    /* ICH4 and later */
0135 #define SMBSLVSTS(p)    (16 + (p)->smba)    /* ICH3 and later */
0136 #define SMBSLVCMD(p)    (17 + (p)->smba)    /* ICH3 and later */
0137 #define SMBNTFDADD(p)   (20 + (p)->smba)    /* ICH3 and later */
0138 
0139 /* PCI Address Constants */
0140 #define SMBBAR      4
0141 #define SMBHSTCFG   0x040
0142 #define TCOBASE     0x050
0143 #define TCOCTL      0x054
0144 
0145 #define SBREG_SMBCTRL       0xc6000c
0146 #define SBREG_SMBCTRL_DNV   0xcf000c
0147 
0148 /* Host configuration bits for SMBHSTCFG */
0149 #define SMBHSTCFG_HST_EN    BIT(0)
0150 #define SMBHSTCFG_SMB_SMI_EN    BIT(1)
0151 #define SMBHSTCFG_I2C_EN    BIT(2)
0152 #define SMBHSTCFG_SPD_WD    BIT(4)
0153 
0154 /* TCO configuration bits for TCOCTL */
0155 #define TCOCTL_EN       BIT(8)
0156 
0157 /* Auxiliary status register bits, ICH4+ only */
0158 #define SMBAUXSTS_CRCE      BIT(0)
0159 #define SMBAUXSTS_STCO      BIT(1)
0160 
0161 /* Auxiliary control register bits, ICH4+ only */
0162 #define SMBAUXCTL_CRC       BIT(0)
0163 #define SMBAUXCTL_E32B      BIT(1)
0164 
0165 /* I801 command constants */
0166 #define I801_QUICK      0x00
0167 #define I801_BYTE       0x04
0168 #define I801_BYTE_DATA      0x08
0169 #define I801_WORD_DATA      0x0C
0170 #define I801_PROC_CALL      0x10
0171 #define I801_BLOCK_DATA     0x14
0172 #define I801_I2C_BLOCK_DATA 0x18    /* ICH5 and later */
0173 #define I801_BLOCK_PROC_CALL    0x1C
0174 
0175 /* I801 Host Control register bits */
0176 #define SMBHSTCNT_INTREN    BIT(0)
0177 #define SMBHSTCNT_KILL      BIT(1)
0178 #define SMBHSTCNT_LAST_BYTE BIT(5)
0179 #define SMBHSTCNT_START     BIT(6)
0180 #define SMBHSTCNT_PEC_EN    BIT(7)  /* ICH3 and later */
0181 
0182 /* I801 Hosts Status register bits */
0183 #define SMBHSTSTS_BYTE_DONE BIT(7)
0184 #define SMBHSTSTS_INUSE_STS BIT(6)
0185 #define SMBHSTSTS_SMBALERT_STS  BIT(5)
0186 #define SMBHSTSTS_FAILED    BIT(4)
0187 #define SMBHSTSTS_BUS_ERR   BIT(3)
0188 #define SMBHSTSTS_DEV_ERR   BIT(2)
0189 #define SMBHSTSTS_INTR      BIT(1)
0190 #define SMBHSTSTS_HOST_BUSY BIT(0)
0191 
0192 /* Host Notify Status register bits */
0193 #define SMBSLVSTS_HST_NTFY_STS  BIT(0)
0194 
0195 /* Host Notify Command register bits */
0196 #define SMBSLVCMD_SMBALERT_DISABLE  BIT(2)
0197 #define SMBSLVCMD_HST_NTFY_INTREN   BIT(0)
0198 
0199 #define STATUS_ERROR_FLAGS  (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
0200                  SMBHSTSTS_DEV_ERR)
0201 
0202 #define STATUS_FLAGS        (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
0203                  STATUS_ERROR_FLAGS)
0204 
0205 /* Older devices have their ID defined in <linux/pci_ids.h> */
0206 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS     0x02a3
0207 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS       0x06a3
0208 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS      0x0f12
0209 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS           0x18df
0210 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS           0x19df
0211 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS           0x1bc9
0212 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS       0x1c22
0213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS      0x1d22
0214 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
0215 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0     0x1d70
0216 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1     0x1d71
0217 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2     0x1d72
0218 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS      0x1e22
0219 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS        0x1f3c
0220 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS      0x2292
0221 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS      0x2330
0222 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS       0x23b0
0223 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS        0x31d4
0224 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS        0x34a3
0225 #define PCI_DEVICE_ID_INTEL_ICELAKE_N_SMBUS     0x38a3
0226 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS     0x3b30
0227 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS       0x43a3
0228 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS      0x4b23
0229 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS       0x4da3
0230 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS      0x51a3
0231 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS      0x54a3
0232 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS       0x5ad4
0233 #define PCI_DEVICE_ID_INTEL_RAPTOR_LAKE_S_SMBUS     0x7a23
0234 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS      0x7aa3
0235 #define PCI_DEVICE_ID_INTEL_METEOR_LAKE_P_SMBUS     0x7e22
0236 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS     0x8c22
0237 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS      0x8ca2
0238 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS     0x8d22
0239 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0     0x8d7d
0240 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1     0x8d7e
0241 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2     0x8d7f
0242 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS      0x9c22
0243 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS   0x9ca2
0244 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS   0x9d23
0245 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS     0x9da3
0246 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS      0xa0a3
0247 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS    0xa123
0248 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS     0xa1a3
0249 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS    0xa223
0250 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS    0xa2a3
0251 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS      0xa323
0252 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS       0xa3a3
0253 
0254 struct i801_mux_config {
0255     char *gpio_chip;
0256     unsigned values[3];
0257     int n_values;
0258     unsigned classes[3];
0259     unsigned gpios[2];      /* Relative to gpio_chip->base */
0260     int n_gpios;
0261 };
0262 
0263 struct i801_priv {
0264     struct i2c_adapter adapter;
0265     unsigned long smba;
0266     unsigned char original_hstcfg;
0267     unsigned char original_hstcnt;
0268     unsigned char original_slvcmd;
0269     struct pci_dev *pci_dev;
0270     unsigned int features;
0271 
0272     /* isr processing */
0273     struct completion done;
0274     u8 status;
0275 
0276     /* Command state used by isr for byte-by-byte block transactions */
0277     u8 cmd;
0278     bool is_read;
0279     int count;
0280     int len;
0281     u8 *data;
0282 
0283 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
0284     const struct i801_mux_config *mux_drvdata;
0285     struct platform_device *mux_pdev;
0286     struct gpiod_lookup_table *lookup;
0287 #endif
0288     struct platform_device *tco_pdev;
0289 
0290     /*
0291      * If set to true the host controller registers are reserved for
0292      * ACPI AML use. Protected by acpi_lock.
0293      */
0294     bool acpi_reserved;
0295     struct mutex acpi_lock;
0296 };
0297 
0298 #define FEATURE_SMBUS_PEC   BIT(0)
0299 #define FEATURE_BLOCK_BUFFER    BIT(1)
0300 #define FEATURE_BLOCK_PROC  BIT(2)
0301 #define FEATURE_I2C_BLOCK_READ  BIT(3)
0302 #define FEATURE_IRQ     BIT(4)
0303 #define FEATURE_HOST_NOTIFY BIT(5)
0304 /* Not really a feature, but it's convenient to handle it as such */
0305 #define FEATURE_IDF     BIT(15)
0306 #define FEATURE_TCO_SPT     BIT(16)
0307 #define FEATURE_TCO_CNL     BIT(17)
0308 
0309 static const char *i801_feature_names[] = {
0310     "SMBus PEC",
0311     "Block buffer",
0312     "Block process call",
0313     "I2C block read",
0314     "Interrupt",
0315     "SMBus Host Notify",
0316 };
0317 
0318 static unsigned int disable_features;
0319 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
0320 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
0321     "\t\t  0x01  disable SMBus PEC\n"
0322     "\t\t  0x02  disable the block buffer\n"
0323     "\t\t  0x08  disable the I2C block read functionality\n"
0324     "\t\t  0x10  don't use interrupts\n"
0325     "\t\t  0x20  disable SMBus Host Notify ");
0326 
0327 /* Make sure the SMBus host is ready to start transmitting.
0328    Return 0 if it is, -EBUSY if it is not. */
0329 static int i801_check_pre(struct i801_priv *priv)
0330 {
0331     int status;
0332 
0333     status = inb_p(SMBHSTSTS(priv));
0334     if (status & SMBHSTSTS_HOST_BUSY) {
0335         pci_err(priv->pci_dev, "SMBus is busy, can't use it!\n");
0336         return -EBUSY;
0337     }
0338 
0339     status &= STATUS_FLAGS;
0340     if (status) {
0341         pci_dbg(priv->pci_dev, "Clearing status flags (%02x)\n", status);
0342         outb_p(status, SMBHSTSTS(priv));
0343     }
0344 
0345     /*
0346      * Clear CRC status if needed.
0347      * During normal operation, i801_check_post() takes care
0348      * of it after every operation.  We do it here only in case
0349      * the hardware was already in this state when the driver
0350      * started.
0351      */
0352     if (priv->features & FEATURE_SMBUS_PEC) {
0353         status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
0354         if (status) {
0355             pci_dbg(priv->pci_dev, "Clearing aux status flags (%02x)\n", status);
0356             outb_p(status, SMBAUXSTS(priv));
0357         }
0358     }
0359 
0360     return 0;
0361 }
0362 
0363 static int i801_check_post(struct i801_priv *priv, int status)
0364 {
0365     int result = 0;
0366 
0367     /*
0368      * If the SMBus is still busy, we give up
0369      */
0370     if (unlikely(status < 0)) {
0371         dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
0372         /* try to stop the current command */
0373         dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
0374         outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
0375         usleep_range(1000, 2000);
0376         outb_p(0, SMBHSTCNT(priv));
0377 
0378         /* Check if it worked */
0379         status = inb_p(SMBHSTSTS(priv));
0380         if ((status & SMBHSTSTS_HOST_BUSY) ||
0381             !(status & SMBHSTSTS_FAILED))
0382             dev_err(&priv->pci_dev->dev,
0383                 "Failed terminating the transaction\n");
0384         return -ETIMEDOUT;
0385     }
0386 
0387     if (status & SMBHSTSTS_FAILED) {
0388         result = -EIO;
0389         dev_err(&priv->pci_dev->dev, "Transaction failed\n");
0390     }
0391     if (status & SMBHSTSTS_DEV_ERR) {
0392         /*
0393          * This may be a PEC error, check and clear it.
0394          *
0395          * AUXSTS is handled differently from HSTSTS.
0396          * For HSTSTS, i801_isr() or i801_wait_intr()
0397          * has already cleared the error bits in hardware,
0398          * and we are passed a copy of the original value
0399          * in "status".
0400          * For AUXSTS, the hardware register is left
0401          * for us to handle here.
0402          * This is asymmetric, slightly iffy, but safe,
0403          * since all this code is serialized and the CRCE
0404          * bit is harmless as long as it's cleared before
0405          * the next operation.
0406          */
0407         if ((priv->features & FEATURE_SMBUS_PEC) &&
0408             (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
0409             outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
0410             result = -EBADMSG;
0411             dev_dbg(&priv->pci_dev->dev, "PEC error\n");
0412         } else {
0413             result = -ENXIO;
0414             dev_dbg(&priv->pci_dev->dev, "No response\n");
0415         }
0416     }
0417     if (status & SMBHSTSTS_BUS_ERR) {
0418         result = -EAGAIN;
0419         dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
0420     }
0421 
0422     return result;
0423 }
0424 
0425 /* Wait for BUSY being cleared and either INTR or an error flag being set */
0426 static int i801_wait_intr(struct i801_priv *priv)
0427 {
0428     unsigned long timeout = jiffies + priv->adapter.timeout;
0429     int status, busy;
0430 
0431     do {
0432         usleep_range(250, 500);
0433         status = inb_p(SMBHSTSTS(priv));
0434         busy = status & SMBHSTSTS_HOST_BUSY;
0435         status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
0436         if (!busy && status)
0437             return status;
0438     } while (time_is_after_eq_jiffies(timeout));
0439 
0440     return -ETIMEDOUT;
0441 }
0442 
0443 /* Wait for either BYTE_DONE or an error flag being set */
0444 static int i801_wait_byte_done(struct i801_priv *priv)
0445 {
0446     unsigned long timeout = jiffies + priv->adapter.timeout;
0447     int status;
0448 
0449     do {
0450         usleep_range(250, 500);
0451         status = inb_p(SMBHSTSTS(priv));
0452         if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
0453             return status & STATUS_ERROR_FLAGS;
0454     } while (time_is_after_eq_jiffies(timeout));
0455 
0456     return -ETIMEDOUT;
0457 }
0458 
0459 static int i801_transaction(struct i801_priv *priv, int xact)
0460 {
0461     int status;
0462     unsigned long result;
0463     const struct i2c_adapter *adap = &priv->adapter;
0464 
0465     status = i801_check_pre(priv);
0466     if (status < 0)
0467         return status;
0468 
0469     if (priv->features & FEATURE_IRQ) {
0470         reinit_completion(&priv->done);
0471         outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
0472                SMBHSTCNT(priv));
0473         result = wait_for_completion_timeout(&priv->done, adap->timeout);
0474         return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
0475     }
0476 
0477     outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
0478 
0479     status = i801_wait_intr(priv);
0480     return i801_check_post(priv, status);
0481 }
0482 
0483 static int i801_block_transaction_by_block(struct i801_priv *priv,
0484                        union i2c_smbus_data *data,
0485                        char read_write, int command)
0486 {
0487     int i, len, status, xact;
0488 
0489     switch (command) {
0490     case I2C_SMBUS_BLOCK_PROC_CALL:
0491         xact = I801_BLOCK_PROC_CALL;
0492         break;
0493     case I2C_SMBUS_BLOCK_DATA:
0494         xact = I801_BLOCK_DATA;
0495         break;
0496     default:
0497         return -EOPNOTSUPP;
0498     }
0499 
0500     /* Set block buffer mode */
0501     outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
0502 
0503     inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
0504 
0505     if (read_write == I2C_SMBUS_WRITE) {
0506         len = data->block[0];
0507         outb_p(len, SMBHSTDAT0(priv));
0508         for (i = 0; i < len; i++)
0509             outb_p(data->block[i+1], SMBBLKDAT(priv));
0510     }
0511 
0512     status = i801_transaction(priv, xact);
0513     if (status)
0514         return status;
0515 
0516     if (read_write == I2C_SMBUS_READ ||
0517         command == I2C_SMBUS_BLOCK_PROC_CALL) {
0518         len = inb_p(SMBHSTDAT0(priv));
0519         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
0520             return -EPROTO;
0521 
0522         data->block[0] = len;
0523         for (i = 0; i < len; i++)
0524             data->block[i + 1] = inb_p(SMBBLKDAT(priv));
0525     }
0526     return 0;
0527 }
0528 
0529 static void i801_isr_byte_done(struct i801_priv *priv)
0530 {
0531     if (priv->is_read) {
0532         /* For SMBus block reads, length is received with first byte */
0533         if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
0534             (priv->count == 0)) {
0535             priv->len = inb_p(SMBHSTDAT0(priv));
0536             if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
0537                 dev_err(&priv->pci_dev->dev,
0538                     "Illegal SMBus block read size %d\n",
0539                     priv->len);
0540                 /* FIXME: Recover */
0541                 priv->len = I2C_SMBUS_BLOCK_MAX;
0542             }
0543             priv->data[-1] = priv->len;
0544         }
0545 
0546         /* Read next byte */
0547         if (priv->count < priv->len)
0548             priv->data[priv->count++] = inb(SMBBLKDAT(priv));
0549         else
0550             dev_dbg(&priv->pci_dev->dev,
0551                 "Discarding extra byte on block read\n");
0552 
0553         /* Set LAST_BYTE for last byte of read transaction */
0554         if (priv->count == priv->len - 1)
0555             outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
0556                    SMBHSTCNT(priv));
0557     } else if (priv->count < priv->len - 1) {
0558         /* Write next byte, except for IRQ after last byte */
0559         outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
0560     }
0561 
0562     /* Clear BYTE_DONE to continue with next byte */
0563     outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
0564 }
0565 
0566 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
0567 {
0568     unsigned short addr;
0569 
0570     addr = inb_p(SMBNTFDADD(priv)) >> 1;
0571 
0572     /*
0573      * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
0574      * always returns 0. Our current implementation doesn't provide
0575      * data, so we just ignore it.
0576      */
0577     i2c_handle_smbus_host_notify(&priv->adapter, addr);
0578 
0579     /* clear Host Notify bit and return */
0580     outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
0581     return IRQ_HANDLED;
0582 }
0583 
0584 /*
0585  * There are three kinds of interrupts:
0586  *
0587  * 1) i801 signals transaction completion with one of these interrupts:
0588  *      INTR - Success
0589  *      DEV_ERR - Invalid command, NAK or communication timeout
0590  *      BUS_ERR - SMI# transaction collision
0591  *      FAILED - transaction was canceled due to a KILL request
0592  *    When any of these occur, update ->status and signal completion.
0593  *    ->status must be cleared before kicking off the next transaction.
0594  *
0595  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
0596  *    occurs for each byte of a byte-by-byte to prepare the next byte.
0597  *
0598  * 3) Host Notify interrupts
0599  */
0600 static irqreturn_t i801_isr(int irq, void *dev_id)
0601 {
0602     struct i801_priv *priv = dev_id;
0603     u16 pcists;
0604     u8 status;
0605 
0606     /* Confirm this is our interrupt */
0607     pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
0608     if (!(pcists & PCI_STATUS_INTERRUPT))
0609         return IRQ_NONE;
0610 
0611     if (priv->features & FEATURE_HOST_NOTIFY) {
0612         status = inb_p(SMBSLVSTS(priv));
0613         if (status & SMBSLVSTS_HST_NTFY_STS)
0614             return i801_host_notify_isr(priv);
0615     }
0616 
0617     status = inb_p(SMBHSTSTS(priv));
0618     if (status & SMBHSTSTS_BYTE_DONE)
0619         i801_isr_byte_done(priv);
0620 
0621     /*
0622      * Clear remaining IRQ sources: Completion of last command, errors
0623      * and the SMB_ALERT signal. SMB_ALERT status is set after signal
0624      * assertion independently of the interrupt generation being blocked
0625      * or not so clear it always when the status is set.
0626      */
0627     status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS | SMBHSTSTS_SMBALERT_STS;
0628     if (status)
0629         outb_p(status, SMBHSTSTS(priv));
0630     status &= ~SMBHSTSTS_SMBALERT_STS; /* SMB_ALERT not reported */
0631     /*
0632      * Report transaction result.
0633      * ->status must be cleared before the next transaction is started.
0634      */
0635     if (status) {
0636         priv->status = status;
0637         complete(&priv->done);
0638     }
0639 
0640     return IRQ_HANDLED;
0641 }
0642 
0643 /*
0644  * For "byte-by-byte" block transactions:
0645  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
0646  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
0647  */
0648 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
0649                            union i2c_smbus_data *data,
0650                            char read_write, int command)
0651 {
0652     int i, len;
0653     int smbcmd;
0654     int status;
0655     unsigned long result;
0656     const struct i2c_adapter *adap = &priv->adapter;
0657 
0658     if (command == I2C_SMBUS_BLOCK_PROC_CALL)
0659         return -EOPNOTSUPP;
0660 
0661     status = i801_check_pre(priv);
0662     if (status < 0)
0663         return status;
0664 
0665     len = data->block[0];
0666 
0667     if (read_write == I2C_SMBUS_WRITE) {
0668         outb_p(len, SMBHSTDAT0(priv));
0669         outb_p(data->block[1], SMBBLKDAT(priv));
0670     }
0671 
0672     if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
0673         read_write == I2C_SMBUS_READ)
0674         smbcmd = I801_I2C_BLOCK_DATA;
0675     else
0676         smbcmd = I801_BLOCK_DATA;
0677 
0678     if (priv->features & FEATURE_IRQ) {
0679         priv->is_read = (read_write == I2C_SMBUS_READ);
0680         if (len == 1 && priv->is_read)
0681             smbcmd |= SMBHSTCNT_LAST_BYTE;
0682         priv->cmd = smbcmd | SMBHSTCNT_INTREN;
0683         priv->len = len;
0684         priv->count = 0;
0685         priv->data = &data->block[1];
0686 
0687         reinit_completion(&priv->done);
0688         outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
0689         result = wait_for_completion_timeout(&priv->done, adap->timeout);
0690         return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
0691     }
0692 
0693     for (i = 1; i <= len; i++) {
0694         if (i == len && read_write == I2C_SMBUS_READ)
0695             smbcmd |= SMBHSTCNT_LAST_BYTE;
0696         outb_p(smbcmd, SMBHSTCNT(priv));
0697 
0698         if (i == 1)
0699             outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
0700                    SMBHSTCNT(priv));
0701 
0702         status = i801_wait_byte_done(priv);
0703         if (status)
0704             goto exit;
0705 
0706         if (i == 1 && read_write == I2C_SMBUS_READ
0707          && command != I2C_SMBUS_I2C_BLOCK_DATA) {
0708             len = inb_p(SMBHSTDAT0(priv));
0709             if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
0710                 dev_err(&priv->pci_dev->dev,
0711                     "Illegal SMBus block read size %d\n",
0712                     len);
0713                 /* Recover */
0714                 while (inb_p(SMBHSTSTS(priv)) &
0715                        SMBHSTSTS_HOST_BUSY)
0716                     outb_p(SMBHSTSTS_BYTE_DONE,
0717                            SMBHSTSTS(priv));
0718                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
0719                 return -EPROTO;
0720             }
0721             data->block[0] = len;
0722         }
0723 
0724         /* Retrieve/store value in SMBBLKDAT */
0725         if (read_write == I2C_SMBUS_READ)
0726             data->block[i] = inb_p(SMBBLKDAT(priv));
0727         if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
0728             outb_p(data->block[i+1], SMBBLKDAT(priv));
0729 
0730         /* signals SMBBLKDAT ready */
0731         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
0732     }
0733 
0734     status = i801_wait_intr(priv);
0735 exit:
0736     return i801_check_post(priv, status);
0737 }
0738 
0739 /* Block transaction function */
0740 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
0741                   char read_write, int command)
0742 {
0743     int result = 0;
0744     unsigned char hostc;
0745 
0746     if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
0747         data->block[0] = I2C_SMBUS_BLOCK_MAX;
0748     else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
0749         return -EPROTO;
0750 
0751     if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
0752         if (read_write == I2C_SMBUS_WRITE) {
0753             /* set I2C_EN bit in configuration register */
0754             pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
0755             pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
0756                           hostc | SMBHSTCFG_I2C_EN);
0757         } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
0758             dev_err(&priv->pci_dev->dev,
0759                 "I2C block read is unsupported!\n");
0760             return -EOPNOTSUPP;
0761         }
0762     }
0763 
0764     /* Experience has shown that the block buffer can only be used for
0765        SMBus (not I2C) block transactions, even though the datasheet
0766        doesn't mention this limitation. */
0767     if ((priv->features & FEATURE_BLOCK_BUFFER) &&
0768         command != I2C_SMBUS_I2C_BLOCK_DATA)
0769         result = i801_block_transaction_by_block(priv, data,
0770                              read_write,
0771                              command);
0772     else
0773         result = i801_block_transaction_byte_by_byte(priv, data,
0774                                  read_write,
0775                                  command);
0776 
0777     if (command == I2C_SMBUS_I2C_BLOCK_DATA
0778      && read_write == I2C_SMBUS_WRITE) {
0779         /* restore saved configuration register value */
0780         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
0781     }
0782     return result;
0783 }
0784 
0785 /* Return negative errno on error. */
0786 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
0787                unsigned short flags, char read_write, u8 command,
0788                int size, union i2c_smbus_data *data)
0789 {
0790     int hwpec;
0791     int block = 0;
0792     int ret, xact;
0793     struct i801_priv *priv = i2c_get_adapdata(adap);
0794 
0795     mutex_lock(&priv->acpi_lock);
0796     if (priv->acpi_reserved) {
0797         mutex_unlock(&priv->acpi_lock);
0798         return -EBUSY;
0799     }
0800 
0801     pm_runtime_get_sync(&priv->pci_dev->dev);
0802 
0803     hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
0804         && size != I2C_SMBUS_QUICK
0805         && size != I2C_SMBUS_I2C_BLOCK_DATA;
0806 
0807     switch (size) {
0808     case I2C_SMBUS_QUICK:
0809         outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0810                SMBHSTADD(priv));
0811         xact = I801_QUICK;
0812         break;
0813     case I2C_SMBUS_BYTE:
0814         outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0815                SMBHSTADD(priv));
0816         if (read_write == I2C_SMBUS_WRITE)
0817             outb_p(command, SMBHSTCMD(priv));
0818         xact = I801_BYTE;
0819         break;
0820     case I2C_SMBUS_BYTE_DATA:
0821         outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0822                SMBHSTADD(priv));
0823         outb_p(command, SMBHSTCMD(priv));
0824         if (read_write == I2C_SMBUS_WRITE)
0825             outb_p(data->byte, SMBHSTDAT0(priv));
0826         xact = I801_BYTE_DATA;
0827         break;
0828     case I2C_SMBUS_WORD_DATA:
0829         outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0830                SMBHSTADD(priv));
0831         outb_p(command, SMBHSTCMD(priv));
0832         if (read_write == I2C_SMBUS_WRITE) {
0833             outb_p(data->word & 0xff, SMBHSTDAT0(priv));
0834             outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
0835         }
0836         xact = I801_WORD_DATA;
0837         break;
0838     case I2C_SMBUS_PROC_CALL:
0839         outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
0840         outb_p(command, SMBHSTCMD(priv));
0841         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
0842         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
0843         xact = I801_PROC_CALL;
0844         read_write = I2C_SMBUS_READ;
0845         break;
0846     case I2C_SMBUS_BLOCK_DATA:
0847         outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
0848                SMBHSTADD(priv));
0849         outb_p(command, SMBHSTCMD(priv));
0850         block = 1;
0851         break;
0852     case I2C_SMBUS_I2C_BLOCK_DATA:
0853         /*
0854          * NB: page 240 of ICH5 datasheet shows that the R/#W
0855          * bit should be cleared here, even when reading.
0856          * However if SPD Write Disable is set (Lynx Point and later),
0857          * the read will fail if we don't set the R/#W bit.
0858          */
0859         outb_p(((addr & 0x7f) << 1) |
0860                ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
0861             (read_write & 0x01) : 0),
0862                SMBHSTADD(priv));
0863         if (read_write == I2C_SMBUS_READ) {
0864             /* NB: page 240 of ICH5 datasheet also shows
0865              * that DATA1 is the cmd field when reading */
0866             outb_p(command, SMBHSTDAT1(priv));
0867         } else
0868             outb_p(command, SMBHSTCMD(priv));
0869         block = 1;
0870         break;
0871     case I2C_SMBUS_BLOCK_PROC_CALL:
0872         /*
0873          * Bit 0 of the slave address register always indicate a write
0874          * command.
0875          */
0876         outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
0877         outb_p(command, SMBHSTCMD(priv));
0878         block = 1;
0879         break;
0880     default:
0881         dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
0882             size);
0883         ret = -EOPNOTSUPP;
0884         goto out;
0885     }
0886 
0887     if (hwpec)  /* enable/disable hardware PEC */
0888         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
0889     else
0890         outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
0891                SMBAUXCTL(priv));
0892 
0893     if (block)
0894         ret = i801_block_transaction(priv, data, read_write, size);
0895     else
0896         ret = i801_transaction(priv, xact);
0897 
0898     /* Some BIOSes don't like it when PEC is enabled at reboot or resume
0899        time, so we forcibly disable it after every transaction. Turn off
0900        E32B for the same reason. */
0901     if (hwpec || block)
0902         outb_p(inb_p(SMBAUXCTL(priv)) &
0903                ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
0904 
0905     if (block)
0906         goto out;
0907     if (ret)
0908         goto out;
0909     if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
0910         goto out;
0911 
0912     switch (xact) {
0913     case I801_BYTE: /* Result put in SMBHSTDAT0 */
0914     case I801_BYTE_DATA:
0915         data->byte = inb_p(SMBHSTDAT0(priv));
0916         break;
0917     case I801_WORD_DATA:
0918     case I801_PROC_CALL:
0919         data->word = inb_p(SMBHSTDAT0(priv)) +
0920                  (inb_p(SMBHSTDAT1(priv)) << 8);
0921         break;
0922     }
0923 
0924 out:
0925     /*
0926      * Unlock the SMBus device for use by BIOS/ACPI,
0927      * and clear status flags if not done already.
0928      */
0929     outb_p(SMBHSTSTS_INUSE_STS | STATUS_FLAGS, SMBHSTSTS(priv));
0930 
0931     pm_runtime_mark_last_busy(&priv->pci_dev->dev);
0932     pm_runtime_put_autosuspend(&priv->pci_dev->dev);
0933     mutex_unlock(&priv->acpi_lock);
0934     return ret;
0935 }
0936 
0937 
0938 static u32 i801_func(struct i2c_adapter *adapter)
0939 {
0940     struct i801_priv *priv = i2c_get_adapdata(adapter);
0941 
0942     return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
0943            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
0944            I2C_FUNC_SMBUS_PROC_CALL |
0945            I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
0946            ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
0947            ((priv->features & FEATURE_BLOCK_PROC) ?
0948         I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
0949            ((priv->features & FEATURE_I2C_BLOCK_READ) ?
0950         I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
0951            ((priv->features & FEATURE_HOST_NOTIFY) ?
0952         I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
0953 }
0954 
0955 static void i801_enable_host_notify(struct i2c_adapter *adapter)
0956 {
0957     struct i801_priv *priv = i2c_get_adapdata(adapter);
0958 
0959     if (!(priv->features & FEATURE_HOST_NOTIFY))
0960         return;
0961 
0962     /*
0963      * Enable host notify interrupt and block the generation of interrupt
0964      * from the SMB_ALERT signal because the driver does not support
0965      * SMBus Alert.
0966      */
0967     outb_p(SMBSLVCMD_HST_NTFY_INTREN | SMBSLVCMD_SMBALERT_DISABLE |
0968            priv->original_slvcmd, SMBSLVCMD(priv));
0969 
0970     /* clear Host Notify bit to allow a new notification */
0971     outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
0972 }
0973 
0974 static void i801_disable_host_notify(struct i801_priv *priv)
0975 {
0976     if (!(priv->features & FEATURE_HOST_NOTIFY))
0977         return;
0978 
0979     outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
0980 }
0981 
0982 static const struct i2c_algorithm smbus_algorithm = {
0983     .smbus_xfer = i801_access,
0984     .functionality  = i801_func,
0985 };
0986 
0987 #define FEATURES_ICH5   (FEATURE_BLOCK_PROC | FEATURE_I2C_BLOCK_READ    | \
0988              FEATURE_IRQ | FEATURE_SMBUS_PEC        | \
0989              FEATURE_BLOCK_BUFFER | FEATURE_HOST_NOTIFY)
0990 #define FEATURES_ICH4   (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER | \
0991              FEATURE_HOST_NOTIFY)
0992 
0993 static const struct pci_device_id i801_ids[] = {
0994     { PCI_DEVICE_DATA(INTEL, 82801AA_3,     0)               },
0995     { PCI_DEVICE_DATA(INTEL, 82801AB_3,     0)               },
0996     { PCI_DEVICE_DATA(INTEL, 82801BA_2,     0)               },
0997     { PCI_DEVICE_DATA(INTEL, 82801CA_3,     FEATURE_HOST_NOTIFY)         },
0998     { PCI_DEVICE_DATA(INTEL, 82801DB_3,     FEATURES_ICH4)           },
0999     { PCI_DEVICE_DATA(INTEL, 82801EB_3,     FEATURES_ICH5)           },
1000     { PCI_DEVICE_DATA(INTEL, ESB_4,         FEATURES_ICH5)           },
1001     { PCI_DEVICE_DATA(INTEL, ICH6_16,       FEATURES_ICH5)           },
1002     { PCI_DEVICE_DATA(INTEL, ICH7_17,       FEATURES_ICH5)           },
1003     { PCI_DEVICE_DATA(INTEL, ESB2_17,       FEATURES_ICH5)           },
1004     { PCI_DEVICE_DATA(INTEL, ICH8_5,        FEATURES_ICH5)           },
1005     { PCI_DEVICE_DATA(INTEL, ICH9_6,        FEATURES_ICH5)           },
1006     { PCI_DEVICE_DATA(INTEL, EP80579_1,     FEATURES_ICH5)           },
1007     { PCI_DEVICE_DATA(INTEL, ICH10_4,       FEATURES_ICH5)           },
1008     { PCI_DEVICE_DATA(INTEL, ICH10_5,       FEATURES_ICH5)           },
1009     { PCI_DEVICE_DATA(INTEL, 5_3400_SERIES_SMBUS,   FEATURES_ICH5)           },
1010     { PCI_DEVICE_DATA(INTEL, COUGARPOINT_SMBUS, FEATURES_ICH5)           },
1011     { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS,    FEATURES_ICH5)           },
1012     { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF0,   FEATURES_ICH5 | FEATURE_IDF)     },
1013     { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF1,   FEATURES_ICH5 | FEATURE_IDF)     },
1014     { PCI_DEVICE_DATA(INTEL, PATSBURG_SMBUS_IDF2,   FEATURES_ICH5 | FEATURE_IDF)     },
1015     { PCI_DEVICE_DATA(INTEL, DH89XXCC_SMBUS,    FEATURES_ICH5)           },
1016     { PCI_DEVICE_DATA(INTEL, PANTHERPOINT_SMBUS,    FEATURES_ICH5)           },
1017     { PCI_DEVICE_DATA(INTEL, LYNXPOINT_SMBUS,   FEATURES_ICH5)           },
1018     { PCI_DEVICE_DATA(INTEL, LYNXPOINT_LP_SMBUS,    FEATURES_ICH5)           },
1019     { PCI_DEVICE_DATA(INTEL, AVOTON_SMBUS,      FEATURES_ICH5)           },
1020     { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS,   FEATURES_ICH5)           },
1021     { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS0,   FEATURES_ICH5 | FEATURE_IDF)     },
1022     { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS1,   FEATURES_ICH5 | FEATURE_IDF)     },
1023     { PCI_DEVICE_DATA(INTEL, WELLSBURG_SMBUS_MS2,   FEATURES_ICH5 | FEATURE_IDF)     },
1024     { PCI_DEVICE_DATA(INTEL, COLETOCREEK_SMBUS, FEATURES_ICH5)           },
1025     { PCI_DEVICE_DATA(INTEL, GEMINILAKE_SMBUS,  FEATURES_ICH5)           },
1026     { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_SMBUS,    FEATURES_ICH5)           },
1027     { PCI_DEVICE_DATA(INTEL, WILDCATPOINT_LP_SMBUS, FEATURES_ICH5)           },
1028     { PCI_DEVICE_DATA(INTEL, BAYTRAIL_SMBUS,    FEATURES_ICH5)           },
1029     { PCI_DEVICE_DATA(INTEL, BRASWELL_SMBUS,    FEATURES_ICH5)           },
1030     { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1031     { PCI_DEVICE_DATA(INTEL, SUNRISEPOINT_LP_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1032     { PCI_DEVICE_DATA(INTEL, CDF_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1033     { PCI_DEVICE_DATA(INTEL, DNV_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_SPT) },
1034     { PCI_DEVICE_DATA(INTEL, EBG_SMBUS,     FEATURES_ICH5 | FEATURE_TCO_CNL) },
1035     { PCI_DEVICE_DATA(INTEL, BROXTON_SMBUS,     FEATURES_ICH5)           },
1036     { PCI_DEVICE_DATA(INTEL, LEWISBURG_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_SPT) },
1037     { PCI_DEVICE_DATA(INTEL, LEWISBURG_SSKU_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1038     { PCI_DEVICE_DATA(INTEL, KABYLAKE_PCH_H_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_SPT) },
1039     { PCI_DEVICE_DATA(INTEL, CANNONLAKE_H_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1040     { PCI_DEVICE_DATA(INTEL, CANNONLAKE_LP_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1041     { PCI_DEVICE_DATA(INTEL, ICELAKE_LP_SMBUS,  FEATURES_ICH5 | FEATURE_TCO_CNL) },
1042     { PCI_DEVICE_DATA(INTEL, ICELAKE_N_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1043     { PCI_DEVICE_DATA(INTEL, COMETLAKE_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1044     { PCI_DEVICE_DATA(INTEL, COMETLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1045     { PCI_DEVICE_DATA(INTEL, COMETLAKE_V_SMBUS, FEATURES_ICH5 | FEATURE_TCO_SPT) },
1046     { PCI_DEVICE_DATA(INTEL, ELKHART_LAKE_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1047     { PCI_DEVICE_DATA(INTEL, TIGERLAKE_LP_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1048     { PCI_DEVICE_DATA(INTEL, TIGERLAKE_H_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1049     { PCI_DEVICE_DATA(INTEL, JASPER_LAKE_SMBUS, FEATURES_ICH5 | FEATURE_TCO_CNL) },
1050     { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_S_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1051     { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_P_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1052     { PCI_DEVICE_DATA(INTEL, ALDER_LAKE_M_SMBUS,    FEATURES_ICH5 | FEATURE_TCO_CNL) },
1053     { PCI_DEVICE_DATA(INTEL, RAPTOR_LAKE_S_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1054     { PCI_DEVICE_DATA(INTEL, METEOR_LAKE_P_SMBUS,   FEATURES_ICH5 | FEATURE_TCO_CNL) },
1055     { 0, }
1056 };
1057 
1058 MODULE_DEVICE_TABLE(pci, i801_ids);
1059 
1060 #if defined CONFIG_X86 && defined CONFIG_DMI
1061 static unsigned char apanel_addr;
1062 
1063 /* Scan the system ROM for the signature "FJKEYINF" */
1064 static __init const void __iomem *bios_signature(const void __iomem *bios)
1065 {
1066     ssize_t offset;
1067     const unsigned char signature[] = "FJKEYINF";
1068 
1069     for (offset = 0; offset < 0x10000; offset += 0x10) {
1070         if (check_signature(bios + offset, signature,
1071                     sizeof(signature)-1))
1072             return bios + offset;
1073     }
1074     return NULL;
1075 }
1076 
1077 static void __init input_apanel_init(void)
1078 {
1079     void __iomem *bios;
1080     const void __iomem *p;
1081 
1082     bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1083     p = bios_signature(bios);
1084     if (p) {
1085         /* just use the first address */
1086         apanel_addr = readb(p + 8 + 3) >> 1;
1087     }
1088     iounmap(bios);
1089 }
1090 
1091 struct dmi_onboard_device_info {
1092     const char *name;
1093     u8 type;
1094     unsigned short i2c_addr;
1095     const char *i2c_type;
1096 };
1097 
1098 static const struct dmi_onboard_device_info dmi_devices[] = {
1099     { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1100     { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1101     { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1102 };
1103 
1104 static void dmi_check_onboard_device(u8 type, const char *name,
1105                      struct i2c_adapter *adap)
1106 {
1107     int i;
1108     struct i2c_board_info info;
1109 
1110     for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1111         /* & ~0x80, ignore enabled/disabled bit */
1112         if ((type & ~0x80) != dmi_devices[i].type)
1113             continue;
1114         if (strcasecmp(name, dmi_devices[i].name))
1115             continue;
1116 
1117         memset(&info, 0, sizeof(struct i2c_board_info));
1118         info.addr = dmi_devices[i].i2c_addr;
1119         strscpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1120         i2c_new_client_device(adap, &info);
1121         break;
1122     }
1123 }
1124 
1125 /* We use our own function to check for onboard devices instead of
1126    dmi_find_device() as some buggy BIOS's have the devices we are interested
1127    in marked as disabled */
1128 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1129 {
1130     int i, count;
1131 
1132     if (dm->type != 10)
1133         return;
1134 
1135     count = (dm->length - sizeof(struct dmi_header)) / 2;
1136     for (i = 0; i < count; i++) {
1137         const u8 *d = (char *)(dm + 1) + (i * 2);
1138         const char *name = ((char *) dm) + dm->length;
1139         u8 type = d[0];
1140         u8 s = d[1];
1141 
1142         if (!s)
1143             continue;
1144         s--;
1145         while (s > 0 && name[0]) {
1146             name += strlen(name) + 1;
1147             s--;
1148         }
1149         if (name[0] == 0) /* Bogus string reference */
1150             continue;
1151 
1152         dmi_check_onboard_device(type, name, adap);
1153     }
1154 }
1155 
1156 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1157 static const char *const acpi_smo8800_ids[] = {
1158     "SMO8800",
1159     "SMO8801",
1160     "SMO8810",
1161     "SMO8811",
1162     "SMO8820",
1163     "SMO8821",
1164     "SMO8830",
1165     "SMO8831",
1166 };
1167 
1168 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1169                          u32 nesting_level,
1170                          void *context,
1171                          void **return_value)
1172 {
1173     struct acpi_device_info *info;
1174     acpi_status status;
1175     char *hid;
1176     int i;
1177 
1178     status = acpi_get_object_info(obj_handle, &info);
1179     if (ACPI_FAILURE(status))
1180         return AE_OK;
1181 
1182     if (!(info->valid & ACPI_VALID_HID))
1183         goto smo88xx_not_found;
1184 
1185     hid = info->hardware_id.string;
1186     if (!hid)
1187         goto smo88xx_not_found;
1188 
1189     i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1190     if (i < 0)
1191         goto smo88xx_not_found;
1192 
1193     kfree(info);
1194 
1195     *return_value = NULL;
1196     return AE_CTRL_TERMINATE;
1197 
1198 smo88xx_not_found:
1199     kfree(info);
1200     return AE_OK;
1201 }
1202 
1203 static bool is_dell_system_with_lis3lv02d(void)
1204 {
1205     void *err = ERR_PTR(-ENOENT);
1206 
1207     if (!dmi_match(DMI_SYS_VENDOR, "Dell Inc."))
1208         return false;
1209 
1210     /*
1211      * Check that ACPI device SMO88xx is present and is functioning.
1212      * Function acpi_get_devices() already filters all ACPI devices
1213      * which are not present or are not functioning.
1214      * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1215      * accelerometer but unfortunately ACPI does not provide any other
1216      * information (like I2C address).
1217      */
1218     acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, &err);
1219 
1220     return !IS_ERR(err);
1221 }
1222 
1223 /*
1224  * Accelerometer's I2C address is not specified in DMI nor ACPI,
1225  * so it is needed to define mapping table based on DMI product names.
1226  */
1227 static const struct {
1228     const char *dmi_product_name;
1229     unsigned short i2c_addr;
1230 } dell_lis3lv02d_devices[] = {
1231     /*
1232      * Dell platform team told us that these Latitude devices have
1233      * ST microelectronics accelerometer at I2C address 0x29.
1234      */
1235     { "Latitude E5250",     0x29 },
1236     { "Latitude E5450",     0x29 },
1237     { "Latitude E5550",     0x29 },
1238     { "Latitude E6440",     0x29 },
1239     { "Latitude E6440 ATG", 0x29 },
1240     { "Latitude E6540",     0x29 },
1241     /*
1242      * Additional individual entries were added after verification.
1243      */
1244     { "Latitude 5480",      0x29 },
1245     { "Vostro V131",        0x1d },
1246 };
1247 
1248 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1249 {
1250     struct i2c_board_info info;
1251     const char *dmi_product_name;
1252     int i;
1253 
1254     dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1255     for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1256         if (strcmp(dmi_product_name,
1257                dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1258             break;
1259     }
1260 
1261     if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1262         dev_warn(&priv->pci_dev->dev,
1263              "Accelerometer lis3lv02d is present on SMBus but its"
1264              " address is unknown, skipping registration\n");
1265         return;
1266     }
1267 
1268     memset(&info, 0, sizeof(struct i2c_board_info));
1269     info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1270     strscpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1271     i2c_new_client_device(&priv->adapter, &info);
1272 }
1273 
1274 /* Register optional slaves */
1275 static void i801_probe_optional_slaves(struct i801_priv *priv)
1276 {
1277     /* Only register slaves on main SMBus channel */
1278     if (priv->features & FEATURE_IDF)
1279         return;
1280 
1281     if (apanel_addr) {
1282         struct i2c_board_info info = {
1283             .addr = apanel_addr,
1284             .type = "fujitsu_apanel",
1285         };
1286 
1287         i2c_new_client_device(&priv->adapter, &info);
1288     }
1289 
1290     if (dmi_name_in_vendors("FUJITSU"))
1291         dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1292 
1293     if (is_dell_system_with_lis3lv02d())
1294         register_dell_lis3lv02d_i2c_device(priv);
1295 
1296     /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1297 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1298     if (!priv->mux_drvdata)
1299 #endif
1300         i2c_register_spd(&priv->adapter);
1301 }
1302 #else
1303 static void __init input_apanel_init(void) {}
1304 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1305 #endif  /* CONFIG_X86 && CONFIG_DMI */
1306 
1307 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1308 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1309     .gpio_chip = "gpio_ich",
1310     .values = { 0x02, 0x03 },
1311     .n_values = 2,
1312     .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1313     .gpios = { 52, 53 },
1314     .n_gpios = 2,
1315 };
1316 
1317 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1318     .gpio_chip = "gpio_ich",
1319     .values = { 0x02, 0x03, 0x01 },
1320     .n_values = 3,
1321     .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1322     .gpios = { 52, 53 },
1323     .n_gpios = 2,
1324 };
1325 
1326 static const struct dmi_system_id mux_dmi_table[] = {
1327     {
1328         .matches = {
1329             DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1330             DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1331         },
1332         .driver_data = &i801_mux_config_asus_z8_d12,
1333     },
1334     {
1335         .matches = {
1336             DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1337             DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1338         },
1339         .driver_data = &i801_mux_config_asus_z8_d12,
1340     },
1341     {
1342         .matches = {
1343             DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1344             DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1345         },
1346         .driver_data = &i801_mux_config_asus_z8_d12,
1347     },
1348     {
1349         .matches = {
1350             DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1351             DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1352         },
1353         .driver_data = &i801_mux_config_asus_z8_d12,
1354     },
1355     {
1356         .matches = {
1357             DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1358             DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1359         },
1360         .driver_data = &i801_mux_config_asus_z8_d12,
1361     },
1362     {
1363         .matches = {
1364             DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1365             DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1366         },
1367         .driver_data = &i801_mux_config_asus_z8_d12,
1368     },
1369     {
1370         .matches = {
1371             DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1372             DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1373         },
1374         .driver_data = &i801_mux_config_asus_z8_d18,
1375     },
1376     {
1377         .matches = {
1378             DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1379             DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1380         },
1381         .driver_data = &i801_mux_config_asus_z8_d18,
1382     },
1383     {
1384         .matches = {
1385             DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1386             DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1387         },
1388         .driver_data = &i801_mux_config_asus_z8_d12,
1389     },
1390     { }
1391 };
1392 
1393 /* Setup multiplexing if needed */
1394 static void i801_add_mux(struct i801_priv *priv)
1395 {
1396     struct device *dev = &priv->adapter.dev;
1397     const struct i801_mux_config *mux_config;
1398     struct i2c_mux_gpio_platform_data gpio_data;
1399     struct gpiod_lookup_table *lookup;
1400     int i;
1401 
1402     if (!priv->mux_drvdata)
1403         return;
1404     mux_config = priv->mux_drvdata;
1405 
1406     /* Prepare the platform data */
1407     memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1408     gpio_data.parent = priv->adapter.nr;
1409     gpio_data.values = mux_config->values;
1410     gpio_data.n_values = mux_config->n_values;
1411     gpio_data.classes = mux_config->classes;
1412     gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1413 
1414     /* Register GPIO descriptor lookup table */
1415     lookup = devm_kzalloc(dev,
1416                   struct_size(lookup, table, mux_config->n_gpios + 1),
1417                   GFP_KERNEL);
1418     if (!lookup)
1419         return;
1420     lookup->dev_id = "i2c-mux-gpio";
1421     for (i = 0; i < mux_config->n_gpios; i++)
1422         lookup->table[i] = GPIO_LOOKUP(mux_config->gpio_chip,
1423                            mux_config->gpios[i], "mux", 0);
1424     gpiod_add_lookup_table(lookup);
1425     priv->lookup = lookup;
1426 
1427     /*
1428      * Register the mux device, we use PLATFORM_DEVID_NONE here
1429      * because since we are referring to the GPIO chip by name we are
1430      * anyways in deep trouble if there is more than one of these
1431      * devices, and there should likely only be one platform controller
1432      * hub.
1433      */
1434     priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1435                 PLATFORM_DEVID_NONE, &gpio_data,
1436                 sizeof(struct i2c_mux_gpio_platform_data));
1437     if (IS_ERR(priv->mux_pdev)) {
1438         gpiod_remove_lookup_table(lookup);
1439         dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1440     }
1441 }
1442 
1443 static void i801_del_mux(struct i801_priv *priv)
1444 {
1445     platform_device_unregister(priv->mux_pdev);
1446     gpiod_remove_lookup_table(priv->lookup);
1447 }
1448 
1449 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1450 {
1451     const struct dmi_system_id *id;
1452     const struct i801_mux_config *mux_config;
1453     unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1454     int i;
1455 
1456     id = dmi_first_match(mux_dmi_table);
1457     if (id) {
1458         /* Remove branch classes from trunk */
1459         mux_config = id->driver_data;
1460         for (i = 0; i < mux_config->n_values; i++)
1461             class &= ~mux_config->classes[i];
1462 
1463         /* Remember for later */
1464         priv->mux_drvdata = mux_config;
1465     }
1466 
1467     return class;
1468 }
1469 #else
1470 static inline void i801_add_mux(struct i801_priv *priv) { }
1471 static inline void i801_del_mux(struct i801_priv *priv) { }
1472 
1473 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1474 {
1475     return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1476 }
1477 #endif
1478 
1479 static struct platform_device *
1480 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1481          struct resource *tco_res)
1482 {
1483     static const struct itco_wdt_platform_data pldata = {
1484         .name = "Intel PCH",
1485         .version = 4,
1486     };
1487     struct resource *res;
1488     int ret;
1489 
1490     /*
1491      * We must access the NO_REBOOT bit over the Primary to Sideband
1492      * (P2SB) bridge.
1493      */
1494 
1495     res = &tco_res[1];
1496     ret = p2sb_bar(pci_dev->bus, 0, res);
1497     if (ret)
1498         return ERR_PTR(ret);
1499 
1500     if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1501         res->start += SBREG_SMBCTRL_DNV;
1502     else
1503         res->start += SBREG_SMBCTRL;
1504 
1505     res->end = res->start + 3;
1506 
1507     return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1508                     tco_res, 2, &pldata, sizeof(pldata));
1509 }
1510 
1511 static struct platform_device *
1512 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1513          struct resource *tco_res)
1514 {
1515     static const struct itco_wdt_platform_data pldata = {
1516         .name = "Intel PCH",
1517         .version = 6,
1518     };
1519 
1520     return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1521                          tco_res, 1, &pldata, sizeof(pldata));
1522 }
1523 
1524 static void i801_add_tco(struct i801_priv *priv)
1525 {
1526     struct pci_dev *pci_dev = priv->pci_dev;
1527     struct resource tco_res[2], *res;
1528     u32 tco_base, tco_ctl;
1529 
1530     /* If we have ACPI based watchdog use that instead */
1531     if (acpi_has_watchdog())
1532         return;
1533 
1534     if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1535         return;
1536 
1537     pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1538     pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1539     if (!(tco_ctl & TCOCTL_EN))
1540         return;
1541 
1542     memset(tco_res, 0, sizeof(tco_res));
1543     /*
1544      * Always populate the main iTCO IO resource here. The second entry
1545      * for NO_REBOOT MMIO is filled by the SPT specific function.
1546      */
1547     res = &tco_res[0];
1548     res->start = tco_base & ~1;
1549     res->end = res->start + 32 - 1;
1550     res->flags = IORESOURCE_IO;
1551 
1552     if (priv->features & FEATURE_TCO_CNL)
1553         priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1554     else
1555         priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1556 
1557     if (IS_ERR(priv->tco_pdev))
1558         dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1559 }
1560 
1561 #ifdef CONFIG_ACPI
1562 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1563                       acpi_physical_address address)
1564 {
1565     return address >= priv->smba &&
1566            address <= pci_resource_end(priv->pci_dev, SMBBAR);
1567 }
1568 
1569 static acpi_status
1570 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1571              u64 *value, void *handler_context, void *region_context)
1572 {
1573     struct i801_priv *priv = handler_context;
1574     struct pci_dev *pdev = priv->pci_dev;
1575     acpi_status status;
1576 
1577     /*
1578      * Once BIOS AML code touches the OpRegion we warn and inhibit any
1579      * further access from the driver itself. This device is now owned
1580      * by the system firmware.
1581      */
1582     mutex_lock(&priv->acpi_lock);
1583 
1584     if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1585         priv->acpi_reserved = true;
1586 
1587         dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1588         dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1589 
1590         /*
1591          * BIOS is accessing the host controller so prevent it from
1592          * suspending automatically from now on.
1593          */
1594         pm_runtime_get_sync(&pdev->dev);
1595     }
1596 
1597     if ((function & ACPI_IO_MASK) == ACPI_READ)
1598         status = acpi_os_read_port(address, (u32 *)value, bits);
1599     else
1600         status = acpi_os_write_port(address, (u32)*value, bits);
1601 
1602     mutex_unlock(&priv->acpi_lock);
1603 
1604     return status;
1605 }
1606 
1607 static int i801_acpi_probe(struct i801_priv *priv)
1608 {
1609     acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1610     acpi_status status;
1611 
1612     status = acpi_install_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO,
1613                             i801_acpi_io_handler, NULL, priv);
1614     if (ACPI_SUCCESS(status))
1615         return 0;
1616 
1617     return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1618 }
1619 
1620 static void i801_acpi_remove(struct i801_priv *priv)
1621 {
1622     acpi_handle ah = ACPI_HANDLE(&priv->pci_dev->dev);
1623 
1624     acpi_remove_address_space_handler(ah, ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1625 }
1626 #else
1627 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1628 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1629 #endif
1630 
1631 static void i801_setup_hstcfg(struct i801_priv *priv)
1632 {
1633     unsigned char hstcfg = priv->original_hstcfg;
1634 
1635     hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1636     hstcfg |= SMBHSTCFG_HST_EN;
1637     pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1638 }
1639 
1640 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1641 {
1642     int err, i;
1643     struct i801_priv *priv;
1644 
1645     priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1646     if (!priv)
1647         return -ENOMEM;
1648 
1649     i2c_set_adapdata(&priv->adapter, priv);
1650     priv->adapter.owner = THIS_MODULE;
1651     priv->adapter.class = i801_get_adapter_class(priv);
1652     priv->adapter.algo = &smbus_algorithm;
1653     priv->adapter.dev.parent = &dev->dev;
1654     ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1655     priv->adapter.retries = 3;
1656     mutex_init(&priv->acpi_lock);
1657 
1658     priv->pci_dev = dev;
1659     priv->features = id->driver_data;
1660 
1661     /* Disable features on user request */
1662     for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1663         if (priv->features & disable_features & (1 << i))
1664             dev_notice(&dev->dev, "%s disabled by user\n",
1665                    i801_feature_names[i]);
1666     }
1667     priv->features &= ~disable_features;
1668 
1669     err = pcim_enable_device(dev);
1670     if (err) {
1671         dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1672             err);
1673         return err;
1674     }
1675     pcim_pin_device(dev);
1676 
1677     /* Determine the address of the SMBus area */
1678     priv->smba = pci_resource_start(dev, SMBBAR);
1679     if (!priv->smba) {
1680         dev_err(&dev->dev,
1681             "SMBus base address uninitialized, upgrade BIOS\n");
1682         return -ENODEV;
1683     }
1684 
1685     if (i801_acpi_probe(priv))
1686         return -ENODEV;
1687 
1688     err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1689     if (err) {
1690         dev_err(&dev->dev,
1691             "Failed to request SMBus region 0x%lx-0x%Lx\n",
1692             priv->smba,
1693             (unsigned long long)pci_resource_end(dev, SMBBAR));
1694         i801_acpi_remove(priv);
1695         return err;
1696     }
1697 
1698     pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1699     i801_setup_hstcfg(priv);
1700     if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1701         dev_info(&dev->dev, "Enabling SMBus device\n");
1702 
1703     if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1704         dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1705         /* Disable SMBus interrupt feature if SMBus using SMI# */
1706         priv->features &= ~FEATURE_IRQ;
1707     }
1708     if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1709         dev_info(&dev->dev, "SPD Write Disable is set\n");
1710 
1711     /* Clear special mode bits */
1712     if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1713         outb_p(inb_p(SMBAUXCTL(priv)) &
1714                ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1715 
1716     /* Remember original Interrupt and Host Notify settings */
1717     priv->original_hstcnt = inb_p(SMBHSTCNT(priv)) & ~SMBHSTCNT_KILL;
1718     if (priv->features & FEATURE_HOST_NOTIFY)
1719         priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1720 
1721     /* Default timeout in interrupt mode: 200 ms */
1722     priv->adapter.timeout = HZ / 5;
1723 
1724     if (dev->irq == IRQ_NOTCONNECTED)
1725         priv->features &= ~FEATURE_IRQ;
1726 
1727     if (priv->features & FEATURE_IRQ) {
1728         u16 pcists;
1729 
1730         /* Complain if an interrupt is already pending */
1731         pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1732         if (pcists & PCI_STATUS_INTERRUPT)
1733             dev_warn(&dev->dev, "An interrupt is pending!\n");
1734     }
1735 
1736     if (priv->features & FEATURE_IRQ) {
1737         init_completion(&priv->done);
1738 
1739         err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1740                        IRQF_SHARED, DRV_NAME, priv);
1741         if (err) {
1742             dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1743                 dev->irq, err);
1744             priv->features &= ~FEATURE_IRQ;
1745         }
1746     }
1747     dev_info(&dev->dev, "SMBus using %s\n",
1748          priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1749 
1750     i801_add_tco(priv);
1751 
1752     snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1753         "SMBus I801 adapter at %04lx", priv->smba);
1754     err = i2c_add_adapter(&priv->adapter);
1755     if (err) {
1756         i801_acpi_remove(priv);
1757         return err;
1758     }
1759 
1760     i801_enable_host_notify(&priv->adapter);
1761 
1762     i801_probe_optional_slaves(priv);
1763     /* We ignore errors - multiplexing is optional */
1764     i801_add_mux(priv);
1765 
1766     pci_set_drvdata(dev, priv);
1767 
1768     dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1769     pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1770     pm_runtime_use_autosuspend(&dev->dev);
1771     pm_runtime_put_autosuspend(&dev->dev);
1772     pm_runtime_allow(&dev->dev);
1773 
1774     return 0;
1775 }
1776 
1777 static void i801_remove(struct pci_dev *dev)
1778 {
1779     struct i801_priv *priv = pci_get_drvdata(dev);
1780 
1781     outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1782     i801_disable_host_notify(priv);
1783     i801_del_mux(priv);
1784     i2c_del_adapter(&priv->adapter);
1785     i801_acpi_remove(priv);
1786     pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1787 
1788     platform_device_unregister(priv->tco_pdev);
1789 
1790     /* if acpi_reserved is set then usage_count is incremented already */
1791     if (!priv->acpi_reserved)
1792         pm_runtime_get_noresume(&dev->dev);
1793 
1794     /*
1795      * do not call pci_disable_device(dev) since it can cause hard hangs on
1796      * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1797      */
1798 }
1799 
1800 static void i801_shutdown(struct pci_dev *dev)
1801 {
1802     struct i801_priv *priv = pci_get_drvdata(dev);
1803 
1804     /* Restore config registers to avoid hard hang on some systems */
1805     outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1806     i801_disable_host_notify(priv);
1807     pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1808 }
1809 
1810 #ifdef CONFIG_PM_SLEEP
1811 static int i801_suspend(struct device *dev)
1812 {
1813     struct i801_priv *priv = dev_get_drvdata(dev);
1814 
1815     outb_p(priv->original_hstcnt, SMBHSTCNT(priv));
1816     pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1817     return 0;
1818 }
1819 
1820 static int i801_resume(struct device *dev)
1821 {
1822     struct i801_priv *priv = dev_get_drvdata(dev);
1823 
1824     i801_setup_hstcfg(priv);
1825     i801_enable_host_notify(&priv->adapter);
1826 
1827     return 0;
1828 }
1829 #endif
1830 
1831 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1832 
1833 static struct pci_driver i801_driver = {
1834     .name       = DRV_NAME,
1835     .id_table   = i801_ids,
1836     .probe      = i801_probe,
1837     .remove     = i801_remove,
1838     .shutdown   = i801_shutdown,
1839     .driver     = {
1840         .pm = &i801_pm_ops,
1841     },
1842 };
1843 
1844 static int __init i2c_i801_init(void)
1845 {
1846     if (dmi_name_in_vendors("FUJITSU"))
1847         input_apanel_init();
1848     return pci_register_driver(&i801_driver);
1849 }
1850 
1851 static void __exit i2c_i801_exit(void)
1852 {
1853     pci_unregister_driver(&i801_driver);
1854 }
1855 
1856 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1857 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1858 MODULE_DESCRIPTION("I801 SMBus driver");
1859 MODULE_LICENSE("GPL");
1860 
1861 module_init(i2c_i801_init);
1862 module_exit(i2c_i801_exit);
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