i2c/busses/i2c-hix5hd2.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2014 Linaro Ltd.
0004  * Copyright (c) 2014 HiSilicon Limited.
0005  *
0006  * Now only support 7 bit address.
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/i2c.h>
0012 #include <linux/io.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/pm_runtime.h>
0018
0019 /* Register Map */
0020 #define HIX5I2C_CTRL        0x00
0021 #define HIX5I2C_COM     0x04
0022 #define HIX5I2C_ICR     0x08
0023 #define HIX5I2C_SR      0x0c
0024 #define HIX5I2C_SCL_H       0x10
0025 #define HIX5I2C_SCL_L       0x14
0026 #define HIX5I2C_TXR     0x18
0027 #define HIX5I2C_RXR     0x1c
0028
0029 /* I2C_CTRL_REG */
0030 #define I2C_ENABLE      BIT(8)
0031 #define I2C_UNMASK_TOTAL    BIT(7)
0032 #define I2C_UNMASK_START    BIT(6)
0033 #define I2C_UNMASK_END      BIT(5)
0034 #define I2C_UNMASK_SEND     BIT(4)
0035 #define I2C_UNMASK_RECEIVE  BIT(3)
0036 #define I2C_UNMASK_ACK      BIT(2)
0037 #define I2C_UNMASK_ARBITRATE    BIT(1)
0038 #define I2C_UNMASK_OVER     BIT(0)
0039 #define I2C_UNMASK_ALL      (I2C_UNMASK_ACK | I2C_UNMASK_OVER)
0040
0041 /* I2C_COM_REG */
0042 #define I2C_NO_ACK      BIT(4)
0043 #define I2C_START       BIT(3)
0044 #define I2C_READ        BIT(2)
0045 #define I2C_WRITE       BIT(1)
0046 #define I2C_STOP        BIT(0)
0047
0048 /* I2C_ICR_REG */
0049 #define I2C_CLEAR_START     BIT(6)
0050 #define I2C_CLEAR_END       BIT(5)
0051 #define I2C_CLEAR_SEND      BIT(4)
0052 #define I2C_CLEAR_RECEIVE   BIT(3)
0053 #define I2C_CLEAR_ACK       BIT(2)
0054 #define I2C_CLEAR_ARBITRATE BIT(1)
0055 #define I2C_CLEAR_OVER      BIT(0)
0056 #define I2C_CLEAR_ALL       (I2C_CLEAR_START | I2C_CLEAR_END | \
0057                 I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
0058                 I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
0059                 I2C_CLEAR_OVER)
0060
0061 /* I2C_SR_REG */
0062 #define I2C_BUSY        BIT(7)
0063 #define I2C_START_INTR      BIT(6)
0064 #define I2C_END_INTR        BIT(5)
0065 #define I2C_SEND_INTR       BIT(4)
0066 #define I2C_RECEIVE_INTR    BIT(3)
0067 #define I2C_ACK_INTR        BIT(2)
0068 #define I2C_ARBITRATE_INTR  BIT(1)
0069 #define I2C_OVER_INTR       BIT(0)
0070
0071 enum hix5hd2_i2c_state {
0072     HIX5I2C_STAT_RW_ERR = -1,
0073     HIX5I2C_STAT_INIT,
0074     HIX5I2C_STAT_RW,
0075     HIX5I2C_STAT_SND_STOP,
0076     HIX5I2C_STAT_RW_SUCCESS,
0077 };
0078
0079 struct hix5hd2_i2c_priv {
0080     struct i2c_adapter adap;
0081     struct i2c_msg *msg;
0082     struct completion msg_complete;
0083     unsigned int msg_idx;
0084     unsigned int msg_len;
0085     int stop;
0086     void __iomem *regs;
0087     struct clk *clk;
0088     struct device *dev;
0089     spinlock_t lock;    /* IRQ synchronization */
0090     int err;
0091     unsigned int freq;
0092     enum hix5hd2_i2c_state state;
0093 };
0094
0095 static u32 hix5hd2_i2c_clr_pend_irq(struct hix5hd2_i2c_priv *priv)
0096 {
0097     u32 val = readl_relaxed(priv->regs + HIX5I2C_SR);
0098
0099     writel_relaxed(val, priv->regs + HIX5I2C_ICR);
0100
0101     return val;
0102 }
0103
0104 static void hix5hd2_i2c_clr_all_irq(struct hix5hd2_i2c_priv *priv)
0105 {
0106     writel_relaxed(I2C_CLEAR_ALL, priv->regs + HIX5I2C_ICR);
0107 }
0108
0109 static void hix5hd2_i2c_disable_irq(struct hix5hd2_i2c_priv *priv)
0110 {
0111     writel_relaxed(0, priv->regs + HIX5I2C_CTRL);
0112 }
0113
0114 static void hix5hd2_i2c_enable_irq(struct hix5hd2_i2c_priv *priv)
0115 {
0116     writel_relaxed(I2C_ENABLE | I2C_UNMASK_TOTAL | I2C_UNMASK_ALL,
0117                priv->regs + HIX5I2C_CTRL);
0118 }
0119
0120 static void hix5hd2_i2c_drv_setrate(struct hix5hd2_i2c_priv *priv)
0121 {
0122     u32 rate, val;
0123     u32 scl, sysclock;
0124
0125     /* close all i2c interrupt */
0126     val = readl_relaxed(priv->regs + HIX5I2C_CTRL);
0127     writel_relaxed(val & (~I2C_UNMASK_TOTAL), priv->regs + HIX5I2C_CTRL);
0128
0129     rate = priv->freq;
0130     sysclock = clk_get_rate(priv->clk);
0131     scl = (sysclock / (rate * 2)) / 2 - 1;
0132     writel_relaxed(scl, priv->regs + HIX5I2C_SCL_H);
0133     writel_relaxed(scl, priv->regs + HIX5I2C_SCL_L);
0134
0135     /* restore original interrupt*/
0136     writel_relaxed(val, priv->regs + HIX5I2C_CTRL);
0137
0138     dev_dbg(priv->dev, "%s: sysclock=%d, rate=%d, scl=%d\n",
0139         __func__, sysclock, rate, scl);
0140 }
0141
0142 static void hix5hd2_i2c_init(struct hix5hd2_i2c_priv *priv)
0143 {
0144     hix5hd2_i2c_disable_irq(priv);
0145     hix5hd2_i2c_drv_setrate(priv);
0146     hix5hd2_i2c_clr_all_irq(priv);
0147     hix5hd2_i2c_enable_irq(priv);
0148 }
0149
0150 static void hix5hd2_i2c_reset(struct hix5hd2_i2c_priv *priv)
0151 {
0152     clk_disable_unprepare(priv->clk);
0153     msleep(20);
0154     clk_prepare_enable(priv->clk);
0155     hix5hd2_i2c_init(priv);
0156 }
0157
0158 static int hix5hd2_i2c_wait_bus_idle(struct hix5hd2_i2c_priv *priv)
0159 {
0160     unsigned long stop_time;
0161     u32 int_status;
0162
0163     /* wait for 100 milli seconds for the bus to be idle */
0164     stop_time = jiffies + msecs_to_jiffies(100);
0165     do {
0166         int_status = hix5hd2_i2c_clr_pend_irq(priv);
0167         if (!(int_status & I2C_BUSY))
0168             return 0;
0169
0170         usleep_range(50, 200);
0171     } while (time_before(jiffies, stop_time));
0172
0173     return -EBUSY;
0174 }
0175
0176 static void hix5hd2_rw_over(struct hix5hd2_i2c_priv *priv)
0177 {
0178     if (priv->state == HIX5I2C_STAT_SND_STOP)
0179         dev_dbg(priv->dev, "%s: rw and send stop over\n", __func__);
0180     else
0181         dev_dbg(priv->dev, "%s: have not data to send\n", __func__);
0182
0183     priv->state = HIX5I2C_STAT_RW_SUCCESS;
0184     priv->err = 0;
0185 }
0186
0187 static void hix5hd2_rw_handle_stop(struct hix5hd2_i2c_priv *priv)
0188 {
0189     if (priv->stop) {
0190         priv->state = HIX5I2C_STAT_SND_STOP;
0191         writel_relaxed(I2C_STOP, priv->regs + HIX5I2C_COM);
0192     } else {
0193         hix5hd2_rw_over(priv);
0194     }
0195 }
0196
0197 static void hix5hd2_read_handle(struct hix5hd2_i2c_priv *priv)
0198 {
0199     if (priv->msg_len == 1) {
0200         /* the last byte don't need send ACK */
0201         writel_relaxed(I2C_READ | I2C_NO_ACK, priv->regs + HIX5I2C_COM);
0202     } else if (priv->msg_len > 1) {
0203         /* if i2c master receive data will send ACK */
0204         writel_relaxed(I2C_READ, priv->regs + HIX5I2C_COM);
0205     } else {
0206         hix5hd2_rw_handle_stop(priv);
0207     }
0208 }
0209
0210 static void hix5hd2_write_handle(struct hix5hd2_i2c_priv *priv)
0211 {
0212     u8 data;
0213
0214     if (priv->msg_len > 0) {
0215         data = priv->msg->buf[priv->msg_idx++];
0216         writel_relaxed(data, priv->regs + HIX5I2C_TXR);
0217         writel_relaxed(I2C_WRITE, priv->regs + HIX5I2C_COM);
0218     } else {
0219         hix5hd2_rw_handle_stop(priv);
0220     }
0221 }
0222
0223 static int hix5hd2_rw_preprocess(struct hix5hd2_i2c_priv *priv)
0224 {
0225     u8 data;
0226
0227     if (priv->state == HIX5I2C_STAT_INIT) {
0228         priv->state = HIX5I2C_STAT_RW;
0229     } else if (priv->state == HIX5I2C_STAT_RW) {
0230         if (priv->msg->flags & I2C_M_RD) {
0231             data = readl_relaxed(priv->regs + HIX5I2C_RXR);
0232             priv->msg->buf[priv->msg_idx++] = data;
0233         }
0234         priv->msg_len--;
0235     } else {
0236         dev_dbg(priv->dev, "%s: error: priv->state = %d, msg_len = %d\n",
0237             __func__, priv->state, priv->msg_len);
0238         return -EAGAIN;
0239     }
0240     return 0;
0241 }
0242
0243 static irqreturn_t hix5hd2_i2c_irq(int irqno, void *dev_id)
0244 {
0245     struct hix5hd2_i2c_priv *priv = dev_id;
0246     u32 int_status;
0247     int ret;
0248
0249     spin_lock(&priv->lock);
0250
0251     int_status = hix5hd2_i2c_clr_pend_irq(priv);
0252
0253     /* handle error */
0254     if (int_status & I2C_ARBITRATE_INTR) {
0255         /* bus error */
0256         dev_dbg(priv->dev, "ARB bus loss\n");
0257         priv->err = -EAGAIN;
0258         priv->state = HIX5I2C_STAT_RW_ERR;
0259         goto stop;
0260     } else if (int_status & I2C_ACK_INTR) {
0261         /* ack error */
0262         dev_dbg(priv->dev, "No ACK from device\n");
0263         priv->err = -ENXIO;
0264         priv->state = HIX5I2C_STAT_RW_ERR;
0265         goto stop;
0266     }
0267
0268     if (int_status & I2C_OVER_INTR) {
0269         if (priv->msg_len > 0) {
0270             ret = hix5hd2_rw_preprocess(priv);
0271             if (ret) {
0272                 priv->err = ret;
0273                 priv->state = HIX5I2C_STAT_RW_ERR;
0274                 goto stop;
0275             }
0276             if (priv->msg->flags & I2C_M_RD)
0277                 hix5hd2_read_handle(priv);
0278             else
0279                 hix5hd2_write_handle(priv);
0280         } else {
0281             hix5hd2_rw_over(priv);
0282         }
0283     }
0284
0285 stop:
0286     if ((priv->state == HIX5I2C_STAT_RW_SUCCESS &&
0287          priv->msg->len == priv->msg_idx) ||
0288         (priv->state == HIX5I2C_STAT_RW_ERR)) {
0289         hix5hd2_i2c_disable_irq(priv);
0290         hix5hd2_i2c_clr_pend_irq(priv);
0291         complete(&priv->msg_complete);
0292     }
0293
0294     spin_unlock(&priv->lock);
0295
0296     return IRQ_HANDLED;
0297 }
0298
0299 static void hix5hd2_i2c_message_start(struct hix5hd2_i2c_priv *priv, int stop)
0300 {
0301     unsigned long flags;
0302
0303     spin_lock_irqsave(&priv->lock, flags);
0304     hix5hd2_i2c_clr_all_irq(priv);
0305     hix5hd2_i2c_enable_irq(priv);
0306
0307     writel_relaxed(i2c_8bit_addr_from_msg(priv->msg),
0308                priv->regs + HIX5I2C_TXR);
0309
0310     writel_relaxed(I2C_WRITE | I2C_START, priv->regs + HIX5I2C_COM);
0311     spin_unlock_irqrestore(&priv->lock, flags);
0312 }
0313
0314 static int hix5hd2_i2c_xfer_msg(struct hix5hd2_i2c_priv *priv,
0315                 struct i2c_msg *msgs, int stop)
0316 {
0317     unsigned long timeout;
0318     int ret;
0319
0320     priv->msg = msgs;
0321     priv->msg_idx = 0;
0322     priv->msg_len = priv->msg->len;
0323     priv->stop = stop;
0324     priv->err = 0;
0325     priv->state = HIX5I2C_STAT_INIT;
0326
0327     reinit_completion(&priv->msg_complete);
0328     hix5hd2_i2c_message_start(priv, stop);
0329
0330     timeout = wait_for_completion_timeout(&priv->msg_complete,
0331                           priv->adap.timeout);
0332     if (timeout == 0) {
0333         priv->state = HIX5I2C_STAT_RW_ERR;
0334         priv->err = -ETIMEDOUT;
0335         dev_warn(priv->dev, "%s timeout=%d\n",
0336              msgs->flags & I2C_M_RD ? "rx" : "tx",
0337              priv->adap.timeout);
0338     }
0339     ret = priv->state;
0340
0341     /*
0342      * If this is the last message to be transfered (stop == 1)
0343      * Then check if the bus can be brought back to idle.
0344      */
0345     if (priv->state == HIX5I2C_STAT_RW_SUCCESS && stop)
0346         ret = hix5hd2_i2c_wait_bus_idle(priv);
0347
0348     if (ret < 0)
0349         hix5hd2_i2c_reset(priv);
0350
0351     return priv->err;
0352 }
0353
0354 static int hix5hd2_i2c_xfer(struct i2c_adapter *adap,
0355                 struct i2c_msg *msgs, int num)
0356 {
0357     struct hix5hd2_i2c_priv *priv = i2c_get_adapdata(adap);
0358     int i, ret, stop;
0359
0360     pm_runtime_get_sync(priv->dev);
0361
0362     for (i = 0; i < num; i++, msgs++) {
0363         stop = (i == num - 1);
0364         ret = hix5hd2_i2c_xfer_msg(priv, msgs, stop);
0365         if (ret < 0)
0366             goto out;
0367     }
0368
0369     ret = num;
0370
0371 out:
0372     pm_runtime_mark_last_busy(priv->dev);
0373     pm_runtime_put_autosuspend(priv->dev);
0374     return ret;
0375 }
0376
0377 static u32 hix5hd2_i2c_func(struct i2c_adapter *adap)
0378 {
0379     return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
0380 }
0381
0382 static const struct i2c_algorithm hix5hd2_i2c_algorithm = {
0383     .master_xfer        = hix5hd2_i2c_xfer,
0384     .functionality      = hix5hd2_i2c_func,
0385 };
0386
0387 static int hix5hd2_i2c_probe(struct platform_device *pdev)
0388 {
0389     struct device_node *np = pdev->dev.of_node;
0390     struct hix5hd2_i2c_priv *priv;
0391     unsigned int freq;
0392     int irq, ret;
0393
0394     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0395     if (!priv)
0396         return -ENOMEM;
0397
0398     if (of_property_read_u32(np, "clock-frequency", &freq)) {
0399         /* use 100k as default value */
0400         priv->freq = I2C_MAX_STANDARD_MODE_FREQ;
0401     } else {
0402         if (freq > I2C_MAX_FAST_MODE_FREQ) {
0403             priv->freq = I2C_MAX_FAST_MODE_FREQ;
0404             dev_warn(priv->dev, "use max freq %d instead\n",
0405                  I2C_MAX_FAST_MODE_FREQ);
0406         } else {
0407             priv->freq = freq;
0408         }
0409     }
0410
0411     priv->regs = devm_platform_ioremap_resource(pdev, 0);
0412     if (IS_ERR(priv->regs))
0413         return PTR_ERR(priv->regs);
0414
0415     irq = platform_get_irq(pdev, 0);
0416     if (irq < 0)
0417         return irq;
0418
0419     priv->clk = devm_clk_get(&pdev->dev, NULL);
0420     if (IS_ERR(priv->clk)) {
0421         dev_err(&pdev->dev, "cannot get clock\n");
0422         return PTR_ERR(priv->clk);
0423     }
0424     clk_prepare_enable(priv->clk);
0425
0426     strscpy(priv->adap.name, "hix5hd2-i2c", sizeof(priv->adap.name));
0427     priv->dev = &pdev->dev;
0428     priv->adap.owner = THIS_MODULE;
0429     priv->adap.algo = &hix5hd2_i2c_algorithm;
0430     priv->adap.retries = 3;
0431     priv->adap.dev.of_node = np;
0432     priv->adap.algo_data = priv;
0433     priv->adap.dev.parent = &pdev->dev;
0434     i2c_set_adapdata(&priv->adap, priv);
0435     platform_set_drvdata(pdev, priv);
0436     spin_lock_init(&priv->lock);
0437     init_completion(&priv->msg_complete);
0438
0439     hix5hd2_i2c_init(priv);
0440
0441     ret = devm_request_irq(&pdev->dev, irq, hix5hd2_i2c_irq,
0442                    IRQF_NO_SUSPEND, dev_name(&pdev->dev), priv);
0443     if (ret != 0) {
0444         dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", irq);
0445         goto err_clk;
0446     }
0447
0448     pm_runtime_set_autosuspend_delay(priv->dev, MSEC_PER_SEC);
0449     pm_runtime_use_autosuspend(priv->dev);
0450     pm_runtime_set_active(priv->dev);
0451     pm_runtime_enable(priv->dev);
0452
0453     ret = i2c_add_adapter(&priv->adap);
0454     if (ret < 0)
0455         goto err_runtime;
0456
0457     return ret;
0458
0459 err_runtime:
0460     pm_runtime_disable(priv->dev);
0461     pm_runtime_set_suspended(priv->dev);
0462 err_clk:
0463     clk_disable_unprepare(priv->clk);
0464     return ret;
0465 }
0466
0467 static int hix5hd2_i2c_remove(struct platform_device *pdev)
0468 {
0469     struct hix5hd2_i2c_priv *priv = platform_get_drvdata(pdev);
0470
0471     i2c_del_adapter(&priv->adap);
0472     pm_runtime_disable(priv->dev);
0473     pm_runtime_set_suspended(priv->dev);
0474     clk_disable_unprepare(priv->clk);
0475
0476     return 0;
0477 }
0478
0479 #ifdef CONFIG_PM
0480 static int hix5hd2_i2c_runtime_suspend(struct device *dev)
0481 {
0482     struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
0483
0484     clk_disable_unprepare(priv->clk);
0485
0486     return 0;
0487 }
0488
0489 static int hix5hd2_i2c_runtime_resume(struct device *dev)
0490 {
0491     struct hix5hd2_i2c_priv *priv = dev_get_drvdata(dev);
0492
0493     clk_prepare_enable(priv->clk);
0494     hix5hd2_i2c_init(priv);
0495
0496     return 0;
0497 }
0498 #endif
0499
0500 static const struct dev_pm_ops hix5hd2_i2c_pm_ops = {
0501     SET_RUNTIME_PM_OPS(hix5hd2_i2c_runtime_suspend,
0502                   hix5hd2_i2c_runtime_resume,
0503                   NULL)
0504 };
0505
0506 static const struct of_device_id hix5hd2_i2c_match[] = {
0507     { .compatible = "hisilicon,hix5hd2-i2c" },
0508     {},
0509 };
0510 MODULE_DEVICE_TABLE(of, hix5hd2_i2c_match);
0511
0512 static struct platform_driver hix5hd2_i2c_driver = {
0513     .probe      = hix5hd2_i2c_probe,
0514     .remove     = hix5hd2_i2c_remove,
0515     .driver     = {
0516         .name   = "hix5hd2-i2c",
0517         .pm = &hix5hd2_i2c_pm_ops,
0518         .of_match_table = hix5hd2_i2c_match,
0519     },
0520 };
0521
0522 module_platform_driver(hix5hd2_i2c_driver);
0523
0524 MODULE_DESCRIPTION("Hix5hd2 I2C Bus driver");
0525 MODULE_AUTHOR("Wei Yan <sledge.yanwei@huawei.com>");
0526 MODULE_LICENSE("GPL");
0527 MODULE_ALIAS("platform:hix5hd2-i2c");