i2c/busses/i2c-hisi.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * HiSilicon I2C Controller Driver for Kunpeng SoC
0004  *
0005  * Copyright (c) 2021 HiSilicon Technologies Co., Ltd.
0006  */
0007
0008 #include <linux/bits.h>
0009 #include <linux/bitfield.h>
0010 #include <linux/completion.h>
0011 #include <linux/i2c.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/property.h>
0018 #include <linux/units.h>
0019
0020 #define HISI_I2C_FRAME_CTRL     0x0000
0021 #define   HISI_I2C_FRAME_CTRL_SPEED_MODE    GENMASK(1, 0)
0022 #define   HISI_I2C_FRAME_CTRL_ADDR_TEN  BIT(2)
0023 #define HISI_I2C_SLV_ADDR       0x0004
0024 #define   HISI_I2C_SLV_ADDR_VAL     GENMASK(9, 0)
0025 #define   HISI_I2C_SLV_ADDR_GC_S_MODE   BIT(10)
0026 #define   HISI_I2C_SLV_ADDR_GC_S_EN BIT(11)
0027 #define HISI_I2C_CMD_TXDATA     0x0008
0028 #define   HISI_I2C_CMD_TXDATA_DATA  GENMASK(7, 0)
0029 #define   HISI_I2C_CMD_TXDATA_RW    BIT(8)
0030 #define   HISI_I2C_CMD_TXDATA_P_EN  BIT(9)
0031 #define   HISI_I2C_CMD_TXDATA_SR_EN BIT(10)
0032 #define HISI_I2C_RXDATA         0x000c
0033 #define   HISI_I2C_RXDATA_DATA      GENMASK(7, 0)
0034 #define HISI_I2C_SS_SCL_HCNT        0x0010
0035 #define HISI_I2C_SS_SCL_LCNT        0x0014
0036 #define HISI_I2C_FS_SCL_HCNT        0x0018
0037 #define HISI_I2C_FS_SCL_LCNT        0x001c
0038 #define HISI_I2C_HS_SCL_HCNT        0x0020
0039 #define HISI_I2C_HS_SCL_LCNT        0x0024
0040 #define HISI_I2C_FIFO_CTRL      0x0028
0041 #define   HISI_I2C_FIFO_RX_CLR      BIT(0)
0042 #define   HISI_I2C_FIFO_TX_CLR      BIT(1)
0043 #define   HISI_I2C_FIFO_RX_AF_THRESH    GENMASK(7, 2)
0044 #define   HISI_I2C_FIFO_TX_AE_THRESH    GENMASK(13, 8)
0045 #define HISI_I2C_FIFO_STATE     0x002c
0046 #define   HISI_I2C_FIFO_STATE_RX_RERR   BIT(0)
0047 #define   HISI_I2C_FIFO_STATE_RX_WERR   BIT(1)
0048 #define   HISI_I2C_FIFO_STATE_RX_EMPTY  BIT(3)
0049 #define   HISI_I2C_FIFO_STATE_TX_RERR   BIT(6)
0050 #define   HISI_I2C_FIFO_STATE_TX_WERR   BIT(7)
0051 #define   HISI_I2C_FIFO_STATE_TX_FULL   BIT(11)
0052 #define HISI_I2C_SDA_HOLD       0x0030
0053 #define   HISI_I2C_SDA_HOLD_TX      GENMASK(15, 0)
0054 #define   HISI_I2C_SDA_HOLD_RX      GENMASK(23, 16)
0055 #define HISI_I2C_FS_SPK_LEN     0x0038
0056 #define   HISI_I2C_FS_SPK_LEN_CNT   GENMASK(7, 0)
0057 #define HISI_I2C_HS_SPK_LEN     0x003c
0058 #define   HISI_I2C_HS_SPK_LEN_CNT   GENMASK(7, 0)
0059 #define HISI_I2C_INT_MSTAT      0x0044
0060 #define HISI_I2C_INT_CLR        0x0048
0061 #define HISI_I2C_INT_MASK       0x004C
0062 #define HISI_I2C_TRANS_STATE        0x0050
0063 #define HISI_I2C_TRANS_ERR      0x0054
0064 #define HISI_I2C_VERSION        0x0058
0065
0066 #define HISI_I2C_INT_ALL    GENMASK(4, 0)
0067 #define HISI_I2C_INT_TRANS_CPLT BIT(0)
0068 #define HISI_I2C_INT_TRANS_ERR  BIT(1)
0069 #define HISI_I2C_INT_FIFO_ERR   BIT(2)
0070 #define HISI_I2C_INT_RX_FULL    BIT(3)
0071 #define HISI_I2C_INT_TX_EMPTY   BIT(4)
0072 #define HISI_I2C_INT_ERR \
0073     (HISI_I2C_INT_TRANS_ERR | HISI_I2C_INT_FIFO_ERR)
0074
0075 #define HISI_I2C_STD_SPEED_MODE     0
0076 #define HISI_I2C_FAST_SPEED_MODE    1
0077 #define HISI_I2C_HIGH_SPEED_MODE    2
0078
0079 #define HISI_I2C_TX_FIFO_DEPTH      64
0080 #define HISI_I2C_RX_FIFO_DEPTH      64
0081 #define HISI_I2C_TX_F_AE_THRESH     1
0082 #define HISI_I2C_RX_F_AF_THRESH     60
0083
0084 #define NSEC_TO_CYCLES(ns, clk_rate_khz) \
0085     DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC)
0086
0087 struct hisi_i2c_controller {
0088     struct i2c_adapter adapter;
0089     void __iomem *iobase;
0090     struct device *dev;
0091     int irq;
0092
0093     /* Intermediates for recording the transfer process */
0094     struct completion *completion;
0095     struct i2c_msg *msgs;
0096     int msg_num;
0097     int msg_tx_idx;
0098     int buf_tx_idx;
0099     int msg_rx_idx;
0100     int buf_rx_idx;
0101     u16 tar_addr;
0102     u32 xfer_err;
0103
0104     /* I2C bus configuration */
0105     struct i2c_timings t;
0106     u32 clk_rate_khz;
0107     u32 spk_len;
0108 };
0109
0110 static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask)
0111 {
0112     writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK);
0113 }
0114
0115 static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask)
0116 {
0117     writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK);
0118 }
0119
0120 static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask)
0121 {
0122     writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR);
0123 }
0124
0125 static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr)
0126 {
0127     u32 int_err = ctlr->xfer_err, reg;
0128
0129     if (int_err & HISI_I2C_INT_FIFO_ERR) {
0130         reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
0131
0132         if (reg & HISI_I2C_FIFO_STATE_RX_RERR)
0133             dev_err(ctlr->dev, "rx fifo error read\n");
0134
0135         if (reg & HISI_I2C_FIFO_STATE_RX_WERR)
0136             dev_err(ctlr->dev, "rx fifo error write\n");
0137
0138         if (reg & HISI_I2C_FIFO_STATE_TX_RERR)
0139             dev_err(ctlr->dev, "tx fifo error read\n");
0140
0141         if (reg & HISI_I2C_FIFO_STATE_TX_WERR)
0142             dev_err(ctlr->dev, "tx fifo error write\n");
0143     }
0144 }
0145
0146 static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr)
0147 {
0148     struct i2c_msg *msg = ctlr->msgs;
0149     u32 reg;
0150
0151     reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL);
0152     reg &= ~HISI_I2C_FRAME_CTRL_ADDR_TEN;
0153     if (msg->flags & I2C_M_TEN)
0154         reg |= HISI_I2C_FRAME_CTRL_ADDR_TEN;
0155     writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);
0156
0157     reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR);
0158     reg &= ~HISI_I2C_SLV_ADDR_VAL;
0159     reg |= FIELD_PREP(HISI_I2C_SLV_ADDR_VAL, msg->addr);
0160     writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR);
0161
0162     reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL);
0163     reg |= HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR;
0164     writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
0165     reg &= ~(HISI_I2C_FIFO_RX_CLR | HISI_I2C_FIFO_TX_CLR);
0166     writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
0167
0168     hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);
0169     hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL);
0170
0171     return 0;
0172 }
0173
0174 static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr)
0175 {
0176     ctlr->msg_num = 0;
0177     ctlr->xfer_err = 0;
0178     ctlr->msg_tx_idx = 0;
0179     ctlr->msg_rx_idx = 0;
0180     ctlr->buf_tx_idx = 0;
0181     ctlr->buf_rx_idx = 0;
0182 }
0183
0184 /*
0185  * Initialize the transfer information and start the I2C bus transfer.
0186  * We only configure the transfer and do some pre/post works here, and
0187  * wait for the transfer done. The major transfer process is performed
0188  * in the IRQ handler.
0189  */
0190 static int hisi_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
0191                 int num)
0192 {
0193     struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap);
0194     DECLARE_COMPLETION_ONSTACK(done);
0195     int ret = num;
0196
0197     hisi_i2c_reset_xfer(ctlr);
0198     ctlr->completion = &done;
0199     ctlr->msg_num = num;
0200     ctlr->msgs = msgs;
0201
0202     hisi_i2c_start_xfer(ctlr);
0203
0204     if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) {
0205         hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
0206         synchronize_irq(ctlr->irq);
0207         i2c_recover_bus(&ctlr->adapter);
0208         dev_err(ctlr->dev, "bus transfer timeout\n");
0209         ret = -EIO;
0210     }
0211
0212     if (ctlr->xfer_err) {
0213         hisi_i2c_handle_errors(ctlr);
0214         ret = -EIO;
0215     }
0216
0217     hisi_i2c_reset_xfer(ctlr);
0218     ctlr->completion = NULL;
0219
0220     return ret;
0221 }
0222
0223 static u32 hisi_i2c_functionality(struct i2c_adapter *adap)
0224 {
0225     return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
0226 }
0227
0228 static const struct i2c_algorithm hisi_i2c_algo = {
0229     .master_xfer    = hisi_i2c_master_xfer,
0230     .functionality  = hisi_i2c_functionality,
0231 };
0232
0233 static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr)
0234 {
0235     struct i2c_msg *cur_msg;
0236     u32 fifo_state;
0237
0238     while (ctlr->msg_rx_idx < ctlr->msg_num) {
0239         cur_msg = ctlr->msgs + ctlr->msg_rx_idx;
0240
0241         if (!(cur_msg->flags & I2C_M_RD)) {
0242             ctlr->msg_rx_idx++;
0243             continue;
0244         }
0245
0246         fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
0247         while (!(fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY) &&
0248                ctlr->buf_rx_idx < cur_msg->len) {
0249             cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA);
0250             fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
0251         }
0252
0253         if (ctlr->buf_rx_idx == cur_msg->len) {
0254             ctlr->buf_rx_idx = 0;
0255             ctlr->msg_rx_idx++;
0256         }
0257
0258         if (fifo_state & HISI_I2C_FIFO_STATE_RX_EMPTY)
0259             break;
0260     }
0261
0262     return 0;
0263 }
0264
0265 static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr)
0266 {
0267     int max_write = HISI_I2C_TX_FIFO_DEPTH;
0268     bool need_restart = false, last_msg;
0269     struct i2c_msg *cur_msg;
0270     u32 cmd, fifo_state;
0271
0272     while (ctlr->msg_tx_idx < ctlr->msg_num) {
0273         cur_msg = ctlr->msgs + ctlr->msg_tx_idx;
0274         last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1);
0275
0276         /* Signal the SR bit when we start transferring a new message */
0277         if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx)
0278             need_restart = true;
0279
0280         fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
0281         while (!(fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) &&
0282                ctlr->buf_tx_idx < cur_msg->len && max_write) {
0283             cmd = 0;
0284
0285             if (need_restart) {
0286                 cmd |= HISI_I2C_CMD_TXDATA_SR_EN;
0287                 need_restart = false;
0288             }
0289
0290             /* Signal the STOP bit at the last frame of the last message */
0291             if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg)
0292                 cmd |= HISI_I2C_CMD_TXDATA_P_EN;
0293
0294             if (cur_msg->flags & I2C_M_RD)
0295                 cmd |= HISI_I2C_CMD_TXDATA_RW;
0296             else
0297                 cmd |= FIELD_PREP(HISI_I2C_CMD_TXDATA_DATA,
0298                           cur_msg->buf[ctlr->buf_tx_idx]);
0299
0300             writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA);
0301             ctlr->buf_tx_idx++;
0302             max_write--;
0303
0304             fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
0305         }
0306
0307         /* Update the transfer index after per message transfer is done. */
0308         if (ctlr->buf_tx_idx == cur_msg->len) {
0309             ctlr->buf_tx_idx = 0;
0310             ctlr->msg_tx_idx++;
0311         }
0312
0313         if ((fifo_state & HISI_I2C_FIFO_STATE_TX_FULL) ||
0314             max_write == 0)
0315             break;
0316     }
0317 }
0318
0319 static irqreturn_t hisi_i2c_irq(int irq, void *context)
0320 {
0321     struct hisi_i2c_controller *ctlr = context;
0322     u32 int_stat;
0323
0324     int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT);
0325     hisi_i2c_clear_int(ctlr, int_stat);
0326     if (!(int_stat & HISI_I2C_INT_ALL))
0327         return IRQ_NONE;
0328
0329     if (int_stat & HISI_I2C_INT_TX_EMPTY)
0330         hisi_i2c_xfer_msg(ctlr);
0331
0332     if (int_stat & HISI_I2C_INT_ERR) {
0333         ctlr->xfer_err = int_stat;
0334         goto out;
0335     }
0336
0337     /* Drain the rx fifo before finish the transfer */
0338     if (int_stat & (HISI_I2C_INT_TRANS_CPLT | HISI_I2C_INT_RX_FULL))
0339         hisi_i2c_read_rx_fifo(ctlr);
0340
0341 out:
0342     if (int_stat & HISI_I2C_INT_TRANS_CPLT || ctlr->xfer_err) {
0343         hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
0344         hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);
0345         complete(ctlr->completion);
0346     }
0347
0348     return IRQ_HANDLED;
0349 }
0350
0351 /*
0352  * Helper function for calculating and configuring the HIGH and LOW
0353  * periods of SCL clock. The caller will pass the ratio of the
0354  * counts (divide / divisor) according to the target speed mode,
0355  * and the target registers.
0356  */
0357 static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr,
0358                  u32 divide, u32 divisor,
0359                  u32 reg_hcnt, u32 reg_lcnt)
0360 {
0361     u32 total_cnt, t_scl_hcnt, t_scl_lcnt, scl_fall_cnt, scl_rise_cnt;
0362     u32 scl_hcnt, scl_lcnt;
0363
0364     /* Total SCL clock cycles per speed period */
0365     total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz);
0366     /* Total HIGH level SCL clock cycles including edges */
0367     t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor);
0368     /* Total LOW level SCL clock cycles including edges */
0369     t_scl_lcnt = total_cnt - t_scl_hcnt;
0370     /* Fall edge SCL clock cycles */
0371     scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz);
0372     /* Rise edge SCL clock cycles */
0373     scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz);
0374
0375     /* Calculated HIGH and LOW periods of SCL clock */
0376     scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt;
0377     scl_lcnt = t_scl_lcnt - 1 - scl_rise_cnt;
0378
0379     writel(scl_hcnt, ctlr->iobase + reg_hcnt);
0380     writel(scl_lcnt, ctlr->iobase + reg_lcnt);
0381 }
0382
0383 static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr)
0384 {
0385     u32 reg, sda_hold_cnt, speed_mode;
0386
0387     i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true);
0388     ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz);
0389
0390     switch (ctlr->t.bus_freq_hz) {
0391     case I2C_MAX_FAST_MODE_FREQ:
0392         speed_mode = HISI_I2C_FAST_SPEED_MODE;
0393         hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT);
0394         break;
0395     case I2C_MAX_HIGH_SPEED_MODE_FREQ:
0396         speed_mode = HISI_I2C_HIGH_SPEED_MODE;
0397         hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT);
0398         break;
0399     case I2C_MAX_STANDARD_MODE_FREQ:
0400     default:
0401         speed_mode = HISI_I2C_STD_SPEED_MODE;
0402
0403         /* For default condition force the bus speed to standard mode. */
0404         ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
0405         hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT);
0406         break;
0407     }
0408
0409     reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL);
0410     reg &= ~HISI_I2C_FRAME_CTRL_SPEED_MODE;
0411     reg |= FIELD_PREP(HISI_I2C_FRAME_CTRL_SPEED_MODE, speed_mode);
0412     writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);
0413
0414     sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz);
0415
0416     reg = FIELD_PREP(HISI_I2C_SDA_HOLD_TX, sda_hold_cnt);
0417     writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD);
0418
0419     writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN);
0420
0421     reg = FIELD_PREP(HISI_I2C_FIFO_RX_AF_THRESH, HISI_I2C_RX_F_AF_THRESH);
0422     reg |= FIELD_PREP(HISI_I2C_FIFO_TX_AE_THRESH, HISI_I2C_TX_F_AE_THRESH);
0423     writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
0424 }
0425
0426 static int hisi_i2c_probe(struct platform_device *pdev)
0427 {
0428     struct hisi_i2c_controller *ctlr;
0429     struct device *dev = &pdev->dev;
0430     struct i2c_adapter *adapter;
0431     u64 clk_rate_hz;
0432     u32 hw_version;
0433     int ret;
0434
0435     ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL);
0436     if (!ctlr)
0437         return -ENOMEM;
0438
0439     ctlr->iobase = devm_platform_ioremap_resource(pdev, 0);
0440     if (IS_ERR(ctlr->iobase))
0441         return PTR_ERR(ctlr->iobase);
0442
0443     ctlr->irq = platform_get_irq(pdev, 0);
0444     if (ctlr->irq < 0)
0445         return ctlr->irq;
0446
0447     ctlr->dev = dev;
0448
0449     hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
0450
0451     ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr);
0452     if (ret) {
0453         dev_err(dev, "failed to request irq handler, ret = %d\n", ret);
0454         return ret;
0455     }
0456
0457     ret = device_property_read_u64(dev, "clk_rate", &clk_rate_hz);
0458     if (ret) {
0459         dev_err(dev, "failed to get clock frequency, ret = %d\n", ret);
0460         return ret;
0461     }
0462
0463     ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ);
0464
0465     hisi_i2c_configure_bus(ctlr);
0466
0467     adapter = &ctlr->adapter;
0468     snprintf(adapter->name, sizeof(adapter->name),
0469          "HiSilicon I2C Controller %s", dev_name(dev));
0470     adapter->owner = THIS_MODULE;
0471     adapter->algo = &hisi_i2c_algo;
0472     adapter->dev.parent = dev;
0473     i2c_set_adapdata(adapter, ctlr);
0474
0475     ret = devm_i2c_add_adapter(dev, adapter);
0476     if (ret)
0477         return ret;
0478
0479     hw_version = readl(ctlr->iobase + HISI_I2C_VERSION);
0480     dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n",
0481          i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version);
0482
0483     return 0;
0484 }
0485
0486 static const struct acpi_device_id hisi_i2c_acpi_ids[] = {
0487     { "HISI03D1", 0 },
0488     { }
0489 };
0490 MODULE_DEVICE_TABLE(acpi, hisi_i2c_acpi_ids);
0491
0492 static struct platform_driver hisi_i2c_driver = {
0493     .probe      = hisi_i2c_probe,
0494     .driver     = {
0495         .name   = "hisi-i2c",
0496         .acpi_match_table = hisi_i2c_acpi_ids,
0497     },
0498 };
0499 module_platform_driver(hisi_i2c_driver);
0500
0501 MODULE_AUTHOR("Yicong Yang <yangyicong@hisilicon.com>");
0502 MODULE_DESCRIPTION("HiSilicon I2C Controller Driver");
0503 MODULE_LICENSE("GPL");