i2c/busses/i2c-highlander.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas Solutions Highlander FPGA I2C/SMBus support.
0004  *
0005  * Supported devices: R0P7780LC0011RL, R0P7785LC0011RL
0006  *
0007  * Copyright (C) 2008  Paul Mundt
0008  * Copyright (C) 2008  Renesas Solutions Corp.
0009  * Copyright (C) 2008  Atom Create Engineering Co., Ltd.
0010  */
0011 #include <linux/module.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/i2c.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/completion.h>
0016 #include <linux/io.h>
0017 #include <linux/delay.h>
0018 #include <linux/slab.h>
0019
0020 #define SMCR        0x00
0021 #define SMCR_START  (1 << 0)
0022 #define SMCR_IRIC   (1 << 1)
0023 #define SMCR_BBSY   (1 << 2)
0024 #define SMCR_ACKE   (1 << 3)
0025 #define SMCR_RST    (1 << 4)
0026 #define SMCR_IEIC   (1 << 6)
0027
0028 #define SMSMADR     0x02
0029
0030 #define SMMR        0x04
0031 #define SMMR_MODE0  (1 << 0)
0032 #define SMMR_MODE1  (1 << 1)
0033 #define SMMR_CAP    (1 << 3)
0034 #define SMMR_TMMD   (1 << 4)
0035 #define SMMR_SP     (1 << 7)
0036
0037 #define SMSADR      0x06
0038 #define SMTRDR      0x46
0039
0040 struct highlander_i2c_dev {
0041     struct device       *dev;
0042     void __iomem        *base;
0043     struct i2c_adapter  adapter;
0044     struct completion   cmd_complete;
0045     unsigned long       last_read_time;
0046     int         irq;
0047     u8          *buf;
0048     size_t          buf_len;
0049 };
0050
0051 static bool iic_force_poll, iic_force_normal;
0052 static int iic_timeout = 1000, iic_read_delay;
0053
0054 static inline void highlander_i2c_irq_enable(struct highlander_i2c_dev *dev)
0055 {
0056     iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR);
0057 }
0058
0059 static inline void highlander_i2c_irq_disable(struct highlander_i2c_dev *dev)
0060 {
0061     iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR);
0062 }
0063
0064 static inline void highlander_i2c_start(struct highlander_i2c_dev *dev)
0065 {
0066     iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR);
0067 }
0068
0069 static inline void highlander_i2c_done(struct highlander_i2c_dev *dev)
0070 {
0071     iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR);
0072 }
0073
0074 static void highlander_i2c_setup(struct highlander_i2c_dev *dev)
0075 {
0076     u16 smmr;
0077
0078     smmr = ioread16(dev->base + SMMR);
0079     smmr |= SMMR_TMMD;
0080
0081     if (iic_force_normal)
0082         smmr &= ~SMMR_SP;
0083     else
0084         smmr |= SMMR_SP;
0085
0086     iowrite16(smmr, dev->base + SMMR);
0087 }
0088
0089 static void smbus_write_data(u8 *src, u16 *dst, int len)
0090 {
0091     for (; len > 1; len -= 2) {
0092         *dst++ = be16_to_cpup((__be16 *)src);
0093         src += 2;
0094     }
0095
0096     if (len)
0097         *dst = *src << 8;
0098 }
0099
0100 static void smbus_read_data(u16 *src, u8 *dst, int len)
0101 {
0102     for (; len > 1; len -= 2) {
0103         *(__be16 *)dst = cpu_to_be16p(src++);
0104         dst += 2;
0105     }
0106
0107     if (len)
0108         *dst = *src >> 8;
0109 }
0110
0111 static void highlander_i2c_command(struct highlander_i2c_dev *dev,
0112                    u8 command, int len)
0113 {
0114     unsigned int i;
0115     u16 cmd = (command << 8) | command;
0116
0117     for (i = 0; i < len; i += 2) {
0118         if (len - i == 1)
0119             cmd = command << 8;
0120         iowrite16(cmd, dev->base + SMSADR + i);
0121         dev_dbg(dev->dev, "command data[%x] 0x%04x\n", i/2, cmd);
0122     }
0123 }
0124
0125 static int highlander_i2c_wait_for_bbsy(struct highlander_i2c_dev *dev)
0126 {
0127     unsigned long timeout;
0128
0129     timeout = jiffies + msecs_to_jiffies(iic_timeout);
0130     while (ioread16(dev->base + SMCR) & SMCR_BBSY) {
0131         if (time_after(jiffies, timeout)) {
0132             dev_warn(dev->dev, "timeout waiting for bus ready\n");
0133             return -ETIMEDOUT;
0134         }
0135
0136         msleep(1);
0137     }
0138
0139     return 0;
0140 }
0141
0142 static int highlander_i2c_reset(struct highlander_i2c_dev *dev)
0143 {
0144     iowrite16(ioread16(dev->base + SMCR) | SMCR_RST, dev->base + SMCR);
0145     return highlander_i2c_wait_for_bbsy(dev);
0146 }
0147
0148 static int highlander_i2c_wait_for_ack(struct highlander_i2c_dev *dev)
0149 {
0150     u16 tmp = ioread16(dev->base + SMCR);
0151
0152     if ((tmp & (SMCR_IRIC | SMCR_ACKE)) == SMCR_ACKE) {
0153         dev_warn(dev->dev, "ack abnormality\n");
0154         return highlander_i2c_reset(dev);
0155     }
0156
0157     return 0;
0158 }
0159
0160 static irqreturn_t highlander_i2c_irq(int irq, void *dev_id)
0161 {
0162     struct highlander_i2c_dev *dev = dev_id;
0163
0164     highlander_i2c_done(dev);
0165     complete(&dev->cmd_complete);
0166
0167     return IRQ_HANDLED;
0168 }
0169
0170 static void highlander_i2c_poll(struct highlander_i2c_dev *dev)
0171 {
0172     unsigned long timeout;
0173     u16 smcr;
0174
0175     timeout = jiffies + msecs_to_jiffies(iic_timeout);
0176     for (;;) {
0177         smcr = ioread16(dev->base + SMCR);
0178
0179         /*
0180          * Don't bother checking ACKE here, this and the reset
0181          * are handled in highlander_i2c_wait_xfer_done() when
0182          * waiting for the ACK.
0183          */
0184
0185         if (smcr & SMCR_IRIC)
0186             return;
0187         if (time_after(jiffies, timeout))
0188             break;
0189
0190         cpu_relax();
0191         cond_resched();
0192     }
0193
0194     dev_err(dev->dev, "polling timed out\n");
0195 }
0196
0197 static inline int highlander_i2c_wait_xfer_done(struct highlander_i2c_dev *dev)
0198 {
0199     if (dev->irq)
0200         wait_for_completion_timeout(&dev->cmd_complete,
0201                       msecs_to_jiffies(iic_timeout));
0202     else
0203         /* busy looping, the IRQ of champions */
0204         highlander_i2c_poll(dev);
0205
0206     return highlander_i2c_wait_for_ack(dev);
0207 }
0208
0209 static int highlander_i2c_read(struct highlander_i2c_dev *dev)
0210 {
0211     int i, cnt;
0212     u16 data[16];
0213
0214     if (highlander_i2c_wait_for_bbsy(dev))
0215         return -EAGAIN;
0216
0217     highlander_i2c_start(dev);
0218
0219     if (highlander_i2c_wait_xfer_done(dev)) {
0220         dev_err(dev->dev, "Arbitration loss\n");
0221         return -EAGAIN;
0222     }
0223
0224     /*
0225      * The R0P7780LC0011RL FPGA needs a significant delay between
0226      * data read cycles, otherwise the transceiver gets confused and
0227      * garbage is returned when the read is subsequently aborted.
0228      *
0229      * It is not sufficient to wait for BBSY.
0230      *
0231      * While this generally only applies to the older SH7780-based
0232      * Highlanders, the same issue can be observed on SH7785 ones,
0233      * albeit less frequently. SH7780-based Highlanders may need
0234      * this to be as high as 1000 ms.
0235      */
0236     if (iic_read_delay && time_before(jiffies, dev->last_read_time +
0237                  msecs_to_jiffies(iic_read_delay)))
0238         msleep(jiffies_to_msecs((dev->last_read_time +
0239                 msecs_to_jiffies(iic_read_delay)) - jiffies));
0240
0241     cnt = (dev->buf_len + 1) >> 1;
0242     for (i = 0; i < cnt; i++) {
0243         data[i] = ioread16(dev->base + SMTRDR + (i * sizeof(u16)));
0244         dev_dbg(dev->dev, "read data[%x] 0x%04x\n", i, data[i]);
0245     }
0246
0247     smbus_read_data(data, dev->buf, dev->buf_len);
0248
0249     dev->last_read_time = jiffies;
0250
0251     return 0;
0252 }
0253
0254 static int highlander_i2c_write(struct highlander_i2c_dev *dev)
0255 {
0256     int i, cnt;
0257     u16 data[16];
0258
0259     smbus_write_data(dev->buf, data, dev->buf_len);
0260
0261     cnt = (dev->buf_len + 1) >> 1;
0262     for (i = 0; i < cnt; i++) {
0263         iowrite16(data[i], dev->base + SMTRDR + (i * sizeof(u16)));
0264         dev_dbg(dev->dev, "write data[%x] 0x%04x\n", i, data[i]);
0265     }
0266
0267     if (highlander_i2c_wait_for_bbsy(dev))
0268         return -EAGAIN;
0269
0270     highlander_i2c_start(dev);
0271
0272     return highlander_i2c_wait_xfer_done(dev);
0273 }
0274
0275 static int highlander_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
0276                   unsigned short flags, char read_write,
0277                   u8 command, int size,
0278                   union i2c_smbus_data *data)
0279 {
0280     struct highlander_i2c_dev *dev = i2c_get_adapdata(adap);
0281     u16 tmp;
0282
0283     init_completion(&dev->cmd_complete);
0284
0285     dev_dbg(dev->dev, "addr %04x, command %02x, read_write %d, size %d\n",
0286         addr, command, read_write, size);
0287
0288     /*
0289      * Set up the buffer and transfer size
0290      */
0291     switch (size) {
0292     case I2C_SMBUS_BYTE_DATA:
0293         dev->buf = &data->byte;
0294         dev->buf_len = 1;
0295         break;
0296     case I2C_SMBUS_I2C_BLOCK_DATA:
0297         dev->buf = &data->block[1];
0298         dev->buf_len = data->block[0];
0299         break;
0300     default:
0301         dev_err(dev->dev, "unsupported command %d\n", size);
0302         return -EINVAL;
0303     }
0304
0305     /*
0306      * Encode the mode setting
0307      */
0308     tmp = ioread16(dev->base + SMMR);
0309     tmp &= ~(SMMR_MODE0 | SMMR_MODE1);
0310
0311     switch (dev->buf_len) {
0312     case 1:
0313         /* default */
0314         break;
0315     case 8:
0316         tmp |= SMMR_MODE0;
0317         break;
0318     case 16:
0319         tmp |= SMMR_MODE1;
0320         break;
0321     case 32:
0322         tmp |= (SMMR_MODE0 | SMMR_MODE1);
0323         break;
0324     default:
0325         dev_err(dev->dev, "unsupported xfer size %zu\n", dev->buf_len);
0326         return -EINVAL;
0327     }
0328
0329     iowrite16(tmp, dev->base + SMMR);
0330
0331     /* Ensure we're in a sane state */
0332     highlander_i2c_done(dev);
0333
0334     /* Set slave address */
0335     iowrite16((addr << 1) | read_write, dev->base + SMSMADR);
0336
0337     highlander_i2c_command(dev, command, dev->buf_len);
0338
0339     if (read_write == I2C_SMBUS_READ)
0340         return highlander_i2c_read(dev);
0341     else
0342         return highlander_i2c_write(dev);
0343 }
0344
0345 static u32 highlander_i2c_func(struct i2c_adapter *adapter)
0346 {
0347     return I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK;
0348 }
0349
0350 static const struct i2c_algorithm highlander_i2c_algo = {
0351     .smbus_xfer = highlander_i2c_smbus_xfer,
0352     .functionality  = highlander_i2c_func,
0353 };
0354
0355 static int highlander_i2c_probe(struct platform_device *pdev)
0356 {
0357     struct highlander_i2c_dev *dev;
0358     struct i2c_adapter *adap;
0359     struct resource *res;
0360     int ret;
0361
0362     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0363     if (unlikely(!res)) {
0364         dev_err(&pdev->dev, "no mem resource\n");
0365         return -ENODEV;
0366     }
0367
0368     dev = kzalloc(sizeof(struct highlander_i2c_dev), GFP_KERNEL);
0369     if (unlikely(!dev))
0370         return -ENOMEM;
0371
0372     dev->base = ioremap(res->start, resource_size(res));
0373     if (unlikely(!dev->base)) {
0374         ret = -ENXIO;
0375         goto err;
0376     }
0377
0378     dev->dev = &pdev->dev;
0379     platform_set_drvdata(pdev, dev);
0380
0381     dev->irq = platform_get_irq(pdev, 0);
0382     if (dev->irq < 0 || iic_force_poll)
0383         dev->irq = 0;
0384
0385     if (dev->irq) {
0386         ret = request_irq(dev->irq, highlander_i2c_irq, 0,
0387                   pdev->name, dev);
0388         if (unlikely(ret))
0389             goto err_unmap;
0390
0391         highlander_i2c_irq_enable(dev);
0392     } else {
0393         dev_notice(&pdev->dev, "no IRQ, using polling mode\n");
0394         highlander_i2c_irq_disable(dev);
0395     }
0396
0397     dev->last_read_time = jiffies;  /* initial read jiffies */
0398
0399     highlander_i2c_setup(dev);
0400
0401     adap = &dev->adapter;
0402     i2c_set_adapdata(adap, dev);
0403     adap->owner = THIS_MODULE;
0404     adap->class = I2C_CLASS_HWMON;
0405     strscpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name));
0406     adap->algo = &highlander_i2c_algo;
0407     adap->dev.parent = &pdev->dev;
0408     adap->nr = pdev->id;
0409
0410     /*
0411      * Reset the adapter
0412      */
0413     ret = highlander_i2c_reset(dev);
0414     if (unlikely(ret)) {
0415         dev_err(&pdev->dev, "controller didn't come up\n");
0416         goto err_free_irq;
0417     }
0418
0419     ret = i2c_add_numbered_adapter(adap);
0420     if (unlikely(ret)) {
0421         dev_err(&pdev->dev, "failure adding adapter\n");
0422         goto err_free_irq;
0423     }
0424
0425     return 0;
0426
0427 err_free_irq:
0428     if (dev->irq)
0429         free_irq(dev->irq, dev);
0430 err_unmap:
0431     iounmap(dev->base);
0432 err:
0433     kfree(dev);
0434
0435     return ret;
0436 }
0437
0438 static int highlander_i2c_remove(struct platform_device *pdev)
0439 {
0440     struct highlander_i2c_dev *dev = platform_get_drvdata(pdev);
0441
0442     i2c_del_adapter(&dev->adapter);
0443
0444     if (dev->irq)
0445         free_irq(dev->irq, dev);
0446
0447     iounmap(dev->base);
0448     kfree(dev);
0449
0450     return 0;
0451 }
0452
0453 static struct platform_driver highlander_i2c_driver = {
0454     .driver     = {
0455         .name   = "i2c-highlander",
0456     },
0457
0458     .probe      = highlander_i2c_probe,
0459     .remove     = highlander_i2c_remove,
0460 };
0461
0462 module_platform_driver(highlander_i2c_driver);
0463
0464 MODULE_AUTHOR("Paul Mundt");
0465 MODULE_DESCRIPTION("Renesas Highlander FPGA I2C/SMBus adapter");
0466 MODULE_LICENSE("GPL v2");
0467
0468 module_param(iic_force_poll, bool, 0);
0469 module_param(iic_force_normal, bool, 0);
0470 module_param(iic_timeout, int, 0);
0471 module_param(iic_read_delay, int, 0);
0472
0473 MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
0474 MODULE_PARM_DESC(iic_force_normal,
0475          "Force normal mode (100 kHz), default is fast mode (400 kHz)");
0476 MODULE_PARM_DESC(iic_timeout, "Set timeout value in msecs (default 1000 ms)");
0477 MODULE_PARM_DESC(iic_read_delay,
0478          "Delay between data read cycles (default 0 ms)");