Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * FSI-attached I2C master algorithm
0004  *
0005  * Copyright 2018 IBM Corporation
0006  *
0007  * This program is free software; you can redistribute it and/or
0008  * modify it under the terms of the GNU General Public License
0009  * as published by the Free Software Foundation; either version
0010  * 2 of the License, or (at your option) any later version.
0011  */
0012 
0013 #include <linux/bitfield.h>
0014 #include <linux/bitops.h>
0015 #include <linux/delay.h>
0016 #include <linux/device.h>
0017 #include <linux/errno.h>
0018 #include <linux/fsi.h>
0019 #include <linux/i2c.h>
0020 #include <linux/jiffies.h>
0021 #include <linux/kernel.h>
0022 #include <linux/list.h>
0023 #include <linux/module.h>
0024 #include <linux/mutex.h>
0025 #include <linux/of.h>
0026 #include <linux/slab.h>
0027 
0028 #define FSI_ENGID_I2C       0x7
0029 
0030 #define I2C_DEFAULT_CLK_DIV 6
0031 
0032 /* i2c registers */
0033 #define I2C_FSI_FIFO        0x00
0034 #define I2C_FSI_CMD     0x04
0035 #define I2C_FSI_MODE        0x08
0036 #define I2C_FSI_WATER_MARK  0x0C
0037 #define I2C_FSI_INT_MASK    0x10
0038 #define I2C_FSI_INT_COND    0x14
0039 #define I2C_FSI_OR_INT_MASK 0x14
0040 #define I2C_FSI_INTS        0x18
0041 #define I2C_FSI_AND_INT_MASK    0x18
0042 #define I2C_FSI_STAT        0x1C
0043 #define I2C_FSI_RESET_I2C   0x1C
0044 #define I2C_FSI_ESTAT       0x20
0045 #define I2C_FSI_RESET_ERR   0x20
0046 #define I2C_FSI_RESID_LEN   0x24
0047 #define I2C_FSI_SET_SCL     0x24
0048 #define I2C_FSI_PORT_BUSY   0x28
0049 #define I2C_FSI_RESET_SCL   0x2C
0050 #define I2C_FSI_SET_SDA     0x30
0051 #define I2C_FSI_RESET_SDA   0x34
0052 
0053 /* cmd register */
0054 #define I2C_CMD_WITH_START  BIT(31)
0055 #define I2C_CMD_WITH_ADDR   BIT(30)
0056 #define I2C_CMD_RD_CONT     BIT(29)
0057 #define I2C_CMD_WITH_STOP   BIT(28)
0058 #define I2C_CMD_FORCELAUNCH BIT(27)
0059 #define I2C_CMD_ADDR        GENMASK(23, 17)
0060 #define I2C_CMD_READ        BIT(16)
0061 #define I2C_CMD_LEN     GENMASK(15, 0)
0062 
0063 /* mode register */
0064 #define I2C_MODE_CLKDIV     GENMASK(31, 16)
0065 #define I2C_MODE_PORT       GENMASK(15, 10)
0066 #define I2C_MODE_ENHANCED   BIT(3)
0067 #define I2C_MODE_DIAG       BIT(2)
0068 #define I2C_MODE_PACE_ALLOW BIT(1)
0069 #define I2C_MODE_WRAP       BIT(0)
0070 
0071 /* watermark register */
0072 #define I2C_WATERMARK_HI    GENMASK(15, 12)
0073 #define I2C_WATERMARK_LO    GENMASK(7, 4)
0074 
0075 #define I2C_FIFO_HI_LVL     4
0076 #define I2C_FIFO_LO_LVL     4
0077 
0078 /* interrupt register */
0079 #define I2C_INT_INV_CMD     BIT(15)
0080 #define I2C_INT_PARITY      BIT(14)
0081 #define I2C_INT_BE_OVERRUN  BIT(13)
0082 #define I2C_INT_BE_ACCESS   BIT(12)
0083 #define I2C_INT_LOST_ARB    BIT(11)
0084 #define I2C_INT_NACK        BIT(10)
0085 #define I2C_INT_DAT_REQ     BIT(9)
0086 #define I2C_INT_CMD_COMP    BIT(8)
0087 #define I2C_INT_STOP_ERR    BIT(7)
0088 #define I2C_INT_BUSY        BIT(6)
0089 #define I2C_INT_IDLE        BIT(5)
0090 
0091 /* status register */
0092 #define I2C_STAT_INV_CMD    BIT(31)
0093 #define I2C_STAT_PARITY     BIT(30)
0094 #define I2C_STAT_BE_OVERRUN BIT(29)
0095 #define I2C_STAT_BE_ACCESS  BIT(28)
0096 #define I2C_STAT_LOST_ARB   BIT(27)
0097 #define I2C_STAT_NACK       BIT(26)
0098 #define I2C_STAT_DAT_REQ    BIT(25)
0099 #define I2C_STAT_CMD_COMP   BIT(24)
0100 #define I2C_STAT_STOP_ERR   BIT(23)
0101 #define I2C_STAT_MAX_PORT   GENMASK(22, 16)
0102 #define I2C_STAT_ANY_INT    BIT(15)
0103 #define I2C_STAT_SCL_IN     BIT(11)
0104 #define I2C_STAT_SDA_IN     BIT(10)
0105 #define I2C_STAT_PORT_BUSY  BIT(9)
0106 #define I2C_STAT_SELF_BUSY  BIT(8)
0107 #define I2C_STAT_FIFO_COUNT GENMASK(7, 0)
0108 
0109 #define I2C_STAT_ERR        (I2C_STAT_INV_CMD |         \
0110                  I2C_STAT_PARITY |          \
0111                  I2C_STAT_BE_OVERRUN |          \
0112                  I2C_STAT_BE_ACCESS |           \
0113                  I2C_STAT_LOST_ARB |            \
0114                  I2C_STAT_NACK |            \
0115                  I2C_STAT_STOP_ERR)
0116 #define I2C_STAT_ANY_RESP   (I2C_STAT_ERR |             \
0117                  I2C_STAT_DAT_REQ |         \
0118                  I2C_STAT_CMD_COMP)
0119 
0120 /* extended status register */
0121 #define I2C_ESTAT_FIFO_SZ   GENMASK(31, 24)
0122 #define I2C_ESTAT_SCL_IN_SY BIT(15)
0123 #define I2C_ESTAT_SDA_IN_SY BIT(14)
0124 #define I2C_ESTAT_S_SCL     BIT(13)
0125 #define I2C_ESTAT_S_SDA     BIT(12)
0126 #define I2C_ESTAT_M_SCL     BIT(11)
0127 #define I2C_ESTAT_M_SDA     BIT(10)
0128 #define I2C_ESTAT_HI_WATER  BIT(9)
0129 #define I2C_ESTAT_LO_WATER  BIT(8)
0130 #define I2C_ESTAT_PORT_BUSY BIT(7)
0131 #define I2C_ESTAT_SELF_BUSY BIT(6)
0132 #define I2C_ESTAT_VERSION   GENMASK(4, 0)
0133 
0134 /* port busy register */
0135 #define I2C_PORT_BUSY_RESET BIT(31)
0136 
0137 /* wait for command complete or data request */
0138 #define I2C_CMD_SLEEP_MAX_US    500
0139 #define I2C_CMD_SLEEP_MIN_US    50
0140 
0141 /* wait after reset; choose time from legacy driver */
0142 #define I2C_RESET_SLEEP_MAX_US  2000
0143 #define I2C_RESET_SLEEP_MIN_US  1000
0144 
0145 /* choose timeout length from legacy driver; it's well tested */
0146 #define I2C_ABORT_TIMEOUT   msecs_to_jiffies(100)
0147 
0148 struct fsi_i2c_master {
0149     struct fsi_device   *fsi;
0150     u8          fifo_size;
0151     struct list_head    ports;
0152     struct mutex        lock;
0153 };
0154 
0155 struct fsi_i2c_port {
0156     struct list_head    list;
0157     struct i2c_adapter  adapter;
0158     struct fsi_i2c_master   *master;
0159     u16         port;
0160     u16         xfrd;
0161 };
0162 
0163 static int fsi_i2c_read_reg(struct fsi_device *fsi, unsigned int reg,
0164                 u32 *data)
0165 {
0166     int rc;
0167     __be32 data_be;
0168 
0169     rc = fsi_device_read(fsi, reg, &data_be, sizeof(data_be));
0170     if (rc)
0171         return rc;
0172 
0173     *data = be32_to_cpu(data_be);
0174 
0175     return 0;
0176 }
0177 
0178 static int fsi_i2c_write_reg(struct fsi_device *fsi, unsigned int reg,
0179                  u32 *data)
0180 {
0181     __be32 data_be = cpu_to_be32p(data);
0182 
0183     return fsi_device_write(fsi, reg, &data_be, sizeof(data_be));
0184 }
0185 
0186 static int fsi_i2c_dev_init(struct fsi_i2c_master *i2c)
0187 {
0188     int rc;
0189     u32 mode = I2C_MODE_ENHANCED, extended_status, watermark;
0190     u32 interrupt = 0;
0191 
0192     /* since we use polling, disable interrupts */
0193     rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_INT_MASK, &interrupt);
0194     if (rc)
0195         return rc;
0196 
0197     mode |= FIELD_PREP(I2C_MODE_CLKDIV, I2C_DEFAULT_CLK_DIV);
0198     rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode);
0199     if (rc)
0200         return rc;
0201 
0202     rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_ESTAT, &extended_status);
0203     if (rc)
0204         return rc;
0205 
0206     i2c->fifo_size = FIELD_GET(I2C_ESTAT_FIFO_SZ, extended_status);
0207     watermark = FIELD_PREP(I2C_WATERMARK_HI,
0208                    i2c->fifo_size - I2C_FIFO_HI_LVL);
0209     watermark |= FIELD_PREP(I2C_WATERMARK_LO, I2C_FIFO_LO_LVL);
0210 
0211     return fsi_i2c_write_reg(i2c->fsi, I2C_FSI_WATER_MARK, &watermark);
0212 }
0213 
0214 static int fsi_i2c_set_port(struct fsi_i2c_port *port)
0215 {
0216     int rc;
0217     struct fsi_device *fsi = port->master->fsi;
0218     u32 mode, dummy = 0;
0219 
0220     rc = fsi_i2c_read_reg(fsi, I2C_FSI_MODE, &mode);
0221     if (rc)
0222         return rc;
0223 
0224     if (FIELD_GET(I2C_MODE_PORT, mode) == port->port)
0225         return 0;
0226 
0227     mode = (mode & ~I2C_MODE_PORT) | FIELD_PREP(I2C_MODE_PORT, port->port);
0228     rc = fsi_i2c_write_reg(fsi, I2C_FSI_MODE, &mode);
0229     if (rc)
0230         return rc;
0231 
0232     /* reset engine when port is changed */
0233     return fsi_i2c_write_reg(fsi, I2C_FSI_RESET_ERR, &dummy);
0234 }
0235 
0236 static int fsi_i2c_start(struct fsi_i2c_port *port, struct i2c_msg *msg,
0237              bool stop)
0238 {
0239     struct fsi_i2c_master *i2c = port->master;
0240     u32 cmd = I2C_CMD_WITH_START | I2C_CMD_WITH_ADDR;
0241 
0242     port->xfrd = 0;
0243 
0244     if (msg->flags & I2C_M_RD)
0245         cmd |= I2C_CMD_READ;
0246 
0247     if (stop || msg->flags & I2C_M_STOP)
0248         cmd |= I2C_CMD_WITH_STOP;
0249 
0250     cmd |= FIELD_PREP(I2C_CMD_ADDR, msg->addr);
0251     cmd |= FIELD_PREP(I2C_CMD_LEN, msg->len);
0252 
0253     return fsi_i2c_write_reg(i2c->fsi, I2C_FSI_CMD, &cmd);
0254 }
0255 
0256 static int fsi_i2c_get_op_bytes(int op_bytes)
0257 {
0258     /* fsi is limited to max 4 byte aligned ops */
0259     if (op_bytes > 4)
0260         return 4;
0261     else if (op_bytes == 3)
0262         return 2;
0263     return op_bytes;
0264 }
0265 
0266 static int fsi_i2c_write_fifo(struct fsi_i2c_port *port, struct i2c_msg *msg,
0267                   u8 fifo_count)
0268 {
0269     int write;
0270     int rc;
0271     struct fsi_i2c_master *i2c = port->master;
0272     int bytes_to_write = i2c->fifo_size - fifo_count;
0273     int bytes_remaining = msg->len - port->xfrd;
0274 
0275     bytes_to_write = min(bytes_to_write, bytes_remaining);
0276 
0277     while (bytes_to_write) {
0278         write = fsi_i2c_get_op_bytes(bytes_to_write);
0279 
0280         rc = fsi_device_write(i2c->fsi, I2C_FSI_FIFO,
0281                       &msg->buf[port->xfrd], write);
0282         if (rc)
0283             return rc;
0284 
0285         port->xfrd += write;
0286         bytes_to_write -= write;
0287     }
0288 
0289     return 0;
0290 }
0291 
0292 static int fsi_i2c_read_fifo(struct fsi_i2c_port *port, struct i2c_msg *msg,
0293                  u8 fifo_count)
0294 {
0295     int read;
0296     int rc;
0297     struct fsi_i2c_master *i2c = port->master;
0298     int bytes_to_read;
0299     int xfr_remaining = msg->len - port->xfrd;
0300     u32 dummy;
0301 
0302     bytes_to_read = min_t(int, fifo_count, xfr_remaining);
0303 
0304     while (bytes_to_read) {
0305         read = fsi_i2c_get_op_bytes(bytes_to_read);
0306 
0307         if (xfr_remaining) {
0308             rc = fsi_device_read(i2c->fsi, I2C_FSI_FIFO,
0309                          &msg->buf[port->xfrd], read);
0310             if (rc)
0311                 return rc;
0312 
0313             port->xfrd += read;
0314             xfr_remaining -= read;
0315         } else {
0316             /* no more buffer but data in fifo, need to clear it */
0317             rc = fsi_device_read(i2c->fsi, I2C_FSI_FIFO, &dummy,
0318                          read);
0319             if (rc)
0320                 return rc;
0321         }
0322 
0323         bytes_to_read -= read;
0324     }
0325 
0326     return 0;
0327 }
0328 
0329 static int fsi_i2c_get_scl(struct i2c_adapter *adap)
0330 {
0331     u32 stat = 0;
0332     struct fsi_i2c_port *port = adap->algo_data;
0333     struct fsi_i2c_master *i2c = port->master;
0334 
0335     fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat);
0336 
0337     return !!(stat & I2C_STAT_SCL_IN);
0338 }
0339 
0340 static void fsi_i2c_set_scl(struct i2c_adapter *adap, int val)
0341 {
0342     u32 dummy = 0;
0343     struct fsi_i2c_port *port = adap->algo_data;
0344     struct fsi_i2c_master *i2c = port->master;
0345 
0346     if (val)
0347         fsi_i2c_write_reg(i2c->fsi, I2C_FSI_SET_SCL, &dummy);
0348     else
0349         fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_SCL, &dummy);
0350 }
0351 
0352 static int fsi_i2c_get_sda(struct i2c_adapter *adap)
0353 {
0354     u32 stat = 0;
0355     struct fsi_i2c_port *port = adap->algo_data;
0356     struct fsi_i2c_master *i2c = port->master;
0357 
0358     fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat);
0359 
0360     return !!(stat & I2C_STAT_SDA_IN);
0361 }
0362 
0363 static void fsi_i2c_set_sda(struct i2c_adapter *adap, int val)
0364 {
0365     u32 dummy = 0;
0366     struct fsi_i2c_port *port = adap->algo_data;
0367     struct fsi_i2c_master *i2c = port->master;
0368 
0369     if (val)
0370         fsi_i2c_write_reg(i2c->fsi, I2C_FSI_SET_SDA, &dummy);
0371     else
0372         fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_SDA, &dummy);
0373 }
0374 
0375 static void fsi_i2c_prepare_recovery(struct i2c_adapter *adap)
0376 {
0377     int rc;
0378     u32 mode;
0379     struct fsi_i2c_port *port = adap->algo_data;
0380     struct fsi_i2c_master *i2c = port->master;
0381 
0382     rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_MODE, &mode);
0383     if (rc)
0384         return;
0385 
0386     mode |= I2C_MODE_DIAG;
0387     fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode);
0388 }
0389 
0390 static void fsi_i2c_unprepare_recovery(struct i2c_adapter *adap)
0391 {
0392     int rc;
0393     u32 mode;
0394     struct fsi_i2c_port *port = adap->algo_data;
0395     struct fsi_i2c_master *i2c = port->master;
0396 
0397     rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_MODE, &mode);
0398     if (rc)
0399         return;
0400 
0401     mode &= ~I2C_MODE_DIAG;
0402     fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode);
0403 }
0404 
0405 static int fsi_i2c_reset_bus(struct fsi_i2c_master *i2c,
0406                  struct fsi_i2c_port *port)
0407 {
0408     int rc;
0409     u32 stat, dummy = 0;
0410 
0411     /* force bus reset, ignore errors */
0412     i2c_recover_bus(&port->adapter);
0413 
0414     /* reset errors */
0415     rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_ERR, &dummy);
0416     if (rc)
0417         return rc;
0418 
0419     /* wait for command complete */
0420     usleep_range(I2C_RESET_SLEEP_MIN_US, I2C_RESET_SLEEP_MAX_US);
0421 
0422     rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat);
0423     if (rc)
0424         return rc;
0425 
0426     if (stat & I2C_STAT_CMD_COMP)
0427         return 0;
0428 
0429     /* failed to get command complete; reset engine again */
0430     rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_I2C, &dummy);
0431     if (rc)
0432         return rc;
0433 
0434     /* re-init engine again */
0435     return fsi_i2c_dev_init(i2c);
0436 }
0437 
0438 static int fsi_i2c_reset_engine(struct fsi_i2c_master *i2c, u16 port)
0439 {
0440     int rc;
0441     u32 mode, dummy = 0;
0442 
0443     /* reset engine */
0444     rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_RESET_I2C, &dummy);
0445     if (rc)
0446         return rc;
0447 
0448     /* re-init engine */
0449     rc = fsi_i2c_dev_init(i2c);
0450     if (rc)
0451         return rc;
0452 
0453     rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_MODE, &mode);
0454     if (rc)
0455         return rc;
0456 
0457     /* set port; default after reset is 0 */
0458     if (port) {
0459         mode &= ~I2C_MODE_PORT;
0460         mode |= FIELD_PREP(I2C_MODE_PORT, port);
0461         rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_MODE, &mode);
0462         if (rc)
0463             return rc;
0464     }
0465 
0466     /* reset busy register; hw workaround */
0467     dummy = I2C_PORT_BUSY_RESET;
0468     rc = fsi_i2c_write_reg(i2c->fsi, I2C_FSI_PORT_BUSY, &dummy);
0469     if (rc)
0470         return rc;
0471 
0472     return 0;
0473 }
0474 
0475 static int fsi_i2c_abort(struct fsi_i2c_port *port, u32 status)
0476 {
0477     int rc;
0478     unsigned long start;
0479     u32 cmd = I2C_CMD_WITH_STOP;
0480     u32 stat;
0481     struct fsi_i2c_master *i2c = port->master;
0482     struct fsi_device *fsi = i2c->fsi;
0483 
0484     rc = fsi_i2c_reset_engine(i2c, port->port);
0485     if (rc)
0486         return rc;
0487 
0488     rc = fsi_i2c_read_reg(fsi, I2C_FSI_STAT, &stat);
0489     if (rc)
0490         return rc;
0491 
0492     /* if sda is low, peform full bus reset */
0493     if (!(stat & I2C_STAT_SDA_IN)) {
0494         rc = fsi_i2c_reset_bus(i2c, port);
0495         if (rc)
0496             return rc;
0497     }
0498 
0499     /* skip final stop command for these errors */
0500     if (status & (I2C_STAT_PARITY | I2C_STAT_LOST_ARB | I2C_STAT_STOP_ERR))
0501         return 0;
0502 
0503     /* write stop command */
0504     rc = fsi_i2c_write_reg(fsi, I2C_FSI_CMD, &cmd);
0505     if (rc)
0506         return rc;
0507 
0508     /* wait until we see command complete in the master */
0509     start = jiffies;
0510 
0511     do {
0512         rc = fsi_i2c_read_reg(fsi, I2C_FSI_STAT, &status);
0513         if (rc)
0514             return rc;
0515 
0516         if (status & I2C_STAT_CMD_COMP)
0517             return 0;
0518 
0519         usleep_range(I2C_CMD_SLEEP_MIN_US, I2C_CMD_SLEEP_MAX_US);
0520     } while (time_after(start + I2C_ABORT_TIMEOUT, jiffies));
0521 
0522     return -ETIMEDOUT;
0523 }
0524 
0525 static int fsi_i2c_handle_status(struct fsi_i2c_port *port,
0526                  struct i2c_msg *msg, u32 status)
0527 {
0528     int rc;
0529     u8 fifo_count;
0530 
0531     if (status & I2C_STAT_ERR) {
0532         rc = fsi_i2c_abort(port, status);
0533         if (rc)
0534             return rc;
0535 
0536         if (status & I2C_STAT_INV_CMD)
0537             return -EINVAL;
0538 
0539         if (status & (I2C_STAT_PARITY | I2C_STAT_BE_OVERRUN |
0540             I2C_STAT_BE_ACCESS))
0541             return -EPROTO;
0542 
0543         if (status & I2C_STAT_NACK)
0544             return -ENXIO;
0545 
0546         if (status & I2C_STAT_LOST_ARB)
0547             return -EAGAIN;
0548 
0549         if (status & I2C_STAT_STOP_ERR)
0550             return -EBADMSG;
0551 
0552         return -EIO;
0553     }
0554 
0555     if (status & I2C_STAT_DAT_REQ) {
0556         fifo_count = FIELD_GET(I2C_STAT_FIFO_COUNT, status);
0557 
0558         if (msg->flags & I2C_M_RD)
0559             return fsi_i2c_read_fifo(port, msg, fifo_count);
0560 
0561         return fsi_i2c_write_fifo(port, msg, fifo_count);
0562     }
0563 
0564     if (status & I2C_STAT_CMD_COMP) {
0565         if (port->xfrd < msg->len)
0566             return -ENODATA;
0567 
0568         return msg->len;
0569     }
0570 
0571     return 0;
0572 }
0573 
0574 static int fsi_i2c_wait(struct fsi_i2c_port *port, struct i2c_msg *msg,
0575             unsigned long timeout)
0576 {
0577     u32 status = 0;
0578     int rc;
0579     unsigned long start = jiffies;
0580 
0581     do {
0582         rc = fsi_i2c_read_reg(port->master->fsi, I2C_FSI_STAT,
0583                       &status);
0584         if (rc)
0585             return rc;
0586 
0587         if (status & I2C_STAT_ANY_RESP) {
0588             rc = fsi_i2c_handle_status(port, msg, status);
0589             if (rc < 0)
0590                 return rc;
0591 
0592             /* cmd complete and all data xfrd */
0593             if (rc == msg->len)
0594                 return 0;
0595 
0596             /* need to xfr more data, but maybe don't need wait */
0597             continue;
0598         }
0599 
0600         usleep_range(I2C_CMD_SLEEP_MIN_US, I2C_CMD_SLEEP_MAX_US);
0601     } while (time_after(start + timeout, jiffies));
0602 
0603     return -ETIMEDOUT;
0604 }
0605 
0606 static int fsi_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
0607             int num)
0608 {
0609     int i, rc;
0610     unsigned long start_time;
0611     struct fsi_i2c_port *port = adap->algo_data;
0612     struct fsi_i2c_master *master = port->master;
0613     struct i2c_msg *msg;
0614 
0615     mutex_lock(&master->lock);
0616 
0617     rc = fsi_i2c_set_port(port);
0618     if (rc)
0619         goto unlock;
0620 
0621     for (i = 0; i < num; i++) {
0622         msg = msgs + i;
0623         start_time = jiffies;
0624 
0625         rc = fsi_i2c_start(port, msg, i == num - 1);
0626         if (rc)
0627             goto unlock;
0628 
0629         rc = fsi_i2c_wait(port, msg,
0630                   adap->timeout - (jiffies - start_time));
0631         if (rc)
0632             goto unlock;
0633     }
0634 
0635 unlock:
0636     mutex_unlock(&master->lock);
0637     return rc ? : num;
0638 }
0639 
0640 static u32 fsi_i2c_functionality(struct i2c_adapter *adap)
0641 {
0642     return I2C_FUNC_I2C | I2C_FUNC_PROTOCOL_MANGLING |
0643         I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA;
0644 }
0645 
0646 static struct i2c_bus_recovery_info fsi_i2c_bus_recovery_info = {
0647     .recover_bus = i2c_generic_scl_recovery,
0648     .get_scl = fsi_i2c_get_scl,
0649     .set_scl = fsi_i2c_set_scl,
0650     .get_sda = fsi_i2c_get_sda,
0651     .set_sda = fsi_i2c_set_sda,
0652     .prepare_recovery = fsi_i2c_prepare_recovery,
0653     .unprepare_recovery = fsi_i2c_unprepare_recovery,
0654 };
0655 
0656 static const struct i2c_algorithm fsi_i2c_algorithm = {
0657     .master_xfer = fsi_i2c_xfer,
0658     .functionality = fsi_i2c_functionality,
0659 };
0660 
0661 static struct device_node *fsi_i2c_find_port_of_node(struct device_node *fsi,
0662                              int port)
0663 {
0664     struct device_node *np;
0665     u32 port_no;
0666     int rc;
0667 
0668     for_each_child_of_node(fsi, np) {
0669         rc = of_property_read_u32(np, "reg", &port_no);
0670         if (!rc && port_no == port)
0671             return np;
0672     }
0673 
0674     return NULL;
0675 }
0676 
0677 static int fsi_i2c_probe(struct device *dev)
0678 {
0679     struct fsi_i2c_master *i2c;
0680     struct fsi_i2c_port *port;
0681     struct device_node *np;
0682     u32 port_no, ports, stat;
0683     int rc;
0684 
0685     i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
0686     if (!i2c)
0687         return -ENOMEM;
0688 
0689     mutex_init(&i2c->lock);
0690     i2c->fsi = to_fsi_dev(dev);
0691     INIT_LIST_HEAD(&i2c->ports);
0692 
0693     rc = fsi_i2c_dev_init(i2c);
0694     if (rc)
0695         return rc;
0696 
0697     rc = fsi_i2c_read_reg(i2c->fsi, I2C_FSI_STAT, &stat);
0698     if (rc)
0699         return rc;
0700 
0701     ports = FIELD_GET(I2C_STAT_MAX_PORT, stat) + 1;
0702     dev_dbg(dev, "I2C master has %d ports\n", ports);
0703 
0704     for (port_no = 0; port_no < ports; port_no++) {
0705         np = fsi_i2c_find_port_of_node(dev->of_node, port_no);
0706         if (!of_device_is_available(np))
0707             continue;
0708 
0709         port = kzalloc(sizeof(*port), GFP_KERNEL);
0710         if (!port) {
0711             of_node_put(np);
0712             break;
0713         }
0714 
0715         port->master = i2c;
0716         port->port = port_no;
0717 
0718         port->adapter.owner = THIS_MODULE;
0719         port->adapter.dev.of_node = np;
0720         port->adapter.dev.parent = dev;
0721         port->adapter.algo = &fsi_i2c_algorithm;
0722         port->adapter.bus_recovery_info = &fsi_i2c_bus_recovery_info;
0723         port->adapter.algo_data = port;
0724 
0725         snprintf(port->adapter.name, sizeof(port->adapter.name),
0726              "i2c_bus-%u", port_no);
0727 
0728         rc = i2c_add_adapter(&port->adapter);
0729         if (rc < 0) {
0730             dev_err(dev, "Failed to register adapter: %d\n", rc);
0731             kfree(port);
0732             continue;
0733         }
0734 
0735         list_add(&port->list, &i2c->ports);
0736     }
0737 
0738     dev_set_drvdata(dev, i2c);
0739 
0740     return 0;
0741 }
0742 
0743 static int fsi_i2c_remove(struct device *dev)
0744 {
0745     struct fsi_i2c_master *i2c = dev_get_drvdata(dev);
0746     struct fsi_i2c_port *port, *tmp;
0747 
0748     list_for_each_entry_safe(port, tmp, &i2c->ports, list) {
0749         list_del(&port->list);
0750         i2c_del_adapter(&port->adapter);
0751         kfree(port);
0752     }
0753 
0754     return 0;
0755 }
0756 
0757 static const struct fsi_device_id fsi_i2c_ids[] = {
0758     { FSI_ENGID_I2C, FSI_VERSION_ANY },
0759     { }
0760 };
0761 
0762 static struct fsi_driver fsi_i2c_driver = {
0763     .id_table = fsi_i2c_ids,
0764     .drv = {
0765         .name = "i2c-fsi",
0766         .bus = &fsi_bus_type,
0767         .probe = fsi_i2c_probe,
0768         .remove = fsi_i2c_remove,
0769     },
0770 };
0771 
0772 module_fsi_driver(fsi_i2c_driver);
0773 
0774 MODULE_AUTHOR("Eddie James <eajames@us.ibm.com>");
0775 MODULE_DESCRIPTION("FSI attached I2C master");
0776 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!