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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
0004  *
0005  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
0006 */
0007 
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 
0011 #include <linux/i2c.h>
0012 #include <linux/time.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/delay.h>
0015 #include <linux/errno.h>
0016 #include <linux/err.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/clk.h>
0019 #include <linux/slab.h>
0020 #include <linux/io.h>
0021 #include <linux/of_address.h>
0022 #include <linux/of_device.h>
0023 #include <linux/of_irq.h>
0024 #include <linux/spinlock.h>
0025 
0026 /*
0027  * HSI2C controller from Samsung supports 2 modes of operation
0028  * 1. Auto mode: Where in master automatically controls the whole transaction
0029  * 2. Manual mode: Software controls the transaction by issuing commands
0030  *    START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
0031  *
0032  * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
0033  *
0034  * Special bits are available for both modes of operation to set commands
0035  * and for checking transfer status
0036  */
0037 
0038 /* Register Map */
0039 #define HSI2C_CTL       0x00
0040 #define HSI2C_FIFO_CTL      0x04
0041 #define HSI2C_TRAILIG_CTL   0x08
0042 #define HSI2C_CLK_CTL       0x0C
0043 #define HSI2C_CLK_SLOT      0x10
0044 #define HSI2C_INT_ENABLE    0x20
0045 #define HSI2C_INT_STATUS    0x24
0046 #define HSI2C_ERR_STATUS    0x2C
0047 #define HSI2C_FIFO_STATUS   0x30
0048 #define HSI2C_TX_DATA       0x34
0049 #define HSI2C_RX_DATA       0x38
0050 #define HSI2C_CONF      0x40
0051 #define HSI2C_AUTO_CONF     0x44
0052 #define HSI2C_TIMEOUT       0x48
0053 #define HSI2C_MANUAL_CMD    0x4C
0054 #define HSI2C_TRANS_STATUS  0x50
0055 #define HSI2C_TIMING_HS1    0x54
0056 #define HSI2C_TIMING_HS2    0x58
0057 #define HSI2C_TIMING_HS3    0x5C
0058 #define HSI2C_TIMING_FS1    0x60
0059 #define HSI2C_TIMING_FS2    0x64
0060 #define HSI2C_TIMING_FS3    0x68
0061 #define HSI2C_TIMING_SLA    0x6C
0062 #define HSI2C_ADDR      0x70
0063 
0064 /* I2C_CTL Register bits */
0065 #define HSI2C_FUNC_MODE_I2C         (1u << 0)
0066 #define HSI2C_MASTER                (1u << 3)
0067 #define HSI2C_RXCHON                (1u << 6)
0068 #define HSI2C_TXCHON                (1u << 7)
0069 #define HSI2C_SW_RST                (1u << 31)
0070 
0071 /* I2C_FIFO_CTL Register bits */
0072 #define HSI2C_RXFIFO_EN             (1u << 0)
0073 #define HSI2C_TXFIFO_EN             (1u << 1)
0074 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x)       ((x) << 4)
0075 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x)       ((x) << 16)
0076 
0077 /* I2C_TRAILING_CTL Register bits */
0078 #define HSI2C_TRAILING_COUNT            (0xf)
0079 
0080 /* I2C_INT_EN Register bits */
0081 #define HSI2C_INT_TX_ALMOSTEMPTY_EN     (1u << 0)
0082 #define HSI2C_INT_RX_ALMOSTFULL_EN      (1u << 1)
0083 #define HSI2C_INT_TRAILING_EN           (1u << 6)
0084 
0085 /* I2C_INT_STAT Register bits */
0086 #define HSI2C_INT_TX_ALMOSTEMPTY        (1u << 0)
0087 #define HSI2C_INT_RX_ALMOSTFULL         (1u << 1)
0088 #define HSI2C_INT_TX_UNDERRUN           (1u << 2)
0089 #define HSI2C_INT_TX_OVERRUN            (1u << 3)
0090 #define HSI2C_INT_RX_UNDERRUN           (1u << 4)
0091 #define HSI2C_INT_RX_OVERRUN            (1u << 5)
0092 #define HSI2C_INT_TRAILING          (1u << 6)
0093 #define HSI2C_INT_I2C               (1u << 9)
0094 
0095 #define HSI2C_INT_TRANS_DONE            (1u << 7)
0096 #define HSI2C_INT_TRANS_ABORT           (1u << 8)
0097 #define HSI2C_INT_NO_DEV_ACK            (1u << 9)
0098 #define HSI2C_INT_NO_DEV            (1u << 10)
0099 #define HSI2C_INT_TIMEOUT           (1u << 11)
0100 #define HSI2C_INT_I2C_TRANS         (HSI2C_INT_TRANS_DONE | \
0101                         HSI2C_INT_TRANS_ABORT | \
0102                         HSI2C_INT_NO_DEV_ACK |  \
0103                         HSI2C_INT_NO_DEV |  \
0104                         HSI2C_INT_TIMEOUT)
0105 
0106 /* I2C_FIFO_STAT Register bits */
0107 #define HSI2C_RX_FIFO_EMPTY         (1u << 24)
0108 #define HSI2C_RX_FIFO_FULL          (1u << 23)
0109 #define HSI2C_RX_FIFO_LVL(x)            ((x >> 16) & 0x7f)
0110 #define HSI2C_TX_FIFO_EMPTY         (1u << 8)
0111 #define HSI2C_TX_FIFO_FULL          (1u << 7)
0112 #define HSI2C_TX_FIFO_LVL(x)            ((x >> 0) & 0x7f)
0113 
0114 /* I2C_CONF Register bits */
0115 #define HSI2C_AUTO_MODE             (1u << 31)
0116 #define HSI2C_10BIT_ADDR_MODE           (1u << 30)
0117 #define HSI2C_HS_MODE               (1u << 29)
0118 
0119 /* I2C_AUTO_CONF Register bits */
0120 #define HSI2C_READ_WRITE            (1u << 16)
0121 #define HSI2C_STOP_AFTER_TRANS          (1u << 17)
0122 #define HSI2C_MASTER_RUN            (1u << 31)
0123 
0124 /* I2C_TIMEOUT Register bits */
0125 #define HSI2C_TIMEOUT_EN            (1u << 31)
0126 #define HSI2C_TIMEOUT_MASK          0xff
0127 
0128 /* I2C_MANUAL_CMD register bits */
0129 #define HSI2C_CMD_READ_DATA         (1u << 4)
0130 #define HSI2C_CMD_SEND_STOP         (1u << 2)
0131 
0132 /* I2C_TRANS_STATUS register bits */
0133 #define HSI2C_MASTER_BUSY           (1u << 17)
0134 #define HSI2C_SLAVE_BUSY            (1u << 16)
0135 
0136 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
0137 #define HSI2C_TIMEOUT_AUTO          (1u << 4)
0138 #define HSI2C_NO_DEV                (1u << 3)
0139 #define HSI2C_NO_DEV_ACK            (1u << 2)
0140 #define HSI2C_TRANS_ABORT           (1u << 1)
0141 #define HSI2C_TRANS_DONE            (1u << 0)
0142 
0143 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
0144 #define HSI2C_MASTER_ST_MASK            0xf
0145 #define HSI2C_MASTER_ST_IDLE            0x0
0146 #define HSI2C_MASTER_ST_START           0x1
0147 #define HSI2C_MASTER_ST_RESTART         0x2
0148 #define HSI2C_MASTER_ST_STOP            0x3
0149 #define HSI2C_MASTER_ST_MASTER_ID       0x4
0150 #define HSI2C_MASTER_ST_ADDR0           0x5
0151 #define HSI2C_MASTER_ST_ADDR1           0x6
0152 #define HSI2C_MASTER_ST_ADDR2           0x7
0153 #define HSI2C_MASTER_ST_ADDR_SR         0x8
0154 #define HSI2C_MASTER_ST_READ            0x9
0155 #define HSI2C_MASTER_ST_WRITE           0xa
0156 #define HSI2C_MASTER_ST_NO_ACK          0xb
0157 #define HSI2C_MASTER_ST_LOSE            0xc
0158 #define HSI2C_MASTER_ST_WAIT            0xd
0159 #define HSI2C_MASTER_ST_WAIT_CMD        0xe
0160 
0161 /* I2C_ADDR register bits */
0162 #define HSI2C_SLV_ADDR_SLV(x)           ((x & 0x3ff) << 0)
0163 #define HSI2C_SLV_ADDR_MAS(x)           ((x & 0x3ff) << 10)
0164 #define HSI2C_MASTER_ID(x)          ((x & 0xff) << 24)
0165 #define MASTER_ID(x)                ((x & 0x7) + 0x08)
0166 
0167 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
0168 
0169 enum i2c_type_exynos {
0170     I2C_TYPE_EXYNOS5,
0171     I2C_TYPE_EXYNOS7,
0172     I2C_TYPE_EXYNOSAUTOV9,
0173 };
0174 
0175 struct exynos5_i2c {
0176     struct i2c_adapter  adap;
0177 
0178     struct i2c_msg      *msg;
0179     struct completion   msg_complete;
0180     unsigned int        msg_ptr;
0181 
0182     unsigned int        irq;
0183 
0184     void __iomem        *regs;
0185     struct clk      *clk;       /* operating clock */
0186     struct clk      *pclk;      /* bus clock */
0187     struct device       *dev;
0188     int         state;
0189 
0190     spinlock_t      lock;       /* IRQ synchronization */
0191 
0192     /*
0193      * Since the TRANS_DONE bit is cleared on read, and we may read it
0194      * either during an IRQ or after a transaction, keep track of its
0195      * state here.
0196      */
0197     int         trans_done;
0198 
0199     /* Controller operating frequency */
0200     unsigned int        op_clock;
0201 
0202     /* Version of HS-I2C Hardware */
0203     const struct exynos_hsi2c_variant *variant;
0204 };
0205 
0206 /**
0207  * struct exynos_hsi2c_variant - platform specific HSI2C driver data
0208  * @fifo_depth: the fifo depth supported by the HSI2C module
0209  * @hw: the hardware variant of Exynos I2C controller
0210  *
0211  * Specifies platform specific configuration of HSI2C module.
0212  * Note: A structure for driver specific platform data is used for future
0213  * expansion of its usage.
0214  */
0215 struct exynos_hsi2c_variant {
0216     unsigned int        fifo_depth;
0217     enum i2c_type_exynos    hw;
0218 };
0219 
0220 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
0221     .fifo_depth = 64,
0222     .hw     = I2C_TYPE_EXYNOS5,
0223 };
0224 
0225 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
0226     .fifo_depth = 16,
0227     .hw     = I2C_TYPE_EXYNOS5,
0228 };
0229 
0230 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
0231     .fifo_depth = 16,
0232     .hw     = I2C_TYPE_EXYNOS7,
0233 };
0234 
0235 static const struct exynos_hsi2c_variant exynosautov9_hsi2c_data = {
0236     .fifo_depth = 64,
0237     .hw     = I2C_TYPE_EXYNOSAUTOV9,
0238 };
0239 
0240 static const struct of_device_id exynos5_i2c_match[] = {
0241     {
0242         .compatible = "samsung,exynos5-hsi2c",
0243         .data = &exynos5250_hsi2c_data
0244     }, {
0245         .compatible = "samsung,exynos5250-hsi2c",
0246         .data = &exynos5250_hsi2c_data
0247     }, {
0248         .compatible = "samsung,exynos5260-hsi2c",
0249         .data = &exynos5260_hsi2c_data
0250     }, {
0251         .compatible = "samsung,exynos7-hsi2c",
0252         .data = &exynos7_hsi2c_data
0253     }, {
0254         .compatible = "samsung,exynosautov9-hsi2c",
0255         .data = &exynosautov9_hsi2c_data
0256     }, {},
0257 };
0258 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
0259 
0260 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
0261 {
0262     writel(readl(i2c->regs + HSI2C_INT_STATUS),
0263                 i2c->regs + HSI2C_INT_STATUS);
0264 }
0265 
0266 /*
0267  * exynos5_i2c_set_timing: updates the registers with appropriate
0268  * timing values calculated
0269  *
0270  * Timing values for operation are calculated against either 100kHz
0271  * or 1MHz controller operating frequency.
0272  *
0273  * Returns 0 on success, -EINVAL if the cycle length cannot
0274  * be calculated.
0275  */
0276 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
0277 {
0278     u32 i2c_timing_s1;
0279     u32 i2c_timing_s2;
0280     u32 i2c_timing_s3;
0281     u32 i2c_timing_sla;
0282     unsigned int t_start_su, t_start_hd;
0283     unsigned int t_stop_su;
0284     unsigned int t_data_su, t_data_hd;
0285     unsigned int t_scl_l, t_scl_h;
0286     unsigned int t_sr_release;
0287     unsigned int t_ftl_cycle;
0288     unsigned int clkin = clk_get_rate(i2c->clk);
0289     unsigned int op_clk = hs_timings ? i2c->op_clock :
0290         (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ :
0291         i2c->op_clock;
0292     int div, clk_cycle, temp;
0293 
0294     /*
0295      * In case of HSI2C controllers in ExynosAutoV9:
0296      *
0297      * FSCL = IPCLK / ((CLK_DIV + 1) * 16)
0298      * T_SCL_LOW = IPCLK * (CLK_DIV + 1) * (N + M)
0299      *   [N : number of 0's in the TSCL_H_HS]
0300      *   [M : number of 0's in the TSCL_L_HS]
0301      * T_SCL_HIGH = IPCLK * (CLK_DIV + 1) * (N + M)
0302      *   [N : number of 1's in the TSCL_H_HS]
0303      *   [M : number of 1's in the TSCL_L_HS]
0304      *
0305      * Result of (N + M) is always 8.
0306      * In general case, we don't need to control timing_s1 and timing_s2.
0307      */
0308     if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) {
0309         div = ((clkin / (16 * i2c->op_clock)) - 1);
0310         i2c_timing_s3 = div << 16;
0311         if (hs_timings)
0312             writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
0313         else
0314             writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
0315 
0316         return 0;
0317     }
0318 
0319     /*
0320      * In case of HSI2C controller in Exynos5 series
0321      * FPCLK / FI2C =
0322      * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
0323      *
0324      * In case of HSI2C controllers in Exynos7 series
0325      * FPCLK / FI2C =
0326      * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
0327      *
0328      * clk_cycle := TSCLK_L + TSCLK_H
0329      * temp := (CLK_DIV + 1) * (clk_cycle + 2)
0330      *
0331      * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
0332      *
0333      */
0334     t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
0335     temp = clkin / op_clk - 8 - t_ftl_cycle;
0336     if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
0337         temp -= t_ftl_cycle;
0338     div = temp / 512;
0339     clk_cycle = temp / (div + 1) - 2;
0340     if (temp < 4 || div >= 256 || clk_cycle < 2) {
0341         dev_err(i2c->dev, "%s clock set-up failed\n",
0342             hs_timings ? "HS" : "FS");
0343         return -EINVAL;
0344     }
0345 
0346     t_scl_l = clk_cycle / 2;
0347     t_scl_h = clk_cycle / 2;
0348     t_start_su = t_scl_l;
0349     t_start_hd = t_scl_l;
0350     t_stop_su = t_scl_l;
0351     t_data_su = t_scl_l / 2;
0352     t_data_hd = t_scl_l / 2;
0353     t_sr_release = clk_cycle;
0354 
0355     i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
0356     i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
0357     i2c_timing_s3 = div << 16 | t_sr_release << 0;
0358     i2c_timing_sla = t_data_hd << 0;
0359 
0360     dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
0361         t_start_su, t_start_hd, t_stop_su);
0362     dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
0363         t_data_su, t_scl_l, t_scl_h);
0364     dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
0365         div, t_sr_release);
0366     dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
0367 
0368     if (hs_timings) {
0369         writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
0370         writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
0371         writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
0372     } else {
0373         writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
0374         writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
0375         writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
0376     }
0377     writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
0378 
0379     return 0;
0380 }
0381 
0382 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
0383 {
0384     /* always set Fast Speed timings */
0385     int ret = exynos5_i2c_set_timing(i2c, false);
0386 
0387     if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ)
0388         return ret;
0389 
0390     return exynos5_i2c_set_timing(i2c, true);
0391 }
0392 
0393 /*
0394  * exynos5_i2c_init: configures the controller for I2C functionality
0395  * Programs I2C controller for Master mode operation
0396  */
0397 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
0398 {
0399     u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
0400     u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
0401 
0402     /* Clear to disable Timeout */
0403     i2c_timeout &= ~HSI2C_TIMEOUT_EN;
0404     writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
0405 
0406     writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
0407                     i2c->regs + HSI2C_CTL);
0408     writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
0409 
0410     if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) {
0411         writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
0412                     i2c->regs + HSI2C_ADDR);
0413         i2c_conf |= HSI2C_HS_MODE;
0414     }
0415 
0416     writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
0417 }
0418 
0419 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
0420 {
0421     u32 i2c_ctl;
0422 
0423     /* Set and clear the bit for reset */
0424     i2c_ctl = readl(i2c->regs + HSI2C_CTL);
0425     i2c_ctl |= HSI2C_SW_RST;
0426     writel(i2c_ctl, i2c->regs + HSI2C_CTL);
0427 
0428     i2c_ctl = readl(i2c->regs + HSI2C_CTL);
0429     i2c_ctl &= ~HSI2C_SW_RST;
0430     writel(i2c_ctl, i2c->regs + HSI2C_CTL);
0431 
0432     /* We don't expect calculations to fail during the run */
0433     exynos5_hsi2c_clock_setup(i2c);
0434     /* Initialize the configure registers */
0435     exynos5_i2c_init(i2c);
0436 }
0437 
0438 /*
0439  * exynos5_i2c_irq: top level IRQ servicing routine
0440  *
0441  * INT_STATUS registers gives the interrupt details. Further,
0442  * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
0443  * state of the bus.
0444  */
0445 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
0446 {
0447     struct exynos5_i2c *i2c = dev_id;
0448     u32 fifo_level, int_status, fifo_status, trans_status;
0449     unsigned char byte;
0450     int len = 0;
0451 
0452     i2c->state = -EINVAL;
0453 
0454     spin_lock(&i2c->lock);
0455 
0456     int_status = readl(i2c->regs + HSI2C_INT_STATUS);
0457     writel(int_status, i2c->regs + HSI2C_INT_STATUS);
0458 
0459     /* handle interrupt related to the transfer status */
0460     switch (i2c->variant->hw) {
0461     case I2C_TYPE_EXYNOSAUTOV9:
0462         fallthrough;
0463     case I2C_TYPE_EXYNOS7:
0464         if (int_status & HSI2C_INT_TRANS_DONE) {
0465             i2c->trans_done = 1;
0466             i2c->state = 0;
0467         } else if (int_status & HSI2C_INT_TRANS_ABORT) {
0468             dev_dbg(i2c->dev, "Deal with arbitration lose\n");
0469             i2c->state = -EAGAIN;
0470             goto stop;
0471         } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
0472             dev_dbg(i2c->dev, "No ACK from device\n");
0473             i2c->state = -ENXIO;
0474             goto stop;
0475         } else if (int_status & HSI2C_INT_NO_DEV) {
0476             dev_dbg(i2c->dev, "No device\n");
0477             i2c->state = -ENXIO;
0478             goto stop;
0479         } else if (int_status & HSI2C_INT_TIMEOUT) {
0480             dev_dbg(i2c->dev, "Accessing device timed out\n");
0481             i2c->state = -ETIMEDOUT;
0482             goto stop;
0483         }
0484 
0485         break;
0486     case I2C_TYPE_EXYNOS5:
0487         if (!(int_status & HSI2C_INT_I2C))
0488             break;
0489 
0490         trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
0491         if (trans_status & HSI2C_NO_DEV_ACK) {
0492             dev_dbg(i2c->dev, "No ACK from device\n");
0493             i2c->state = -ENXIO;
0494             goto stop;
0495         } else if (trans_status & HSI2C_NO_DEV) {
0496             dev_dbg(i2c->dev, "No device\n");
0497             i2c->state = -ENXIO;
0498             goto stop;
0499         } else if (trans_status & HSI2C_TRANS_ABORT) {
0500             dev_dbg(i2c->dev, "Deal with arbitration lose\n");
0501             i2c->state = -EAGAIN;
0502             goto stop;
0503         } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
0504             dev_dbg(i2c->dev, "Accessing device timed out\n");
0505             i2c->state = -ETIMEDOUT;
0506             goto stop;
0507         } else if (trans_status & HSI2C_TRANS_DONE) {
0508             i2c->trans_done = 1;
0509             i2c->state = 0;
0510         }
0511 
0512         break;
0513     }
0514 
0515     if ((i2c->msg->flags & I2C_M_RD) && (int_status &
0516             (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
0517         fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
0518         fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
0519         len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
0520 
0521         while (len > 0) {
0522             byte = (unsigned char)
0523                 readl(i2c->regs + HSI2C_RX_DATA);
0524             i2c->msg->buf[i2c->msg_ptr++] = byte;
0525             len--;
0526         }
0527         i2c->state = 0;
0528     } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
0529         fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
0530         fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
0531 
0532         len = i2c->variant->fifo_depth - fifo_level;
0533         if (len > (i2c->msg->len - i2c->msg_ptr)) {
0534             u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
0535 
0536             int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
0537             writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
0538             len = i2c->msg->len - i2c->msg_ptr;
0539         }
0540 
0541         while (len > 0) {
0542             byte = i2c->msg->buf[i2c->msg_ptr++];
0543             writel(byte, i2c->regs + HSI2C_TX_DATA);
0544             len--;
0545         }
0546         i2c->state = 0;
0547     }
0548 
0549  stop:
0550     if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
0551         (i2c->state < 0)) {
0552         writel(0, i2c->regs + HSI2C_INT_ENABLE);
0553         exynos5_i2c_clr_pend_irq(i2c);
0554         complete(&i2c->msg_complete);
0555     }
0556 
0557     spin_unlock(&i2c->lock);
0558 
0559     return IRQ_HANDLED;
0560 }
0561 
0562 /*
0563  * exynos5_i2c_wait_bus_idle
0564  *
0565  * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
0566  * cleared.
0567  *
0568  * Returns -EBUSY if the bus cannot be bought to idle
0569  */
0570 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
0571 {
0572     unsigned long stop_time;
0573     u32 trans_status;
0574 
0575     /* wait for 100 milli seconds for the bus to be idle */
0576     stop_time = jiffies + msecs_to_jiffies(100) + 1;
0577     do {
0578         trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
0579         if (!(trans_status & HSI2C_MASTER_BUSY))
0580             return 0;
0581 
0582         usleep_range(50, 200);
0583     } while (time_before(jiffies, stop_time));
0584 
0585     return -EBUSY;
0586 }
0587 
0588 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
0589 {
0590     u32 val;
0591 
0592     val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;
0593     writel(val, i2c->regs + HSI2C_CTL);
0594     val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;
0595     writel(val, i2c->regs + HSI2C_CONF);
0596 
0597     /*
0598      * Specification says master should send nine clock pulses. It can be
0599      * emulated by sending manual read command (nine pulses for read eight
0600      * bits + one pulse for NACK).
0601      */
0602     writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
0603     exynos5_i2c_wait_bus_idle(i2c);
0604     writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
0605     exynos5_i2c_wait_bus_idle(i2c);
0606 
0607     val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;
0608     writel(val, i2c->regs + HSI2C_CTL);
0609     val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;
0610     writel(val, i2c->regs + HSI2C_CONF);
0611 }
0612 
0613 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
0614 {
0615     unsigned long timeout;
0616 
0617     if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
0618         return;
0619 
0620     /*
0621      * HSI2C_MASTER_ST_LOSE state (in Exynos7 and ExynosAutoV9 variants)
0622      * before transaction indicates that bus is stuck (SDA is low).
0623      * In such case bus recovery can be performed.
0624      */
0625     timeout = jiffies + msecs_to_jiffies(100);
0626     for (;;) {
0627         u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);
0628 
0629         if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE)
0630             return;
0631 
0632         if (time_is_before_jiffies(timeout))
0633             return;
0634 
0635         exynos5_i2c_bus_recover(i2c);
0636     }
0637 }
0638 
0639 /*
0640  * exynos5_i2c_message_start: Configures the bus and starts the xfer
0641  * i2c: struct exynos5_i2c pointer for the current bus
0642  * stop: Enables stop after transfer if set. Set for last transfer of
0643  *       in the list of messages.
0644  *
0645  * Configures the bus for read/write function
0646  * Sets chip address to talk to, message length to be sent.
0647  * Enables appropriate interrupts and sends start xfer command.
0648  */
0649 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
0650 {
0651     u32 i2c_ctl;
0652     u32 int_en = 0;
0653     u32 i2c_auto_conf = 0;
0654     u32 i2c_addr = 0;
0655     u32 fifo_ctl;
0656     unsigned long flags;
0657     unsigned short trig_lvl;
0658 
0659     if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
0660         int_en |= HSI2C_INT_I2C;
0661     else
0662         int_en |= HSI2C_INT_I2C_TRANS;
0663 
0664     i2c_ctl = readl(i2c->regs + HSI2C_CTL);
0665     i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
0666     fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
0667 
0668     if (i2c->msg->flags & I2C_M_RD) {
0669         i2c_ctl |= HSI2C_RXCHON;
0670 
0671         i2c_auto_conf |= HSI2C_READ_WRITE;
0672 
0673         trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
0674             (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
0675         fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
0676 
0677         int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
0678             HSI2C_INT_TRAILING_EN);
0679     } else {
0680         i2c_ctl |= HSI2C_TXCHON;
0681 
0682         trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
0683             (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
0684         fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
0685 
0686         int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
0687     }
0688 
0689     i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr);
0690 
0691     if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ)
0692         i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr));
0693 
0694     writel(i2c_addr, i2c->regs + HSI2C_ADDR);
0695 
0696     writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
0697     writel(i2c_ctl, i2c->regs + HSI2C_CTL);
0698 
0699     exynos5_i2c_bus_check(i2c);
0700 
0701     /*
0702      * Enable interrupts before starting the transfer so that we don't
0703      * miss any INT_I2C interrupts.
0704      */
0705     spin_lock_irqsave(&i2c->lock, flags);
0706     writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
0707 
0708     if (stop == 1)
0709         i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
0710     i2c_auto_conf |= i2c->msg->len;
0711     i2c_auto_conf |= HSI2C_MASTER_RUN;
0712     writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
0713     spin_unlock_irqrestore(&i2c->lock, flags);
0714 }
0715 
0716 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
0717                   struct i2c_msg *msgs, int stop)
0718 {
0719     unsigned long timeout;
0720     int ret;
0721 
0722     i2c->msg = msgs;
0723     i2c->msg_ptr = 0;
0724     i2c->trans_done = 0;
0725 
0726     reinit_completion(&i2c->msg_complete);
0727 
0728     exynos5_i2c_message_start(i2c, stop);
0729 
0730     timeout = wait_for_completion_timeout(&i2c->msg_complete,
0731                           EXYNOS5_I2C_TIMEOUT);
0732     if (timeout == 0)
0733         ret = -ETIMEDOUT;
0734     else
0735         ret = i2c->state;
0736 
0737     /*
0738      * If this is the last message to be transfered (stop == 1)
0739      * Then check if the bus can be brought back to idle.
0740      */
0741     if (ret == 0 && stop)
0742         ret = exynos5_i2c_wait_bus_idle(i2c);
0743 
0744     if (ret < 0) {
0745         exynos5_i2c_reset(i2c);
0746         if (ret == -ETIMEDOUT)
0747             dev_warn(i2c->dev, "%s timeout\n",
0748                  (msgs->flags & I2C_M_RD) ? "rx" : "tx");
0749     }
0750 
0751     /* Return the state as in interrupt routine */
0752     return ret;
0753 }
0754 
0755 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
0756             struct i2c_msg *msgs, int num)
0757 {
0758     struct exynos5_i2c *i2c = adap->algo_data;
0759     int i, ret;
0760 
0761     ret = clk_enable(i2c->pclk);
0762     if (ret)
0763         return ret;
0764 
0765     ret = clk_enable(i2c->clk);
0766     if (ret)
0767         goto err_pclk;
0768 
0769     for (i = 0; i < num; ++i) {
0770         ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);
0771         if (ret)
0772             break;
0773     }
0774 
0775     clk_disable(i2c->clk);
0776 err_pclk:
0777     clk_disable(i2c->pclk);
0778 
0779     return ret ?: num;
0780 }
0781 
0782 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
0783 {
0784     return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
0785 }
0786 
0787 static const struct i2c_algorithm exynos5_i2c_algorithm = {
0788     .master_xfer        = exynos5_i2c_xfer,
0789     .functionality      = exynos5_i2c_func,
0790 };
0791 
0792 static int exynos5_i2c_probe(struct platform_device *pdev)
0793 {
0794     struct device_node *np = pdev->dev.of_node;
0795     struct exynos5_i2c *i2c;
0796     int ret;
0797 
0798     i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
0799     if (!i2c)
0800         return -ENOMEM;
0801 
0802     if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
0803         i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
0804 
0805     strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
0806     i2c->adap.owner   = THIS_MODULE;
0807     i2c->adap.algo    = &exynos5_i2c_algorithm;
0808     i2c->adap.retries = 3;
0809 
0810     i2c->dev = &pdev->dev;
0811     i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
0812     if (IS_ERR(i2c->clk)) {
0813         dev_err(&pdev->dev, "cannot get clock\n");
0814         return -ENOENT;
0815     }
0816 
0817     i2c->pclk = devm_clk_get_optional(&pdev->dev, "hsi2c_pclk");
0818     if (IS_ERR(i2c->pclk)) {
0819         return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),
0820                      "cannot get pclk");
0821     }
0822 
0823     ret = clk_prepare_enable(i2c->pclk);
0824     if (ret)
0825         return ret;
0826 
0827     ret = clk_prepare_enable(i2c->clk);
0828     if (ret)
0829         goto err_pclk;
0830 
0831     i2c->regs = devm_platform_ioremap_resource(pdev, 0);
0832     if (IS_ERR(i2c->regs)) {
0833         ret = PTR_ERR(i2c->regs);
0834         goto err_clk;
0835     }
0836 
0837     i2c->adap.dev.of_node = np;
0838     i2c->adap.algo_data = i2c;
0839     i2c->adap.dev.parent = &pdev->dev;
0840 
0841     /* Clear pending interrupts from u-boot or misc causes */
0842     exynos5_i2c_clr_pend_irq(i2c);
0843 
0844     spin_lock_init(&i2c->lock);
0845     init_completion(&i2c->msg_complete);
0846 
0847     i2c->irq = ret = platform_get_irq(pdev, 0);
0848     if (ret < 0)
0849         goto err_clk;
0850 
0851     ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
0852                    IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);
0853     if (ret != 0) {
0854         dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
0855         goto err_clk;
0856     }
0857 
0858     i2c->variant = of_device_get_match_data(&pdev->dev);
0859 
0860     ret = exynos5_hsi2c_clock_setup(i2c);
0861     if (ret)
0862         goto err_clk;
0863 
0864     exynos5_i2c_reset(i2c);
0865 
0866     ret = i2c_add_adapter(&i2c->adap);
0867     if (ret < 0)
0868         goto err_clk;
0869 
0870     platform_set_drvdata(pdev, i2c);
0871 
0872     clk_disable(i2c->clk);
0873     clk_disable(i2c->pclk);
0874 
0875     return 0;
0876 
0877  err_clk:
0878     clk_disable_unprepare(i2c->clk);
0879 
0880  err_pclk:
0881     clk_disable_unprepare(i2c->pclk);
0882     return ret;
0883 }
0884 
0885 static int exynos5_i2c_remove(struct platform_device *pdev)
0886 {
0887     struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
0888 
0889     i2c_del_adapter(&i2c->adap);
0890 
0891     clk_unprepare(i2c->clk);
0892     clk_unprepare(i2c->pclk);
0893 
0894     return 0;
0895 }
0896 
0897 #ifdef CONFIG_PM_SLEEP
0898 static int exynos5_i2c_suspend_noirq(struct device *dev)
0899 {
0900     struct exynos5_i2c *i2c = dev_get_drvdata(dev);
0901 
0902     i2c_mark_adapter_suspended(&i2c->adap);
0903     clk_unprepare(i2c->clk);
0904     clk_unprepare(i2c->pclk);
0905 
0906     return 0;
0907 }
0908 
0909 static int exynos5_i2c_resume_noirq(struct device *dev)
0910 {
0911     struct exynos5_i2c *i2c = dev_get_drvdata(dev);
0912     int ret = 0;
0913 
0914     ret = clk_prepare_enable(i2c->pclk);
0915     if (ret)
0916         return ret;
0917 
0918     ret = clk_prepare_enable(i2c->clk);
0919     if (ret)
0920         goto err_pclk;
0921 
0922     ret = exynos5_hsi2c_clock_setup(i2c);
0923     if (ret)
0924         goto err_clk;
0925 
0926     exynos5_i2c_init(i2c);
0927     clk_disable(i2c->clk);
0928     clk_disable(i2c->pclk);
0929     i2c_mark_adapter_resumed(&i2c->adap);
0930 
0931     return 0;
0932 
0933 err_clk:
0934     clk_disable_unprepare(i2c->clk);
0935 err_pclk:
0936     clk_disable_unprepare(i2c->pclk);
0937     return ret;
0938 }
0939 #endif
0940 
0941 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
0942     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
0943                       exynos5_i2c_resume_noirq)
0944 };
0945 
0946 static struct platform_driver exynos5_i2c_driver = {
0947     .probe      = exynos5_i2c_probe,
0948     .remove     = exynos5_i2c_remove,
0949     .driver     = {
0950         .name   = "exynos5-hsi2c",
0951         .pm = &exynos5_i2c_dev_pm_ops,
0952         .of_match_table = exynos5_i2c_match,
0953     },
0954 };
0955 
0956 module_platform_driver(exynos5_i2c_driver);
0957 
0958 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
0959 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
0960 MODULE_AUTHOR("Taekgyun Ko <taeggyun.ko@samsung.com>");
0961 MODULE_LICENSE("GPL v2");
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